[mirror_ubuntu-jammy-kernel.git] / drivers / remoteproc / imx_rproc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mailbox_client.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_reserved_mem.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/remoteproc.h>
#include <linux/workqueue.h>

#include "remoteproc_internal.h"

#define IMX7D_SRC_SCR			0x0C
#define IMX7D_ENABLE_M4			BIT(3)
#define IMX7D_SW_M4P_RST		BIT(2)
#define IMX7D_SW_M4C_RST		BIT(1)
#define IMX7D_SW_M4C_NON_SCLR_RST	BIT(0)

#define IMX7D_M4_RST_MASK		(IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
					 | IMX7D_SW_M4C_RST \
					 | IMX7D_SW_M4C_NON_SCLR_RST)

#define IMX7D_M4_START			(IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
					 | IMX7D_SW_M4C_RST)
#define IMX7D_M4_STOP			IMX7D_SW_M4C_NON_SCLR_RST

/* Address: 0x020D8000 */
#define IMX6SX_SRC_SCR			0x00
#define IMX6SX_ENABLE_M4		BIT(22)
#define IMX6SX_SW_M4P_RST		BIT(12)
#define IMX6SX_SW_M4C_NON_SCLR_RST	BIT(4)
#define IMX6SX_SW_M4C_RST		BIT(3)

#define IMX6SX_M4_START			(IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
					 | IMX6SX_SW_M4C_RST)
#define IMX6SX_M4_STOP			IMX6SX_SW_M4C_NON_SCLR_RST
#define IMX6SX_M4_RST_MASK		(IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
					 | IMX6SX_SW_M4C_NON_SCLR_RST \
					 | IMX6SX_SW_M4C_RST)

#define IMX7D_RPROC_MEM_MAX		8

/**
 * struct imx_rproc_mem - slim internal memory structure
 * @cpu_addr: MPU virtual address of the memory region
 * @sys_addr: Bus address used to access the memory region
 * @size: Size of the memory region
 */
struct imx_rproc_mem {
	void __iomem *cpu_addr;
	phys_addr_t sys_addr;
	size_t size;
};

/* att flags */
/* M4 own area. Can be mapped at probe */
#define ATT_OWN		BIT(1)

/* address translation table */
struct imx_rproc_att {
	u32 da;	/* device address (From Cortex M4 view)*/
	u32 sa;	/* system bus address */
	u32 size; /* size of reg range */
	int flags;
};

struct imx_rproc_dcfg {
	u32				src_reg;
	u32				src_mask;
	u32				src_start;
	u32				src_stop;
	const struct imx_rproc_att	*att;
	size_t				att_size;
};

struct imx_rproc {
	struct device			*dev;
	struct regmap			*regmap;
	struct rproc			*rproc;
	const struct imx_rproc_dcfg	*dcfg;
	struct imx_rproc_mem		mem[IMX7D_RPROC_MEM_MAX];
	struct clk			*clk;
	struct mbox_client		cl;
	struct mbox_chan		*tx_ch;
	struct mbox_chan		*rx_ch;
	struct work_struct		rproc_work;
	struct workqueue_struct		*workqueue;
};

static const struct imx_rproc_att imx_rproc_att_imx8mq[] = {
	/* dev addr , sys addr  , size	    , flags */
	/* TCML - alias */
	{ 0x00000000, 0x007e0000, 0x00020000, 0 },
	/* OCRAM_S */
	{ 0x00180000, 0x00180000, 0x00008000, 0 },
	/* OCRAM */
	{ 0x00900000, 0x00900000, 0x00020000, 0 },
	/* OCRAM */
	{ 0x00920000, 0x00920000, 0x00020000, 0 },
	/* QSPI Code - alias */
	{ 0x08000000, 0x08000000, 0x08000000, 0 },
	/* DDR (Code) - alias */
	{ 0x10000000, 0x80000000, 0x0FFE0000, 0 },
	/* TCML */
	{ 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN },
	/* TCMU */
	{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN },
	/* OCRAM_S */
	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
	/* OCRAM */
	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
	/* OCRAM */
	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
	/* DDR (Data) */
	{ 0x40000000, 0x40000000, 0x80000000, 0 },
};

static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
	/* dev addr , sys addr  , size	    , flags */
	/* OCRAM_S (M4 Boot code) - alias */
	{ 0x00000000, 0x00180000, 0x00008000, 0 },
	/* OCRAM_S (Code) */
	{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
	/* OCRAM (Code) - alias */
	{ 0x00900000, 0x00900000, 0x00020000, 0 },
	/* OCRAM_EPDC (Code) - alias */
	{ 0x00920000, 0x00920000, 0x00020000, 0 },
	/* OCRAM_PXP (Code) - alias */
	{ 0x00940000, 0x00940000, 0x00008000, 0 },
	/* TCML (Code) */
	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
	/* DDR (Code) - alias, first part of DDR (Data) */
	{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },

	/* TCMU (Data) */
	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
	/* OCRAM (Data) */
	{ 0x20200000, 0x00900000, 0x00020000, 0 },
	/* OCRAM_EPDC (Data) */
	{ 0x20220000, 0x00920000, 0x00020000, 0 },
	/* OCRAM_PXP (Data) */
	{ 0x20240000, 0x00940000, 0x00008000, 0 },
	/* DDR (Data) */
	{ 0x80000000, 0x80000000, 0x60000000, 0 },
};

static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
	/* dev addr , sys addr  , size	    , flags */
	/* TCML (M4 Boot Code) - alias */
	{ 0x00000000, 0x007F8000, 0x00008000, 0 },
	/* OCRAM_S (Code) */
	{ 0x00180000, 0x008F8000, 0x00004000, 0 },
	/* OCRAM_S (Code) - alias */
	{ 0x00180000, 0x008FC000, 0x00004000, 0 },
	/* TCML (Code) */
	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
	/* DDR (Code) - alias, first part of DDR (Data) */
	{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },

	/* TCMU (Data) */
	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
	/* OCRAM_S (Data) - alias? */
	{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
	/* DDR (Data) */
	{ 0x80000000, 0x80000000, 0x60000000, 0 },
};

static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = {
	.src_reg	= IMX7D_SRC_SCR,
	.src_mask	= IMX7D_M4_RST_MASK,
	.src_start	= IMX7D_M4_START,
	.src_stop	= IMX7D_M4_STOP,
	.att		= imx_rproc_att_imx8mq,
	.att_size	= ARRAY_SIZE(imx_rproc_att_imx8mq),
};

static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = {
	.src_reg	= IMX7D_SRC_SCR,
	.src_mask	= IMX7D_M4_RST_MASK,
	.src_start	= IMX7D_M4_START,
	.src_stop	= IMX7D_M4_STOP,
	.att		= imx_rproc_att_imx7d,
	.att_size	= ARRAY_SIZE(imx_rproc_att_imx7d),
};

static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = {
	.src_reg	= IMX6SX_SRC_SCR,
	.src_mask	= IMX6SX_M4_RST_MASK,
	.src_start	= IMX6SX_M4_START,
	.src_stop	= IMX6SX_M4_STOP,
	.att		= imx_rproc_att_imx6sx,
	.att_size	= ARRAY_SIZE(imx_rproc_att_imx6sx),
};

static int imx_rproc_start(struct rproc *rproc)
{
	struct imx_rproc *priv = rproc->priv;
	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	struct device *dev = priv->dev;
	int ret;

	ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
				 dcfg->src_mask, dcfg->src_start);
	if (ret)
		dev_err(dev, "Failed to enable M4!\n");

	return ret;
}

static int imx_rproc_stop(struct rproc *rproc)
{
	struct imx_rproc *priv = rproc->priv;
	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	struct device *dev = priv->dev;
	int ret;

	ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
				 dcfg->src_mask, dcfg->src_stop);
	if (ret)
		dev_err(dev, "Failed to stop M4!\n");

	return ret;
}

static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
			       size_t len, u64 *sys)
{
	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	int i;

	/* parse address translation table */
	for (i = 0; i < dcfg->att_size; i++) {
		const struct imx_rproc_att *att = &dcfg->att[i];

		if (da >= att->da && da + len < att->da + att->size) {
			unsigned int offset = da - att->da;

			*sys = att->sa + offset;
			return 0;
		}
	}

	dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",
		 da, len);
	return -ENOENT;
}

static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
{
	struct imx_rproc *priv = rproc->priv;
	void *va = NULL;
	u64 sys;
	int i;

	if (len == 0)
		return NULL;

	/*
	 * On device side we have many aliases, so we need to convert device
	 * address (M4) to system bus address first.
	 */
	if (imx_rproc_da_to_sys(priv, da, len, &sys))
		return NULL;

	for (i = 0; i < IMX7D_RPROC_MEM_MAX; i++) {
		if (sys >= priv->mem[i].sys_addr && sys + len <
		    priv->mem[i].sys_addr +  priv->mem[i].size) {
			unsigned int offset = sys - priv->mem[i].sys_addr;
			/* __force to make sparse happy with type conversion */
			va = (__force void *)(priv->mem[i].cpu_addr + offset);
			break;
		}
	}

	dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",
		da, len, va);

	return va;
}

static int imx_rproc_mem_alloc(struct rproc *rproc,
			       struct rproc_mem_entry *mem)
{
	struct device *dev = rproc->dev.parent;
	void *va;

	dev_dbg(dev, "map memory: %p+%zx\n", &mem->dma, mem->len);
	va = ioremap_wc(mem->dma, mem->len);
	if (IS_ERR_OR_NULL(va)) {
		dev_err(dev, "Unable to map memory region: %p+%zx\n",
			&mem->dma, mem->len);
		return -ENOMEM;
	}

	/* Update memory entry va */
	mem->va = va;

	return 0;
}

static int imx_rproc_mem_release(struct rproc *rproc,
				 struct rproc_mem_entry *mem)
{
	dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma);
	iounmap(mem->va);

	return 0;
}

static int imx_rproc_parse_memory_regions(struct rproc *rproc)
{
	struct imx_rproc *priv = rproc->priv;
	struct device_node *np = priv->dev->of_node;
	struct of_phandle_iterator it;
	struct rproc_mem_entry *mem;
	struct reserved_mem *rmem;
	u32 da;

	/* Register associated reserved memory regions */
	of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
	while (of_phandle_iterator_next(&it) == 0) {
		/*
		 * Ignore the first memory region which will be used vdev buffer.
		 * No need to do extra handlings, rproc_add_virtio_dev will handle it.
		 */
		if (!strcmp(it.node->name, "vdev0buffer"))
			continue;

		rmem = of_reserved_mem_lookup(it.node);
		if (!rmem) {
			dev_err(priv->dev, "unable to acquire memory-region\n");
			return -EINVAL;
		}

		/* No need to translate pa to da, i.MX use same map */
		da = rmem->base;

		/* Register memory region */
		mem = rproc_mem_entry_init(priv->dev, NULL, (dma_addr_t)rmem->base, rmem->size, da,
					   imx_rproc_mem_alloc, imx_rproc_mem_release,
					   it.node->name);

		if (mem)
			rproc_coredump_add_segment(rproc, da, rmem->size);
		else
			return -ENOMEM;

		rproc_add_carveout(rproc, mem);
	}

	return  0;
}

static int imx_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
{
	int ret = imx_rproc_parse_memory_regions(rproc);

	if (ret)
		return ret;

	ret = rproc_elf_load_rsc_table(rproc, fw);
	if (ret)
		dev_info(&rproc->dev, "No resource table in elf\n");

	return 0;
}

static void imx_rproc_kick(struct rproc *rproc, int vqid)
{
	struct imx_rproc *priv = rproc->priv;
	int err;
	__u32 mmsg;

	if (!priv->tx_ch) {
		dev_err(priv->dev, "No initialized mbox tx channel\n");
		return;
	}

	/*
	 * Send the index of the triggered virtqueue as the mu payload.
	 * Let remote processor know which virtqueue is used.
	 */
	mmsg = vqid << 16;

	err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
	if (err < 0)
		dev_err(priv->dev, "%s: failed (%d, err:%d)\n",
			__func__, vqid, err);
}

static const struct rproc_ops imx_rproc_ops = {
	.start		= imx_rproc_start,
	.stop		= imx_rproc_stop,
	.kick		= imx_rproc_kick,
	.da_to_va       = imx_rproc_da_to_va,
	.load		= rproc_elf_load_segments,
	.parse_fw	= imx_rproc_parse_fw,
	.find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
	.sanity_check	= rproc_elf_sanity_check,
	.get_boot_addr	= rproc_elf_get_boot_addr,
};

static int imx_rproc_addr_init(struct imx_rproc *priv,
			       struct platform_device *pdev)
{
	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	int a, b = 0, err, nph;

	/* remap required addresses */
	for (a = 0; a < dcfg->att_size; a++) {
		const struct imx_rproc_att *att = &dcfg->att[a];

		if (!(att->flags & ATT_OWN))
			continue;

		if (b >= IMX7D_RPROC_MEM_MAX)
			break;

		priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
						     att->sa, att->size);
		if (!priv->mem[b].cpu_addr) {
			dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa);
			return -ENOMEM;
		}
		priv->mem[b].sys_addr = att->sa;
		priv->mem[b].size = att->size;
		b++;
	}

	/* memory-region is optional property */
	nph = of_count_phandle_with_args(np, "memory-region", NULL);
	if (nph <= 0)
		return 0;

	/* remap optional addresses */
	for (a = 0; a < nph; a++) {
		struct device_node *node;
		struct resource res;

		node = of_parse_phandle(np, "memory-region", a);
		/* Not map vdev region */
		if (!strcmp(node->name, "vdev"))
			continue;
		err = of_address_to_resource(node, 0, &res);
		if (err) {
			dev_err(dev, "unable to resolve memory region\n");
			return err;
		}

		if (b >= IMX7D_RPROC_MEM_MAX)
			break;

		/* Not use resource version, because we might share region */
		priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
		if (!priv->mem[b].cpu_addr) {
			dev_err(dev, "failed to remap %pr\n", &res);
			return -ENOMEM;
		}
		priv->mem[b].sys_addr = res.start;
		priv->mem[b].size = resource_size(&res);
		b++;
	}

	return 0;
}

static void imx_rproc_vq_work(struct work_struct *work)
{
	struct imx_rproc *priv = container_of(work, struct imx_rproc,
					      rproc_work);

	rproc_vq_interrupt(priv->rproc, 0);
	rproc_vq_interrupt(priv->rproc, 1);
}

static void imx_rproc_rx_callback(struct mbox_client *cl, void *msg)
{
	struct rproc *rproc = dev_get_drvdata(cl->dev);
	struct imx_rproc *priv = rproc->priv;

	queue_work(priv->workqueue, &priv->rproc_work);
}

static int imx_rproc_xtr_mbox_init(struct rproc *rproc)
{
	struct imx_rproc *priv = rproc->priv;
	struct device *dev = priv->dev;
	struct mbox_client *cl;
	int ret;

	if (!of_get_property(dev->of_node, "mbox-names", NULL))
		return 0;

	cl = &priv->cl;
	cl->dev = dev;
	cl->tx_block = true;
	cl->tx_tout = 100;
	cl->knows_txdone = false;
	cl->rx_callback = imx_rproc_rx_callback;

	priv->tx_ch = mbox_request_channel_byname(cl, "tx");
	if (IS_ERR(priv->tx_ch)) {
		ret = PTR_ERR(priv->tx_ch);
		return dev_err_probe(cl->dev, ret,
				     "failed to request tx mailbox channel: %d\n", ret);
	}

	priv->rx_ch = mbox_request_channel_byname(cl, "rx");
	if (IS_ERR(priv->rx_ch)) {
		mbox_free_channel(priv->tx_ch);
		ret = PTR_ERR(priv->rx_ch);
		return dev_err_probe(cl->dev, ret,
				     "failed to request rx mailbox channel: %d\n", ret);
	}

	return 0;
}

static void imx_rproc_free_mbox(struct rproc *rproc)
{
	struct imx_rproc *priv = rproc->priv;

	mbox_free_channel(priv->tx_ch);
	mbox_free_channel(priv->rx_ch);
}

static int imx_rproc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct imx_rproc *priv;
	struct rproc *rproc;
	struct regmap_config config = { .name = "imx-rproc" };
	const struct imx_rproc_dcfg *dcfg;
	struct regmap *regmap;
	int ret;

	regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
	if (IS_ERR(regmap)) {
		dev_err(dev, "failed to find syscon\n");
		return PTR_ERR(regmap);
	}
	regmap_attach_dev(dev, regmap, &config);

	/* set some other name then imx */
	rproc = rproc_alloc(dev, "imx-rproc", &imx_rproc_ops,
			    NULL, sizeof(*priv));
	if (!rproc)
		return -ENOMEM;

	dcfg = of_device_get_match_data(dev);
	if (!dcfg) {
		ret = -EINVAL;
		goto err_put_rproc;
	}

	priv = rproc->priv;
	priv->rproc = rproc;
	priv->regmap = regmap;
	priv->dcfg = dcfg;
	priv->dev = dev;

	dev_set_drvdata(dev, rproc);
	priv->workqueue = create_workqueue(dev_name(dev));
	if (!priv->workqueue) {
		dev_err(dev, "cannot create workqueue\n");
		ret = -ENOMEM;
		goto err_put_rproc;
	}

	ret = imx_rproc_xtr_mbox_init(rproc);
	if (ret)
		goto err_put_wkq;

	ret = imx_rproc_addr_init(priv, pdev);
	if (ret) {
		dev_err(dev, "failed on imx_rproc_addr_init\n");
		goto err_put_mbox;
	}

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "Failed to get clock\n");
		ret = PTR_ERR(priv->clk);
		goto err_put_mbox;
	}

	/*
	 * clk for M4 block including memory. Should be
	 * enabled before .start for FW transfer.
	 */
	ret = clk_prepare_enable(priv->clk);
	if (ret) {
		dev_err(&rproc->dev, "Failed to enable clock\n");
		goto err_put_mbox;
	}

	INIT_WORK(&priv->rproc_work, imx_rproc_vq_work);

	ret = rproc_add(rproc);
	if (ret) {
		dev_err(dev, "rproc_add failed\n");
		goto err_put_clk;
	}

	return 0;

err_put_clk:
	clk_disable_unprepare(priv->clk);
err_put_mbox:
	imx_rproc_free_mbox(rproc);
err_put_wkq:
	destroy_workqueue(priv->workqueue);
err_put_rproc:
	rproc_free(rproc);

	return ret;
}

static int imx_rproc_remove(struct platform_device *pdev)
{
	struct rproc *rproc = platform_get_drvdata(pdev);
	struct imx_rproc *priv = rproc->priv;

	clk_disable_unprepare(priv->clk);
	rproc_del(rproc);
	imx_rproc_free_mbox(rproc);
	rproc_free(rproc);

	return 0;
}

static const struct of_device_id imx_rproc_of_match[] = {
	{ .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d },
	{ .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx },
	{ .compatible = "fsl,imx8mq-cm4", .data = &imx_rproc_cfg_imx8mq },
	{ .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq },
	{},
};
MODULE_DEVICE_TABLE(of, imx_rproc_of_match);

static struct platform_driver imx_rproc_driver = {
	.probe = imx_rproc_probe,
	.remove = imx_rproc_remove,
	.driver = {
		.name = "imx-rproc",
		.of_match_table = imx_rproc_of_match,
	},
};

module_platform_driver(imx_rproc_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("i.MX remote processor control driver");
MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
a0ff4aa6 OR	2	/*
a0ff4aa6 OR	3	* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
a0ff4aa6 OR	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/kernel.h>
2df70620	10	#include <linux/mailbox_client.h>
a0ff4aa6 OR	11	#include <linux/mfd/syscon.h>
	12	#include <linux/module.h>
	13	#include <linux/of_address.h>
b29b4249	14	#include <linux/of_reserved_mem.h>
a0ff4aa6 OR	15	#include <linux/of_device.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/regmap.h>
	18	#include <linux/remoteproc.h>
2df70620 PF	19	#include <linux/workqueue.h>
	20
	21	#include "remoteproc_internal.h"
a0ff4aa6 OR	22
	23	#define IMX7D_SRC_SCR 0x0C
	24	#define IMX7D_ENABLE_M4 BIT(3)
	25	#define IMX7D_SW_M4P_RST BIT(2)
	26	#define IMX7D_SW_M4C_RST BIT(1)
	27	#define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
	28
	29	#define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 \| IMX7D_SW_M4P_RST \
	30	\| IMX7D_SW_M4C_RST \
	31	\| IMX7D_SW_M4C_NON_SCLR_RST)
	32
	33	#define IMX7D_M4_START (IMX7D_ENABLE_M4 \| IMX7D_SW_M4P_RST \
	34	\| IMX7D_SW_M4C_RST)
	35	#define IMX7D_M4_STOP IMX7D_SW_M4C_NON_SCLR_RST
	36
	37	/* Address: 0x020D8000 */
	38	#define IMX6SX_SRC_SCR 0x00
	39	#define IMX6SX_ENABLE_M4 BIT(22)
	40	#define IMX6SX_SW_M4P_RST BIT(12)
	41	#define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4)
	42	#define IMX6SX_SW_M4C_RST BIT(3)
	43
	44	#define IMX6SX_M4_START (IMX6SX_ENABLE_M4 \| IMX6SX_SW_M4P_RST \
	45	\| IMX6SX_SW_M4C_RST)
	46	#define IMX6SX_M4_STOP IMX6SX_SW_M4C_NON_SCLR_RST
	47	#define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 \| IMX6SX_SW_M4P_RST \
	48	\| IMX6SX_SW_M4C_NON_SCLR_RST \
	49	\| IMX6SX_SW_M4C_RST)
	50
	51	#define IMX7D_RPROC_MEM_MAX 8
	52
	53	/**
	54	* struct imx_rproc_mem - slim internal memory structure
	55	* @cpu_addr: MPU virtual address of the memory region
	56	* @sys_addr: Bus address used to access the memory region
	57	* @size: Size of the memory region
	58	*/
	59	struct imx_rproc_mem {
	60	void __iomem *cpu_addr;
	61	phys_addr_t sys_addr;
	62	size_t size;
	63	};
	64
	65	/* att flags */
	66	/* M4 own area. Can be mapped at probe */
	67	#define ATT_OWN BIT(1)
	68
	69	/* address translation table */
	70	struct imx_rproc_att {
	71	u32 da; /* device address (From Cortex M4 view)*/
	72	u32 sa; /* system bus address */
	73	u32 size; /* size of reg range */
	74	int flags;
	75	};
	76
	77	struct imx_rproc_dcfg {
	78	u32 src_reg;
	79	u32 src_mask;
	80	u32 src_start;
	81	u32 src_stop;
	82	const struct imx_rproc_att *att;
	83	size_t att_size;
	84	};
	85
86	struct imx_rproc {
87	struct device *dev;
88	struct regmap *regmap;
89	struct rproc *rproc;
90	const struct imx_rproc_dcfg *dcfg;
91	struct imx_rproc_mem mem[IMX7D_RPROC_MEM_MAX];
92	struct clk *clk;
2df70620 PF	93	struct mbox_client cl;
	94	struct mbox_chan *tx_ch;
	95	struct mbox_chan *rx_ch;
	96	struct work_struct rproc_work;
	97	struct workqueue_struct *workqueue;
a0ff4aa6 OR	98	};
a0ff4aa6 OR	99
4ab8f960 PF	100	static const struct imx_rproc_att imx_rproc_att_imx8mq[] = {
	101	/* dev addr , sys addr , size , flags */
	102	/* TCML - alias */
	103	{ 0x00000000, 0x007e0000, 0x00020000, 0 },
	104	/* OCRAM_S */
	105	{ 0x00180000, 0x00180000, 0x00008000, 0 },
	106	/* OCRAM */
	107	{ 0x00900000, 0x00900000, 0x00020000, 0 },
	108	/* OCRAM */
	109	{ 0x00920000, 0x00920000, 0x00020000, 0 },
	110	/* QSPI Code - alias */
	111	{ 0x08000000, 0x08000000, 0x08000000, 0 },
	112	/* DDR (Code) - alias */
	113	{ 0x10000000, 0x80000000, 0x0FFE0000, 0 },
	114	/* TCML */
	115	{ 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN },
	116	/* TCMU */
	117	{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN },
	118	/* OCRAM_S */
	119	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
	120	/* OCRAM */
	121	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
	122	/* OCRAM */
	123	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
	124	/* DDR (Data) */
	125	{ 0x40000000, 0x40000000, 0x80000000, 0 },
	126	};
	127
a0ff4aa6 OR	128	static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
	129	/* dev addr , sys addr , size , flags */
	130	/* OCRAM_S (M4 Boot code) - alias */
	131	{ 0x00000000, 0x00180000, 0x00008000, 0 },
	132	/* OCRAM_S (Code) */
	133	{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
	134	/* OCRAM (Code) - alias */
	135	{ 0x00900000, 0x00900000, 0x00020000, 0 },
	136	/* OCRAM_EPDC (Code) - alias */
	137	{ 0x00920000, 0x00920000, 0x00020000, 0 },
	138	/* OCRAM_PXP (Code) - alias */
	139	{ 0x00940000, 0x00940000, 0x00008000, 0 },
	140	/* TCML (Code) */
	141	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
	142	/* DDR (Code) - alias, first part of DDR (Data) */
	143	{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
	144
	145	/* TCMU (Data) */
	146	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
	147	/* OCRAM (Data) */
	148	{ 0x20200000, 0x00900000, 0x00020000, 0 },
	149	/* OCRAM_EPDC (Data) */
	150	{ 0x20220000, 0x00920000, 0x00020000, 0 },
	151	/* OCRAM_PXP (Data) */
	152	{ 0x20240000, 0x00940000, 0x00008000, 0 },
	153	/* DDR (Data) */
	154	{ 0x80000000, 0x80000000, 0x60000000, 0 },
	155	};
	156
	157	static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
	158	/* dev addr , sys addr , size , flags */
	159	/* TCML (M4 Boot Code) - alias */
	160	{ 0x00000000, 0x007F8000, 0x00008000, 0 },
	161	/* OCRAM_S (Code) */
	162	{ 0x00180000, 0x008F8000, 0x00004000, 0 },
	163	/* OCRAM_S (Code) - alias */
	164	{ 0x00180000, 0x008FC000, 0x00004000, 0 },
	165	/* TCML (Code) */
	166	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
	167	/* DDR (Code) - alias, first part of DDR (Data) */
	168	{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
	169
	170	/* TCMU (Data) */
	171	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
	172	/* OCRAM_S (Data) - alias? */
	173	{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
	174	/* DDR (Data) */
	175	{ 0x80000000, 0x80000000, 0x60000000, 0 },
	176	};
	177
4ab8f960 PF	178	static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = {
	179	.src_reg = IMX7D_SRC_SCR,
	180	.src_mask = IMX7D_M4_RST_MASK,
	181	.src_start = IMX7D_M4_START,
	182	.src_stop = IMX7D_M4_STOP,
	183	.att = imx_rproc_att_imx8mq,
	184	.att_size = ARRAY_SIZE(imx_rproc_att_imx8mq),
	185	};
	186
a0ff4aa6 OR	187	static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = {
	188	.src_reg = IMX7D_SRC_SCR,
	189	.src_mask = IMX7D_M4_RST_MASK,
	190	.src_start = IMX7D_M4_START,
	191	.src_stop = IMX7D_M4_STOP,
	192	.att = imx_rproc_att_imx7d,
	193	.att_size = ARRAY_SIZE(imx_rproc_att_imx7d),
	194	};
	195
	196	static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = {
	197	.src_reg = IMX6SX_SRC_SCR,
	198	.src_mask = IMX6SX_M4_RST_MASK,
	199	.src_start = IMX6SX_M4_START,
	200	.src_stop = IMX6SX_M4_STOP,
	201	.att = imx_rproc_att_imx6sx,
	202	.att_size = ARRAY_SIZE(imx_rproc_att_imx6sx),
	203	};
	204
	205	static int imx_rproc_start(struct rproc *rproc)
	206	{
	207	struct imx_rproc *priv = rproc->priv;
	208	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	209	struct device *dev = priv->dev;
	210	int ret;
	211
	212	ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
	213	dcfg->src_mask, dcfg->src_start);
	214	if (ret)
16a3c637	215	dev_err(dev, "Failed to enable M4!\n");
a0ff4aa6 OR	216
	217	return ret;
	218	}
	219
	220	static int imx_rproc_stop(struct rproc *rproc)
	221	{
	222	struct imx_rproc *priv = rproc->priv;
	223	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	224	struct device *dev = priv->dev;
	225	int ret;
	226
	227	ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
	228	dcfg->src_mask, dcfg->src_stop);
	229	if (ret)
16a3c637	230	dev_err(dev, "Failed to stop M4!\n");
a0ff4aa6 OR	231
	232	return ret;
	233	}
	234
	235	static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
9ce3bf22	236	size_t len, u64 *sys)
a0ff4aa6 OR	237	{
	238	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	239	int i;
	240
	241	/* parse address translation table */
	242	for (i = 0; i < dcfg->att_size; i++) {
	243	const struct imx_rproc_att *att = &dcfg->att[i];
	244
	245	if (da >= att->da && da + len < att->da + att->size) {
	246	unsigned int offset = da - att->da;
	247
	248	*sys = att->sa + offset;
	249	return 0;
	250	}
	251	}
	252
9ce3bf22	253	dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",
a0ff4aa6 OR	254	da, len);
	255	return -ENOENT;
	256	}
	257
40df0a91	258	static void imx_rproc_da_to_va(struct rproc rproc, u64 da, size_t len, bool *is_iomem)
a0ff4aa6 OR	259	{
	260	struct imx_rproc *priv = rproc->priv;
	261	void *va = NULL;
	262	u64 sys;
	263	int i;
	264
9ce3bf22	265	if (len == 0)
a0ff4aa6 OR	266	return NULL;
	267
	268	/*
	269	* On device side we have many aliases, so we need to convert device
	270	* address (M4) to system bus address first.
	271	*/
	272	if (imx_rproc_da_to_sys(priv, da, len, &sys))
	273	return NULL;
	274
	275	for (i = 0; i < IMX7D_RPROC_MEM_MAX; i++) {
	276	if (sys >= priv->mem[i].sys_addr && sys + len <
	277	priv->mem[i].sys_addr + priv->mem[i].size) {
	278	unsigned int offset = sys - priv->mem[i].sys_addr;
	279	/* __force to make sparse happy with type conversion */
	280	va = (__force void *)(priv->mem[i].cpu_addr + offset);
	281	break;
	282	}
	283	}
	284
9ce3bf22 CL	285	dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",
9ce3bf22 CL	286	da, len, va);
a0ff4aa6 OR	287
	288	return va;
	289	}
	290
b29b4249 PF	291	static int imx_rproc_mem_alloc(struct rproc *rproc,
	292	struct rproc_mem_entry *mem)
	293	{
	294	struct device *dev = rproc->dev.parent;
	295	void *va;
	296
	297	dev_dbg(dev, "map memory: %p+%zx\n", &mem->dma, mem->len);
	298	va = ioremap_wc(mem->dma, mem->len);
	299	if (IS_ERR_OR_NULL(va)) {
	300	dev_err(dev, "Unable to map memory region: %p+%zx\n",
	301	&mem->dma, mem->len);
	302	return -ENOMEM;
	303	}
	304
	305	/* Update memory entry va */
	306	mem->va = va;
	307
	308	return 0;
	309	}
	310
	311	static int imx_rproc_mem_release(struct rproc *rproc,
	312	struct rproc_mem_entry *mem)
	313	{
	314	dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma);
	315	iounmap(mem->va);
	316
	317	return 0;
	318	}
	319
	320	static int imx_rproc_parse_memory_regions(struct rproc *rproc)
	321	{
	322	struct imx_rproc *priv = rproc->priv;
	323	struct device_node *np = priv->dev->of_node;
	324	struct of_phandle_iterator it;
	325	struct rproc_mem_entry *mem;
	326	struct reserved_mem *rmem;
	327	u32 da;
	328
	329	/* Register associated reserved memory regions */
	330	of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
	331	while (of_phandle_iterator_next(&it) == 0) {
	332	/*
	333	* Ignore the first memory region which will be used vdev buffer.
	334	* No need to do extra handlings, rproc_add_virtio_dev will handle it.
	335	*/
	336	if (!strcmp(it.node->name, "vdev0buffer"))
	337	continue;
	338
	339	rmem = of_reserved_mem_lookup(it.node);
	340	if (!rmem) {
	341	dev_err(priv->dev, "unable to acquire memory-region\n");
	342	return -EINVAL;
	343	}
	344
	345	/* No need to translate pa to da, i.MX use same map */
	346	da = rmem->base;
	347
	348	/* Register memory region */
	349	mem = rproc_mem_entry_init(priv->dev, NULL, (dma_addr_t)rmem->base, rmem->size, da,
	350	imx_rproc_mem_alloc, imx_rproc_mem_release,
	351	it.node->name);
	352
	353	if (mem)
	354	rproc_coredump_add_segment(rproc, da, rmem->size);
355	else
356	return -ENOMEM;
357
358	rproc_add_carveout(rproc, mem);
359	}
360
361	return 0;
362	}
363
364	static int imx_rproc_parse_fw(struct rproc rproc, const struct firmware fw)
365	{
366	int ret = imx_rproc_parse_memory_regions(rproc);
367
368	if (ret)
369	return ret;
370
371	ret = rproc_elf_load_rsc_table(rproc, fw);
372	if (ret)
373	dev_info(&rproc->dev, "No resource table in elf\n");
374
375	return 0;
376	}
377
2df70620 PF	378	static void imx_rproc_kick(struct rproc *rproc, int vqid)
	379	{
	380	struct imx_rproc *priv = rproc->priv;
	381	int err;
	382	__u32 mmsg;
	383
	384	if (!priv->tx_ch) {
	385	dev_err(priv->dev, "No initialized mbox tx channel\n");
	386	return;
	387	}
	388
	389	/*
	390	* Send the index of the triggered virtqueue as the mu payload.
	391	* Let remote processor know which virtqueue is used.
	392	*/
	393	mmsg = vqid << 16;
	394
	395	err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
	396	if (err < 0)
	397	dev_err(priv->dev, "%s: failed (%d, err:%d)\n",
	398	__func__, vqid, err);
	399	}
	400
a0ff4aa6 OR	401	static const struct rproc_ops imx_rproc_ops = {
	402	.start = imx_rproc_start,
	403	.stop = imx_rproc_stop,
2df70620	404	.kick = imx_rproc_kick,
a0ff4aa6	405	.da_to_va = imx_rproc_da_to_va,
b29b4249 PF	406	.load = rproc_elf_load_segments,
	407	.parse_fw = imx_rproc_parse_fw,
	408	.find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
	409	.sanity_check = rproc_elf_sanity_check,
	410	.get_boot_addr = rproc_elf_get_boot_addr,
a0ff4aa6 OR	411	};
	412
	413	static int imx_rproc_addr_init(struct imx_rproc *priv,
	414	struct platform_device *pdev)
	415	{
	416	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
	417	struct device *dev = &pdev->dev;
	418	struct device_node *np = dev->of_node;
	419	int a, b = 0, err, nph;
	420
	421	/* remap required addresses */
	422	for (a = 0; a < dcfg->att_size; a++) {
	423	const struct imx_rproc_att *att = &dcfg->att[a];
	424
	425	if (!(att->flags & ATT_OWN))
	426	continue;
	427
68c2d645	428	if (b >= IMX7D_RPROC_MEM_MAX)
a0ff4aa6 OR	429	break;
	430
	431	priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
	432	att->sa, att->size);
68a39a3e	433	if (!priv->mem[b].cpu_addr) {
1896b3d8	434	dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa);
68a39a3e	435	return -ENOMEM;
a0ff4aa6 OR	436	}
	437	priv->mem[b].sys_addr = att->sa;
	438	priv->mem[b].size = att->size;
	439	b++;
	440	}
	441
	442	/* memory-region is optional property */
	443	nph = of_count_phandle_with_args(np, "memory-region", NULL);
	444	if (nph <= 0)
	445	return 0;
	446
	447	/* remap optional addresses */
	448	for (a = 0; a < nph; a++) {
	449	struct device_node *node;
	450	struct resource res;
	451
	452	node = of_parse_phandle(np, "memory-region", a);
8f2d8961 PF	453	/* Not map vdev region */
	454	if (!strcmp(node->name, "vdev"))
	455	continue;
a0ff4aa6 OR	456	err = of_address_to_resource(node, 0, &res);
	457	if (err) {
	458	dev_err(dev, "unable to resolve memory region\n");
	459	return err;
	460	}
	461
68c2d645	462	if (b >= IMX7D_RPROC_MEM_MAX)
a0ff4aa6 OR	463	break;
a0ff4aa6 OR	464
ecadcc47 PF	465	/* Not use resource version, because we might share region */
ecadcc47 PF	466	priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
18cda801	467	if (!priv->mem[b].cpu_addr) {
1896b3d8	468	dev_err(dev, "failed to remap %pr\n", &res);
18cda801	469	return -ENOMEM;
a0ff4aa6 OR	470	}
	471	priv->mem[b].sys_addr = res.start;
	472	priv->mem[b].size = resource_size(&res);
	473	b++;
	474	}
	475
	476	return 0;
	477	}
	478
2df70620 PF	479	static void imx_rproc_vq_work(struct work_struct *work)
	480	{
	481	struct imx_rproc *priv = container_of(work, struct imx_rproc,
	482	rproc_work);
	483
	484	rproc_vq_interrupt(priv->rproc, 0);
	485	rproc_vq_interrupt(priv->rproc, 1);
	486	}
	487
	488	static void imx_rproc_rx_callback(struct mbox_client cl, void msg)
	489	{
	490	struct rproc *rproc = dev_get_drvdata(cl->dev);
	491	struct imx_rproc *priv = rproc->priv;
	492
	493	queue_work(priv->workqueue, &priv->rproc_work);
	494	}
	495
	496	static int imx_rproc_xtr_mbox_init(struct rproc *rproc)
	497	{
	498	struct imx_rproc *priv = rproc->priv;
	499	struct device *dev = priv->dev;
	500	struct mbox_client *cl;
	501	int ret;
	502
	503	if (!of_get_property(dev->of_node, "mbox-names", NULL))
	504	return 0;
	505
	506	cl = &priv->cl;
	507	cl->dev = dev;
	508	cl->tx_block = true;
	509	cl->tx_tout = 100;
	510	cl->knows_txdone = false;
	511	cl->rx_callback = imx_rproc_rx_callback;
	512
	513	priv->tx_ch = mbox_request_channel_byname(cl, "tx");
	514	if (IS_ERR(priv->tx_ch)) {
	515	ret = PTR_ERR(priv->tx_ch);
	516	return dev_err_probe(cl->dev, ret,
	517	"failed to request tx mailbox channel: %d\n", ret);
	518	}
	519
	520	priv->rx_ch = mbox_request_channel_byname(cl, "rx");
	521	if (IS_ERR(priv->rx_ch)) {
	522	mbox_free_channel(priv->tx_ch);
	523	ret = PTR_ERR(priv->rx_ch);
	524	return dev_err_probe(cl->dev, ret,
	525	"failed to request rx mailbox channel: %d\n", ret);
	526	}
	527
	528	return 0;
	529	}
	530
	531	static void imx_rproc_free_mbox(struct rproc *rproc)
	532	{
	533	struct imx_rproc *priv = rproc->priv;
	534
	535	mbox_free_channel(priv->tx_ch);
	536	mbox_free_channel(priv->rx_ch);
	537	}
	538
a0ff4aa6 OR	539	static int imx_rproc_probe(struct platform_device *pdev)
	540	{
	541	struct device *dev = &pdev->dev;
	542	struct device_node *np = dev->of_node;
	543	struct imx_rproc *priv;
	544	struct rproc *rproc;
	545	struct regmap_config config = { .name = "imx-rproc" };
	546	const struct imx_rproc_dcfg *dcfg;
	547	struct regmap *regmap;
	548	int ret;
	549
	550	regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
	551	if (IS_ERR(regmap)) {
	552	dev_err(dev, "failed to find syscon\n");
	553	return PTR_ERR(regmap);
	554	}
	555	regmap_attach_dev(dev, regmap, &config);
	556
	557	/* set some other name then imx */
	558	rproc = rproc_alloc(dev, "imx-rproc", &imx_rproc_ops,
	559	NULL, sizeof(*priv));
99a31adf CJ	560	if (!rproc)
99a31adf CJ	561	return -ENOMEM;
a0ff4aa6 OR	562
a0ff4aa6 OR	563	dcfg = of_device_get_match_data(dev);
de6f83f8 CJ	564	if (!dcfg) {
	565	ret = -EINVAL;
	566	goto err_put_rproc;
	567	}
a0ff4aa6 OR	568
	569	priv = rproc->priv;
	570	priv->rproc = rproc;
	571	priv->regmap = regmap;
	572	priv->dcfg = dcfg;
	573	priv->dev = dev;
	574
	575	dev_set_drvdata(dev, rproc);
2df70620 PF	576	priv->workqueue = create_workqueue(dev_name(dev));
	577	if (!priv->workqueue) {
	578	dev_err(dev, "cannot create workqueue\n");
	579	ret = -ENOMEM;
	580	goto err_put_rproc;
	581	}
	582
	583	ret = imx_rproc_xtr_mbox_init(rproc);
	584	if (ret)
	585	goto err_put_wkq;
a0ff4aa6 OR	586
	587	ret = imx_rproc_addr_init(priv, pdev);
	588	if (ret) {
16a3c637	589	dev_err(dev, "failed on imx_rproc_addr_init\n");
2df70620	590	goto err_put_mbox;
a0ff4aa6 OR	591	}
	592
	593	priv->clk = devm_clk_get(dev, NULL);
	594	if (IS_ERR(priv->clk)) {
	595	dev_err(dev, "Failed to get clock\n");
96a30d7f	596	ret = PTR_ERR(priv->clk);
2df70620	597	goto err_put_mbox;
a0ff4aa6 OR	598	}
	599
	600	/*
	601	* clk for M4 block including memory. Should be
	602	* enabled before .start for FW transfer.
	603	*/
	604	ret = clk_prepare_enable(priv->clk);
	605	if (ret) {
	606	dev_err(&rproc->dev, "Failed to enable clock\n");
2df70620	607	goto err_put_mbox;
a0ff4aa6 OR	608	}
a0ff4aa6 OR	609
2df70620 PF	610	INIT_WORK(&priv->rproc_work, imx_rproc_vq_work);
2df70620 PF	611
a0ff4aa6 OR	612	ret = rproc_add(rproc);
	613	if (ret) {
	614	dev_err(dev, "rproc_add failed\n");
	615	goto err_put_clk;
	616	}
	617
99a31adf	618	return 0;
a0ff4aa6 OR	619
	620	err_put_clk:
	621	clk_disable_unprepare(priv->clk);
2df70620 PF	622	err_put_mbox:
	623	imx_rproc_free_mbox(rproc);
	624	err_put_wkq:
	625	destroy_workqueue(priv->workqueue);
a0ff4aa6 OR	626	err_put_rproc:
a0ff4aa6 OR	627	rproc_free(rproc);
99a31adf	628
a0ff4aa6 OR	629	return ret;
	630	}
	631
	632	static int imx_rproc_remove(struct platform_device *pdev)
	633	{
	634	struct rproc *rproc = platform_get_drvdata(pdev);
	635	struct imx_rproc *priv = rproc->priv;
	636
	637	clk_disable_unprepare(priv->clk);
	638	rproc_del(rproc);
2df70620	639	imx_rproc_free_mbox(rproc);
a0ff4aa6 OR	640	rproc_free(rproc);
	641
	642	return 0;
	643	}
	644
	645	static const struct of_device_id imx_rproc_of_match[] = {
	646	{ .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d },
	647	{ .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx },
4ab8f960 PF	648	{ .compatible = "fsl,imx8mq-cm4", .data = &imx_rproc_cfg_imx8mq },
4ab8f960 PF	649	{ .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq },
a0ff4aa6 OR	650	{},
	651	};
	652	MODULE_DEVICE_TABLE(of, imx_rproc_of_match);
	653
	654	static struct platform_driver imx_rproc_driver = {
	655	.probe = imx_rproc_probe,
	656	.remove = imx_rproc_remove,
	657	.driver = {
	658	.name = "imx-rproc",
	659	.of_match_table = imx_rproc_of_match,
	660	},
	661	};
	662
	663	module_platform_driver(imx_rproc_driver);
	664
	665	MODULE_LICENSE("GPL v2");
4ab8f960	666	MODULE_DESCRIPTION("i.MX remote processor control driver");
a0ff4aa6	667	MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");