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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
34ed5a33 OBC |
2 | /* |
3 | * OMAP Remote Processor driver | |
4 | * | |
75242927 | 5 | * Copyright (C) 2011-2020 Texas Instruments Incorporated - http://www.ti.com/ |
34ed5a33 OBC |
6 | * Copyright (C) 2011 Google, Inc. |
7 | * | |
8 | * Ohad Ben-Cohen <ohad@wizery.com> | |
9 | * Brian Swetland <swetland@google.com> | |
10 | * Fernando Guzman Lugo <fernando.lugo@ti.com> | |
11 | * Mark Grosen <mgrosen@ti.com> | |
12 | * Suman Anna <s-anna@ti.com> | |
13 | * Hari Kanigeri <h-kanigeri2@ti.com> | |
34ed5a33 OBC |
14 | */ |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
9077ac1a SA |
18 | #include <linux/clk.h> |
19 | #include <linux/clk/ti.h> | |
34ed5a33 | 20 | #include <linux/err.h> |
9077ac1a | 21 | #include <linux/io.h> |
75242927 | 22 | #include <linux/of_device.h> |
f4af5bd2 | 23 | #include <linux/of_reserved_mem.h> |
34ed5a33 | 24 | #include <linux/platform_device.h> |
5f31b232 | 25 | #include <linux/pm_runtime.h> |
34ed5a33 | 26 | #include <linux/dma-mapping.h> |
69591e4a | 27 | #include <linux/interrupt.h> |
34ed5a33 | 28 | #include <linux/remoteproc.h> |
8841a66a | 29 | #include <linux/mailbox_client.h> |
9077ac1a | 30 | #include <linux/omap-iommu.h> |
c869c75c | 31 | #include <linux/omap-mailbox.h> |
75242927 SA |
32 | #include <linux/regmap.h> |
33 | #include <linux/mfd/syscon.h> | |
34 | #include <linux/reset.h> | |
e28edc57 SA |
35 | #include <clocksource/timer-ti-dm.h> |
36 | ||
37 | #include <linux/platform_data/dmtimer-omap.h> | |
34ed5a33 OBC |
38 | |
39 | #include "omap_remoteproc.h" | |
40 | #include "remoteproc_internal.h" | |
41 | ||
5f31b232 SA |
42 | /* default auto-suspend delay (ms) */ |
43 | #define DEFAULT_AUTOSUSPEND_DELAY 10000 | |
44 | ||
75242927 SA |
45 | /** |
46 | * struct omap_rproc_boot_data - boot data structure for the DSP omap rprocs | |
47 | * @syscon: regmap handle for the system control configuration module | |
48 | * @boot_reg: boot register offset within the @syscon regmap | |
0aaf1913 SA |
49 | * @boot_reg_shift: bit-field shift required for the boot address value in |
50 | * @boot_reg | |
75242927 SA |
51 | */ |
52 | struct omap_rproc_boot_data { | |
53 | struct regmap *syscon; | |
54 | unsigned int boot_reg; | |
0aaf1913 | 55 | unsigned int boot_reg_shift; |
75242927 SA |
56 | }; |
57 | ||
4a032199 SA |
58 | /** |
59 | * struct omap_rproc_mem - internal memory structure | |
60 | * @cpu_addr: MPU virtual address of the memory region | |
61 | * @bus_addr: bus address used to access the memory region | |
62 | * @dev_addr: device address of the memory region from DSP view | |
63 | * @size: size of the memory region | |
64 | */ | |
65 | struct omap_rproc_mem { | |
66 | void __iomem *cpu_addr; | |
67 | phys_addr_t bus_addr; | |
68 | u32 dev_addr; | |
69 | size_t size; | |
70 | }; | |
71 | ||
e28edc57 SA |
72 | /** |
73 | * struct omap_rproc_timer - data structure for a timer used by a omap rproc | |
74 | * @odt: timer pointer | |
75 | * @timer_ops: OMAP dmtimer ops for @odt timer | |
69591e4a | 76 | * @irq: timer irq |
e28edc57 SA |
77 | */ |
78 | struct omap_rproc_timer { | |
79 | struct omap_dm_timer *odt; | |
80 | const struct omap_dm_timer_ops *timer_ops; | |
69591e4a | 81 | int irq; |
e28edc57 SA |
82 | }; |
83 | ||
34ed5a33 OBC |
84 | /** |
85 | * struct omap_rproc - omap remote processor state | |
8841a66a SA |
86 | * @mbox: mailbox channel handle |
87 | * @client: mailbox client to request the mailbox channel | |
75242927 | 88 | * @boot_data: boot data structure for setting processor boot address |
4a032199 SA |
89 | * @mem: internal memory regions data |
90 | * @num_mems: number of internal memory regions | |
e28edc57 | 91 | * @num_timers: number of rproc timer(s) |
69591e4a | 92 | * @num_wd_timers: number of rproc watchdog timers |
e28edc57 | 93 | * @timers: timer(s) info used by rproc |
5f31b232 SA |
94 | * @autosuspend_delay: auto-suspend delay value to be used for runtime pm |
95 | * @need_resume: if true a resume is needed in the system resume callback | |
34ed5a33 | 96 | * @rproc: rproc handle |
75242927 | 97 | * @reset: reset handle |
9077ac1a SA |
98 | * @pm_comp: completion primitive to sync for suspend response |
99 | * @fck: functional clock for the remoteproc | |
100 | * @suspend_acked: state machine flag to store the suspend request ack | |
34ed5a33 OBC |
101 | */ |
102 | struct omap_rproc { | |
8841a66a SA |
103 | struct mbox_chan *mbox; |
104 | struct mbox_client client; | |
75242927 | 105 | struct omap_rproc_boot_data *boot_data; |
4a032199 SA |
106 | struct omap_rproc_mem *mem; |
107 | int num_mems; | |
e28edc57 | 108 | int num_timers; |
69591e4a | 109 | int num_wd_timers; |
e28edc57 | 110 | struct omap_rproc_timer *timers; |
5f31b232 SA |
111 | int autosuspend_delay; |
112 | bool need_resume; | |
34ed5a33 | 113 | struct rproc *rproc; |
75242927 | 114 | struct reset_control *reset; |
9077ac1a SA |
115 | struct completion pm_comp; |
116 | struct clk *fck; | |
117 | bool suspend_acked; | |
75242927 SA |
118 | }; |
119 | ||
4a032199 SA |
120 | /** |
121 | * struct omap_rproc_mem_data - memory definitions for an omap remote processor | |
122 | * @name: name for this memory entry | |
123 | * @dev_addr: device address for the memory entry | |
124 | */ | |
125 | struct omap_rproc_mem_data { | |
126 | const char *name; | |
127 | const u32 dev_addr; | |
128 | }; | |
129 | ||
75242927 SA |
130 | /** |
131 | * struct omap_rproc_dev_data - device data for the omap remote processor | |
132 | * @device_name: device name of the remote processor | |
4a032199 | 133 | * @mems: memory definitions for this remote processor |
75242927 SA |
134 | */ |
135 | struct omap_rproc_dev_data { | |
136 | const char *device_name; | |
4a032199 | 137 | const struct omap_rproc_mem_data *mems; |
34ed5a33 OBC |
138 | }; |
139 | ||
e28edc57 SA |
140 | /** |
141 | * omap_rproc_request_timer() - request a timer for a remoteproc | |
142 | * @dev: device requesting the timer | |
143 | * @np: device node pointer to the desired timer | |
144 | * @timer: handle to a struct omap_rproc_timer to return the timer handle | |
145 | * | |
146 | * This helper function is used primarily to request a timer associated with | |
147 | * a remoteproc. The returned handle is stored in the .odt field of the | |
148 | * @timer structure passed in, and is used to invoke other timer specific | |
149 | * ops (like starting a timer either during device initialization or during | |
150 | * a resume operation, or for stopping/freeing a timer). | |
151 | * | |
152 | * Return: 0 on success, otherwise an appropriate failure | |
153 | */ | |
154 | static int omap_rproc_request_timer(struct device *dev, struct device_node *np, | |
155 | struct omap_rproc_timer *timer) | |
156 | { | |
157 | int ret; | |
158 | ||
159 | timer->odt = timer->timer_ops->request_by_node(np); | |
160 | if (!timer->odt) { | |
161 | dev_err(dev, "request for timer node %p failed\n", np); | |
162 | return -EBUSY; | |
163 | } | |
164 | ||
165 | ret = timer->timer_ops->set_source(timer->odt, OMAP_TIMER_SRC_SYS_CLK); | |
166 | if (ret) { | |
167 | dev_err(dev, "error setting OMAP_TIMER_SRC_SYS_CLK as source for timer node %p\n", | |
168 | np); | |
169 | timer->timer_ops->free(timer->odt); | |
170 | return ret; | |
171 | } | |
172 | ||
173 | /* clean counter, remoteproc code will set the value */ | |
e6d05acd | 174 | timer->timer_ops->set_load(timer->odt, 0); |
e28edc57 SA |
175 | |
176 | return 0; | |
177 | } | |
178 | ||
179 | /** | |
180 | * omap_rproc_start_timer() - start a timer for a remoteproc | |
181 | * @timer: handle to a OMAP rproc timer | |
182 | * | |
183 | * This helper function is used to start a timer associated with a remoteproc, | |
184 | * obtained using the request_timer ops. The helper function needs to be | |
185 | * invoked by the driver to start the timer (during device initialization) | |
186 | * or to just resume the timer. | |
187 | * | |
188 | * Return: 0 on success, otherwise a failure as returned by DMTimer ops | |
189 | */ | |
190 | static inline int omap_rproc_start_timer(struct omap_rproc_timer *timer) | |
191 | { | |
192 | return timer->timer_ops->start(timer->odt); | |
193 | } | |
194 | ||
195 | /** | |
196 | * omap_rproc_stop_timer() - stop a timer for a remoteproc | |
197 | * @timer: handle to a OMAP rproc timer | |
198 | * | |
199 | * This helper function is used to disable a timer associated with a | |
200 | * remoteproc, and needs to be called either during a device shutdown | |
201 | * or suspend operation. The separate helper function allows the driver | |
202 | * to just stop a timer without having to release the timer during a | |
203 | * suspend operation. | |
204 | * | |
205 | * Return: 0 on success, otherwise a failure as returned by DMTimer ops | |
206 | */ | |
207 | static inline int omap_rproc_stop_timer(struct omap_rproc_timer *timer) | |
208 | { | |
209 | return timer->timer_ops->stop(timer->odt); | |
210 | } | |
211 | ||
212 | /** | |
213 | * omap_rproc_release_timer() - release a timer for a remoteproc | |
214 | * @timer: handle to a OMAP rproc timer | |
215 | * | |
216 | * This helper function is used primarily to release a timer associated | |
217 | * with a remoteproc. The dmtimer will be available for other clients to | |
218 | * use once released. | |
219 | * | |
220 | * Return: 0 on success, otherwise a failure as returned by DMTimer ops | |
221 | */ | |
222 | static inline int omap_rproc_release_timer(struct omap_rproc_timer *timer) | |
223 | { | |
224 | return timer->timer_ops->free(timer->odt); | |
225 | } | |
226 | ||
69591e4a SA |
227 | /** |
228 | * omap_rproc_get_timer_irq() - get the irq for a timer | |
229 | * @timer: handle to a OMAP rproc timer | |
230 | * | |
231 | * This function is used to get the irq associated with a watchdog timer. The | |
232 | * function is called by the OMAP remoteproc driver to register a interrupt | |
233 | * handler to handle watchdog events on the remote processor. | |
234 | * | |
235 | * Return: irq id on success, otherwise a failure as returned by DMTimer ops | |
236 | */ | |
237 | static inline int omap_rproc_get_timer_irq(struct omap_rproc_timer *timer) | |
238 | { | |
239 | return timer->timer_ops->get_irq(timer->odt); | |
240 | } | |
241 | ||
242 | /** | |
243 | * omap_rproc_ack_timer_irq() - acknowledge a timer irq | |
244 | * @timer: handle to a OMAP rproc timer | |
245 | * | |
246 | * This function is used to clear the irq associated with a watchdog timer. The | |
247 | * The function is called by the OMAP remoteproc upon a watchdog event on the | |
248 | * remote processor to clear the interrupt status of the watchdog timer. | |
249 | */ | |
250 | static inline void omap_rproc_ack_timer_irq(struct omap_rproc_timer *timer) | |
251 | { | |
252 | timer->timer_ops->write_status(timer->odt, OMAP_TIMER_INT_OVERFLOW); | |
253 | } | |
254 | ||
255 | /** | |
256 | * omap_rproc_watchdog_isr() - Watchdog ISR handler for remoteproc device | |
257 | * @irq: IRQ number associated with a watchdog timer | |
258 | * @data: IRQ handler data | |
259 | * | |
260 | * This ISR routine executes the required necessary low-level code to | |
261 | * acknowledge a watchdog timer interrupt. There can be multiple watchdog | |
262 | * timers associated with a rproc (like IPUs which have 2 watchdog timers, | |
263 | * one per Cortex M3/M4 core), so a lookup has to be performed to identify | |
264 | * the timer to acknowledge its interrupt. | |
265 | * | |
266 | * The function also invokes rproc_report_crash to report the watchdog event | |
267 | * to the remoteproc driver core, to trigger a recovery. | |
268 | * | |
269 | * Return: IRQ_HANDLED on success, otherwise IRQ_NONE | |
270 | */ | |
271 | static irqreturn_t omap_rproc_watchdog_isr(int irq, void *data) | |
272 | { | |
273 | struct rproc *rproc = data; | |
274 | struct omap_rproc *oproc = rproc->priv; | |
275 | struct device *dev = rproc->dev.parent; | |
276 | struct omap_rproc_timer *timers = oproc->timers; | |
277 | struct omap_rproc_timer *wd_timer = NULL; | |
278 | int num_timers = oproc->num_timers + oproc->num_wd_timers; | |
279 | int i; | |
280 | ||
281 | for (i = oproc->num_timers; i < num_timers; i++) { | |
282 | if (timers[i].irq > 0 && irq == timers[i].irq) { | |
283 | wd_timer = &timers[i]; | |
284 | break; | |
285 | } | |
286 | } | |
287 | ||
288 | if (!wd_timer) { | |
289 | dev_err(dev, "invalid timer\n"); | |
290 | return IRQ_NONE; | |
291 | } | |
292 | ||
293 | omap_rproc_ack_timer_irq(wd_timer); | |
294 | ||
295 | rproc_report_crash(rproc, RPROC_WATCHDOG); | |
296 | ||
297 | return IRQ_HANDLED; | |
298 | } | |
299 | ||
e28edc57 SA |
300 | /** |
301 | * omap_rproc_enable_timers() - enable the timers for a remoteproc | |
302 | * @rproc: handle of a remote processor | |
303 | * @configure: boolean flag used to acquire and configure the timer handle | |
304 | * | |
305 | * This function is used primarily to enable the timers associated with | |
306 | * a remoteproc. The configure flag is provided to allow the driver to | |
307 | * to either acquire and start a timer (during device initialization) or | |
308 | * to just start a timer (during a resume operation). | |
309 | * | |
310 | * Return: 0 on success, otherwise an appropriate failure | |
311 | */ | |
312 | static int omap_rproc_enable_timers(struct rproc *rproc, bool configure) | |
313 | { | |
314 | int i; | |
315 | int ret = 0; | |
316 | struct platform_device *tpdev; | |
317 | struct dmtimer_platform_data *tpdata; | |
318 | const struct omap_dm_timer_ops *timer_ops; | |
319 | struct omap_rproc *oproc = rproc->priv; | |
320 | struct omap_rproc_timer *timers = oproc->timers; | |
321 | struct device *dev = rproc->dev.parent; | |
322 | struct device_node *np = NULL; | |
69591e4a | 323 | int num_timers = oproc->num_timers + oproc->num_wd_timers; |
e28edc57 | 324 | |
69591e4a | 325 | if (!num_timers) |
e28edc57 SA |
326 | return 0; |
327 | ||
328 | if (!configure) | |
329 | goto start_timers; | |
330 | ||
69591e4a SA |
331 | for (i = 0; i < num_timers; i++) { |
332 | if (i < oproc->num_timers) | |
333 | np = of_parse_phandle(dev->of_node, "ti,timers", i); | |
334 | else | |
335 | np = of_parse_phandle(dev->of_node, | |
336 | "ti,watchdog-timers", | |
337 | (i - oproc->num_timers)); | |
e28edc57 SA |
338 | if (!np) { |
339 | ret = -ENXIO; | |
340 | dev_err(dev, "device node lookup for timer at index %d failed: %d\n", | |
69591e4a SA |
341 | i < oproc->num_timers ? i : |
342 | i - oproc->num_timers, ret); | |
e28edc57 SA |
343 | goto free_timers; |
344 | } | |
345 | ||
346 | tpdev = of_find_device_by_node(np); | |
347 | if (!tpdev) { | |
348 | ret = -ENODEV; | |
349 | dev_err(dev, "could not get timer platform device\n"); | |
350 | goto put_node; | |
351 | } | |
352 | ||
353 | tpdata = dev_get_platdata(&tpdev->dev); | |
354 | put_device(&tpdev->dev); | |
355 | if (!tpdata) { | |
356 | ret = -EINVAL; | |
357 | dev_err(dev, "dmtimer pdata structure NULL\n"); | |
358 | goto put_node; | |
359 | } | |
360 | ||
361 | timer_ops = tpdata->timer_ops; | |
362 | if (!timer_ops || !timer_ops->request_by_node || | |
363 | !timer_ops->set_source || !timer_ops->set_load || | |
364 | !timer_ops->free || !timer_ops->start || | |
69591e4a SA |
365 | !timer_ops->stop || !timer_ops->get_irq || |
366 | !timer_ops->write_status) { | |
e28edc57 SA |
367 | ret = -EINVAL; |
368 | dev_err(dev, "device does not have required timer ops\n"); | |
369 | goto put_node; | |
370 | } | |
371 | ||
69591e4a | 372 | timers[i].irq = -1; |
e28edc57 SA |
373 | timers[i].timer_ops = timer_ops; |
374 | ret = omap_rproc_request_timer(dev, np, &timers[i]); | |
375 | if (ret) { | |
376 | dev_err(dev, "request for timer %p failed: %d\n", np, | |
377 | ret); | |
378 | goto put_node; | |
379 | } | |
380 | of_node_put(np); | |
69591e4a SA |
381 | |
382 | if (i >= oproc->num_timers) { | |
383 | timers[i].irq = omap_rproc_get_timer_irq(&timers[i]); | |
384 | if (timers[i].irq < 0) { | |
385 | dev_err(dev, "get_irq for timer %p failed: %d\n", | |
386 | np, timers[i].irq); | |
387 | ret = -EBUSY; | |
388 | goto free_timers; | |
389 | } | |
390 | ||
391 | ret = request_irq(timers[i].irq, | |
392 | omap_rproc_watchdog_isr, IRQF_SHARED, | |
393 | "rproc-wdt", rproc); | |
394 | if (ret) { | |
395 | dev_err(dev, "error requesting irq for timer %p\n", | |
396 | np); | |
397 | omap_rproc_release_timer(&timers[i]); | |
398 | timers[i].odt = NULL; | |
399 | timers[i].timer_ops = NULL; | |
400 | timers[i].irq = -1; | |
401 | goto free_timers; | |
402 | } | |
403 | } | |
e28edc57 SA |
404 | } |
405 | ||
406 | start_timers: | |
69591e4a | 407 | for (i = 0; i < num_timers; i++) { |
e28edc57 SA |
408 | ret = omap_rproc_start_timer(&timers[i]); |
409 | if (ret) { | |
410 | dev_err(dev, "start timer %p failed failed: %d\n", np, | |
411 | ret); | |
412 | break; | |
413 | } | |
414 | } | |
415 | if (ret) { | |
416 | while (i >= 0) { | |
417 | omap_rproc_stop_timer(&timers[i]); | |
418 | i--; | |
419 | } | |
420 | goto put_node; | |
421 | } | |
422 | return 0; | |
423 | ||
424 | put_node: | |
425 | if (configure) | |
426 | of_node_put(np); | |
427 | free_timers: | |
428 | while (i--) { | |
69591e4a SA |
429 | if (i >= oproc->num_timers) |
430 | free_irq(timers[i].irq, rproc); | |
e28edc57 SA |
431 | omap_rproc_release_timer(&timers[i]); |
432 | timers[i].odt = NULL; | |
433 | timers[i].timer_ops = NULL; | |
69591e4a | 434 | timers[i].irq = -1; |
e28edc57 SA |
435 | } |
436 | ||
437 | return ret; | |
438 | } | |
439 | ||
440 | /** | |
441 | * omap_rproc_disable_timers() - disable the timers for a remoteproc | |
442 | * @rproc: handle of a remote processor | |
443 | * @configure: boolean flag used to release the timer handle | |
444 | * | |
445 | * This function is used primarily to disable the timers associated with | |
446 | * a remoteproc. The configure flag is provided to allow the driver to | |
447 | * to either stop and release a timer (during device shutdown) or to just | |
448 | * stop a timer (during a suspend operation). | |
449 | * | |
450 | * Return: 0 on success or no timers | |
451 | */ | |
452 | static int omap_rproc_disable_timers(struct rproc *rproc, bool configure) | |
453 | { | |
454 | int i; | |
455 | struct omap_rproc *oproc = rproc->priv; | |
456 | struct omap_rproc_timer *timers = oproc->timers; | |
69591e4a | 457 | int num_timers = oproc->num_timers + oproc->num_wd_timers; |
e28edc57 | 458 | |
69591e4a | 459 | if (!num_timers) |
e28edc57 SA |
460 | return 0; |
461 | ||
69591e4a | 462 | for (i = 0; i < num_timers; i++) { |
e28edc57 SA |
463 | omap_rproc_stop_timer(&timers[i]); |
464 | if (configure) { | |
69591e4a SA |
465 | if (i >= oproc->num_timers) |
466 | free_irq(timers[i].irq, rproc); | |
e28edc57 SA |
467 | omap_rproc_release_timer(&timers[i]); |
468 | timers[i].odt = NULL; | |
469 | timers[i].timer_ops = NULL; | |
69591e4a | 470 | timers[i].irq = -1; |
e28edc57 SA |
471 | } |
472 | } | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
34ed5a33 OBC |
477 | /** |
478 | * omap_rproc_mbox_callback() - inbound mailbox message handler | |
8841a66a | 479 | * @client: mailbox client pointer used for requesting the mailbox channel |
34ed5a33 OBC |
480 | * @data: mailbox payload |
481 | * | |
482 | * This handler is invoked by omap's mailbox driver whenever a mailbox | |
483 | * message is received. Usually, the mailbox payload simply contains | |
484 | * the index of the virtqueue that is kicked by the remote processor, | |
485 | * and we let remoteproc core handle it. | |
486 | * | |
487 | * In addition to virtqueue indices, we also have some out-of-band values | |
488 | * that indicates different events. Those values are deliberately very | |
489 | * big so they don't coincide with virtqueue indices. | |
490 | */ | |
8841a66a | 491 | static void omap_rproc_mbox_callback(struct mbox_client *client, void *data) |
34ed5a33 | 492 | { |
8841a66a SA |
493 | struct omap_rproc *oproc = container_of(client, struct omap_rproc, |
494 | client); | |
b5ab5e24 | 495 | struct device *dev = oproc->rproc->dev.parent; |
34ed5a33 | 496 | const char *name = oproc->rproc->name; |
8841a66a | 497 | u32 msg = (u32)data; |
34ed5a33 OBC |
498 | |
499 | dev_dbg(dev, "mbox msg: 0x%x\n", msg); | |
500 | ||
501 | switch (msg) { | |
502 | case RP_MBOX_CRASH: | |
232ba6ca SA |
503 | /* |
504 | * remoteproc detected an exception, notify the rproc core. | |
505 | * The remoteproc core will handle the recovery. | |
506 | */ | |
34ed5a33 | 507 | dev_err(dev, "omap rproc %s crashed\n", name); |
232ba6ca | 508 | rproc_report_crash(oproc->rproc, RPROC_FATAL_ERROR); |
34ed5a33 OBC |
509 | break; |
510 | case RP_MBOX_ECHO_REPLY: | |
511 | dev_info(dev, "received echo reply from %s\n", name); | |
512 | break; | |
9077ac1a | 513 | case RP_MBOX_SUSPEND_ACK: |
9077ac1a SA |
514 | case RP_MBOX_SUSPEND_CANCEL: |
515 | oproc->suspend_acked = msg == RP_MBOX_SUSPEND_ACK; | |
516 | complete(&oproc->pm_comp); | |
517 | break; | |
34ed5a33 | 518 | default: |
8135d1d2 SA |
519 | if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG) |
520 | return; | |
521 | if (msg > oproc->rproc->max_notifyid) { | |
522 | dev_dbg(dev, "dropping unknown message 0x%x", msg); | |
523 | return; | |
524 | } | |
55f34080 | 525 | /* msg contains the index of the triggered vring */ |
34ed5a33 OBC |
526 | if (rproc_vq_interrupt(oproc->rproc, msg) == IRQ_NONE) |
527 | dev_dbg(dev, "no message was found in vqid %d\n", msg); | |
528 | } | |
34ed5a33 OBC |
529 | } |
530 | ||
531 | /* kick a virtqueue */ | |
532 | static void omap_rproc_kick(struct rproc *rproc, int vqid) | |
533 | { | |
534 | struct omap_rproc *oproc = rproc->priv; | |
b5ab5e24 | 535 | struct device *dev = rproc->dev.parent; |
34ed5a33 OBC |
536 | int ret; |
537 | ||
5f31b232 SA |
538 | /* wake up the rproc before kicking it */ |
539 | ret = pm_runtime_get_sync(dev); | |
540 | if (WARN_ON(ret < 0)) { | |
541 | dev_err(dev, "pm_runtime_get_sync() failed during kick, ret = %d\n", | |
542 | ret); | |
543 | pm_runtime_put_noidle(dev); | |
544 | return; | |
545 | } | |
546 | ||
34ed5a33 | 547 | /* send the index of the triggered virtqueue in the mailbox payload */ |
8841a66a SA |
548 | ret = mbox_send_message(oproc->mbox, (void *)vqid); |
549 | if (ret < 0) | |
14096c13 AS |
550 | dev_err(dev, "failed to send mailbox message, status = %d\n", |
551 | ret); | |
5f31b232 SA |
552 | |
553 | pm_runtime_mark_last_busy(dev); | |
554 | pm_runtime_put_autosuspend(dev); | |
34ed5a33 OBC |
555 | } |
556 | ||
75242927 SA |
557 | /** |
558 | * omap_rproc_write_dsp_boot_addr() - set boot address for DSP remote processor | |
559 | * @rproc: handle of a remote processor | |
560 | * | |
561 | * Set boot address for a supported DSP remote processor. | |
feae0300 SA |
562 | * |
563 | * Return: 0 on success, or -EINVAL if boot address is not aligned properly | |
75242927 | 564 | */ |
feae0300 | 565 | static int omap_rproc_write_dsp_boot_addr(struct rproc *rproc) |
75242927 | 566 | { |
feae0300 | 567 | struct device *dev = rproc->dev.parent; |
75242927 SA |
568 | struct omap_rproc *oproc = rproc->priv; |
569 | struct omap_rproc_boot_data *bdata = oproc->boot_data; | |
570 | u32 offset = bdata->boot_reg; | |
0aaf1913 SA |
571 | u32 value; |
572 | u32 mask; | |
75242927 | 573 | |
feae0300 SA |
574 | if (rproc->bootaddr & (SZ_1K - 1)) { |
575 | dev_err(dev, "invalid boot address 0x%llx, must be aligned on a 1KB boundary\n", | |
576 | rproc->bootaddr); | |
577 | return -EINVAL; | |
578 | } | |
579 | ||
0aaf1913 SA |
580 | value = rproc->bootaddr >> bdata->boot_reg_shift; |
581 | mask = ~(SZ_1K - 1) >> bdata->boot_reg_shift; | |
582 | ||
583 | return regmap_update_bits(bdata->syscon, offset, mask, value); | |
75242927 SA |
584 | } |
585 | ||
34ed5a33 OBC |
586 | /* |
587 | * Power up the remote processor. | |
588 | * | |
589 | * This function will be invoked only after the firmware for this rproc | |
590 | * was loaded, parsed successfully, and all of its resource requirements | |
591 | * were met. | |
592 | */ | |
593 | static int omap_rproc_start(struct rproc *rproc) | |
594 | { | |
595 | struct omap_rproc *oproc = rproc->priv; | |
b5ab5e24 | 596 | struct device *dev = rproc->dev.parent; |
34ed5a33 | 597 | int ret; |
8841a66a | 598 | struct mbox_client *client = &oproc->client; |
34ed5a33 | 599 | |
feae0300 SA |
600 | if (oproc->boot_data) { |
601 | ret = omap_rproc_write_dsp_boot_addr(rproc); | |
602 | if (ret) | |
603 | return ret; | |
604 | } | |
4980f465 | 605 | |
8841a66a SA |
606 | client->dev = dev; |
607 | client->tx_done = NULL; | |
608 | client->rx_callback = omap_rproc_mbox_callback; | |
609 | client->tx_block = false; | |
610 | client->knows_txdone = false; | |
34ed5a33 | 611 | |
75242927 | 612 | oproc->mbox = mbox_request_channel(client, 0); |
34ed5a33 | 613 | if (IS_ERR(oproc->mbox)) { |
8841a66a SA |
614 | ret = -EBUSY; |
615 | dev_err(dev, "mbox_request_channel failed: %ld\n", | |
616 | PTR_ERR(oproc->mbox)); | |
34ed5a33 OBC |
617 | return ret; |
618 | } | |
619 | ||
620 | /* | |
621 | * Ping the remote processor. this is only for sanity-sake; | |
622 | * there is no functional effect whatsoever. | |
623 | * | |
624 | * Note that the reply will _not_ arrive immediately: this message | |
625 | * will wait in the mailbox fifo until the remote processor is booted. | |
626 | */ | |
8841a66a SA |
627 | ret = mbox_send_message(oproc->mbox, (void *)RP_MBOX_ECHO_REQUEST); |
628 | if (ret < 0) { | |
629 | dev_err(dev, "mbox_send_message failed: %d\n", ret); | |
34ed5a33 OBC |
630 | goto put_mbox; |
631 | } | |
632 | ||
e28edc57 SA |
633 | ret = omap_rproc_enable_timers(rproc, true); |
634 | if (ret) { | |
635 | dev_err(dev, "omap_rproc_enable_timers failed: %d\n", ret); | |
636 | goto put_mbox; | |
637 | } | |
638 | ||
75242927 | 639 | ret = reset_control_deassert(oproc->reset); |
34ed5a33 | 640 | if (ret) { |
75242927 | 641 | dev_err(dev, "reset control deassert failed: %d\n", ret); |
e28edc57 | 642 | goto disable_timers; |
34ed5a33 OBC |
643 | } |
644 | ||
5f31b232 SA |
645 | /* |
646 | * remote processor is up, so update the runtime pm status and | |
647 | * enable the auto-suspend. The device usage count is incremented | |
648 | * manually for balancing it for auto-suspend | |
649 | */ | |
650 | pm_runtime_set_active(dev); | |
651 | pm_runtime_use_autosuspend(dev); | |
652 | pm_runtime_get_noresume(dev); | |
653 | pm_runtime_enable(dev); | |
654 | pm_runtime_mark_last_busy(dev); | |
655 | pm_runtime_put_autosuspend(dev); | |
656 | ||
34ed5a33 OBC |
657 | return 0; |
658 | ||
e28edc57 SA |
659 | disable_timers: |
660 | omap_rproc_disable_timers(rproc, true); | |
34ed5a33 | 661 | put_mbox: |
8841a66a | 662 | mbox_free_channel(oproc->mbox); |
34ed5a33 OBC |
663 | return ret; |
664 | } | |
665 | ||
666 | /* power off the remote processor */ | |
667 | static int omap_rproc_stop(struct rproc *rproc) | |
668 | { | |
5f31b232 | 669 | struct device *dev = rproc->dev.parent; |
34ed5a33 OBC |
670 | struct omap_rproc *oproc = rproc->priv; |
671 | int ret; | |
672 | ||
5f31b232 SA |
673 | /* |
674 | * cancel any possible scheduled runtime suspend by incrementing | |
675 | * the device usage count, and resuming the device. The remoteproc | |
676 | * also needs to be woken up if suspended, to avoid the remoteproc | |
677 | * OS to continue to remember any context that it has saved, and | |
678 | * avoid potential issues in misindentifying a subsequent device | |
679 | * reboot as a power restore boot | |
680 | */ | |
681 | ret = pm_runtime_get_sync(dev); | |
682 | if (ret < 0) { | |
683 | pm_runtime_put_noidle(dev); | |
684 | return ret; | |
685 | } | |
686 | ||
75242927 | 687 | ret = reset_control_assert(oproc->reset); |
34ed5a33 | 688 | if (ret) |
5f31b232 | 689 | goto out; |
34ed5a33 | 690 | |
e28edc57 SA |
691 | ret = omap_rproc_disable_timers(rproc, true); |
692 | if (ret) | |
5f31b232 | 693 | goto enable_device; |
e28edc57 | 694 | |
8841a66a | 695 | mbox_free_channel(oproc->mbox); |
34ed5a33 | 696 | |
5f31b232 SA |
697 | /* |
698 | * update the runtime pm states and status now that the remoteproc | |
699 | * has stopped | |
700 | */ | |
701 | pm_runtime_disable(dev); | |
702 | pm_runtime_dont_use_autosuspend(dev); | |
703 | pm_runtime_put_noidle(dev); | |
704 | pm_runtime_set_suspended(dev); | |
705 | ||
34ed5a33 | 706 | return 0; |
5f31b232 SA |
707 | |
708 | enable_device: | |
709 | reset_control_deassert(oproc->reset); | |
710 | out: | |
711 | /* schedule the next auto-suspend */ | |
712 | pm_runtime_mark_last_busy(dev); | |
713 | pm_runtime_put_autosuspend(dev); | |
714 | return ret; | |
34ed5a33 OBC |
715 | } |
716 | ||
530a1b57 SA |
717 | /** |
718 | * omap_rproc_da_to_va() - internal memory translation helper | |
719 | * @rproc: remote processor to apply the address translation for | |
720 | * @da: device address to translate | |
721 | * @len: length of the memory buffer | |
722 | * | |
723 | * Custom function implementing the rproc .da_to_va ops to provide address | |
724 | * translation (device address to kernel virtual address) for internal RAMs | |
725 | * present in a DSP or IPU device). The translated addresses can be used | |
726 | * either by the remoteproc core for loading, or by any rpmsg bus drivers. | |
727 | * | |
728 | * Return: translated virtual address in kernel memory space on success, | |
729 | * or NULL on failure. | |
730 | */ | |
731 | static void *omap_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) | |
732 | { | |
733 | struct omap_rproc *oproc = rproc->priv; | |
734 | int i; | |
735 | u32 offset; | |
736 | ||
737 | if (len <= 0) | |
738 | return NULL; | |
739 | ||
740 | if (!oproc->num_mems) | |
741 | return NULL; | |
742 | ||
743 | for (i = 0; i < oproc->num_mems; i++) { | |
744 | if (da >= oproc->mem[i].dev_addr && da + len <= | |
745 | oproc->mem[i].dev_addr + oproc->mem[i].size) { | |
746 | offset = da - oproc->mem[i].dev_addr; | |
747 | /* __force to make sparse happy with type conversion */ | |
748 | return (__force void *)(oproc->mem[i].cpu_addr + | |
749 | offset); | |
750 | } | |
751 | } | |
752 | ||
753 | return NULL; | |
754 | } | |
755 | ||
c008fad2 | 756 | static const struct rproc_ops omap_rproc_ops = { |
34ed5a33 OBC |
757 | .start = omap_rproc_start, |
758 | .stop = omap_rproc_stop, | |
759 | .kick = omap_rproc_kick, | |
530a1b57 | 760 | .da_to_va = omap_rproc_da_to_va, |
34ed5a33 OBC |
761 | }; |
762 | ||
9077ac1a SA |
763 | #ifdef CONFIG_PM |
764 | static bool _is_rproc_in_standby(struct omap_rproc *oproc) | |
765 | { | |
766 | return ti_clk_is_in_standby(oproc->fck); | |
767 | } | |
768 | ||
769 | /* 1 sec is long enough time to let the remoteproc side suspend the device */ | |
770 | #define DEF_SUSPEND_TIMEOUT 1000 | |
5f31b232 | 771 | static int _omap_rproc_suspend(struct rproc *rproc, bool auto_suspend) |
9077ac1a SA |
772 | { |
773 | struct device *dev = rproc->dev.parent; | |
774 | struct omap_rproc *oproc = rproc->priv; | |
775 | unsigned long to = msecs_to_jiffies(DEF_SUSPEND_TIMEOUT); | |
776 | unsigned long ta = jiffies + to; | |
5f31b232 SA |
777 | u32 suspend_msg = auto_suspend ? |
778 | RP_MBOX_SUSPEND_AUTO : RP_MBOX_SUSPEND_SYSTEM; | |
9077ac1a SA |
779 | int ret; |
780 | ||
781 | reinit_completion(&oproc->pm_comp); | |
782 | oproc->suspend_acked = false; | |
5f31b232 | 783 | ret = mbox_send_message(oproc->mbox, (void *)suspend_msg); |
9077ac1a SA |
784 | if (ret < 0) { |
785 | dev_err(dev, "PM mbox_send_message failed: %d\n", ret); | |
786 | return ret; | |
787 | } | |
788 | ||
789 | ret = wait_for_completion_timeout(&oproc->pm_comp, to); | |
790 | if (!oproc->suspend_acked) | |
791 | return -EBUSY; | |
792 | ||
793 | /* | |
794 | * The remoteproc side is returning the ACK message before saving the | |
795 | * context, because the context saving is performed within a SYS/BIOS | |
796 | * function, and it cannot have any inter-dependencies against the IPC | |
797 | * layer. Also, as the SYS/BIOS needs to preserve properly the processor | |
798 | * register set, sending this ACK or signalling the completion of the | |
799 | * context save through a shared memory variable can never be the | |
800 | * absolute last thing to be executed on the remoteproc side, and the | |
801 | * MPU cannot use the ACK message as a sync point to put the remoteproc | |
802 | * into reset. The only way to ensure that the remote processor has | |
803 | * completed saving the context is to check that the module has reached | |
804 | * STANDBY state (after saving the context, the SYS/BIOS executes the | |
805 | * appropriate target-specific WFI instruction causing the module to | |
806 | * enter STANDBY). | |
807 | */ | |
808 | while (!_is_rproc_in_standby(oproc)) { | |
809 | if (time_after(jiffies, ta)) | |
810 | return -ETIME; | |
811 | schedule(); | |
812 | } | |
813 | ||
814 | ret = reset_control_assert(oproc->reset); | |
815 | if (ret) { | |
816 | dev_err(dev, "reset assert during suspend failed %d\n", ret); | |
817 | return ret; | |
818 | } | |
819 | ||
820 | ret = omap_rproc_disable_timers(rproc, false); | |
821 | if (ret) { | |
822 | dev_err(dev, "disabling timers during suspend failed %d\n", | |
823 | ret); | |
824 | goto enable_device; | |
825 | } | |
826 | ||
5f31b232 SA |
827 | /* |
828 | * IOMMUs would have to be disabled specifically for runtime suspend. | |
829 | * They are handled automatically through System PM callbacks for | |
830 | * regular system suspend | |
831 | */ | |
832 | if (auto_suspend) { | |
833 | ret = omap_iommu_domain_deactivate(rproc->domain); | |
834 | if (ret) { | |
835 | dev_err(dev, "iommu domain deactivate failed %d\n", | |
836 | ret); | |
837 | goto enable_timers; | |
838 | } | |
839 | } | |
840 | ||
9077ac1a SA |
841 | return 0; |
842 | ||
5f31b232 SA |
843 | enable_timers: |
844 | /* ignore errors on re-enabling code */ | |
845 | omap_rproc_enable_timers(rproc, false); | |
9077ac1a SA |
846 | enable_device: |
847 | reset_control_deassert(oproc->reset); | |
848 | return ret; | |
849 | } | |
850 | ||
5f31b232 | 851 | static int _omap_rproc_resume(struct rproc *rproc, bool auto_suspend) |
9077ac1a SA |
852 | { |
853 | struct device *dev = rproc->dev.parent; | |
854 | struct omap_rproc *oproc = rproc->priv; | |
855 | int ret; | |
856 | ||
5f31b232 SA |
857 | /* |
858 | * IOMMUs would have to be enabled specifically for runtime resume. | |
859 | * They would have been already enabled automatically through System | |
860 | * PM callbacks for regular system resume | |
861 | */ | |
862 | if (auto_suspend) { | |
863 | ret = omap_iommu_domain_activate(rproc->domain); | |
864 | if (ret) { | |
865 | dev_err(dev, "omap_iommu activate failed %d\n", ret); | |
866 | goto out; | |
867 | } | |
868 | } | |
869 | ||
9077ac1a SA |
870 | /* boot address could be lost after suspend, so restore it */ |
871 | if (oproc->boot_data) { | |
872 | ret = omap_rproc_write_dsp_boot_addr(rproc); | |
873 | if (ret) { | |
874 | dev_err(dev, "boot address restore failed %d\n", ret); | |
5f31b232 | 875 | goto suspend_iommu; |
9077ac1a SA |
876 | } |
877 | } | |
878 | ||
879 | ret = omap_rproc_enable_timers(rproc, false); | |
880 | if (ret) { | |
881 | dev_err(dev, "enabling timers during resume failed %d\n", ret); | |
5f31b232 | 882 | goto suspend_iommu; |
9077ac1a SA |
883 | } |
884 | ||
885 | ret = reset_control_deassert(oproc->reset); | |
886 | if (ret) { | |
887 | dev_err(dev, "reset deassert during resume failed %d\n", ret); | |
888 | goto disable_timers; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | ||
893 | disable_timers: | |
894 | omap_rproc_disable_timers(rproc, false); | |
5f31b232 SA |
895 | suspend_iommu: |
896 | if (auto_suspend) | |
897 | omap_iommu_domain_deactivate(rproc->domain); | |
9077ac1a SA |
898 | out: |
899 | return ret; | |
900 | } | |
901 | ||
902 | static int __maybe_unused omap_rproc_suspend(struct device *dev) | |
903 | { | |
904 | struct platform_device *pdev = to_platform_device(dev); | |
905 | struct rproc *rproc = platform_get_drvdata(pdev); | |
5f31b232 | 906 | struct omap_rproc *oproc = rproc->priv; |
9077ac1a SA |
907 | int ret = 0; |
908 | ||
909 | mutex_lock(&rproc->lock); | |
910 | if (rproc->state == RPROC_OFFLINE) | |
911 | goto out; | |
912 | ||
913 | if (rproc->state == RPROC_SUSPENDED) | |
914 | goto out; | |
915 | ||
916 | if (rproc->state != RPROC_RUNNING) { | |
917 | ret = -EBUSY; | |
918 | goto out; | |
919 | } | |
920 | ||
5f31b232 | 921 | ret = _omap_rproc_suspend(rproc, false); |
9077ac1a SA |
922 | if (ret) { |
923 | dev_err(dev, "suspend failed %d\n", ret); | |
924 | goto out; | |
925 | } | |
926 | ||
5f31b232 SA |
927 | /* |
928 | * remoteproc is running at the time of system suspend, so remember | |
929 | * it so as to wake it up during system resume | |
930 | */ | |
931 | oproc->need_resume = true; | |
9077ac1a | 932 | rproc->state = RPROC_SUSPENDED; |
5f31b232 | 933 | |
9077ac1a SA |
934 | out: |
935 | mutex_unlock(&rproc->lock); | |
936 | return ret; | |
937 | } | |
938 | ||
939 | static int __maybe_unused omap_rproc_resume(struct device *dev) | |
940 | { | |
941 | struct platform_device *pdev = to_platform_device(dev); | |
942 | struct rproc *rproc = platform_get_drvdata(pdev); | |
5f31b232 | 943 | struct omap_rproc *oproc = rproc->priv; |
9077ac1a SA |
944 | int ret = 0; |
945 | ||
946 | mutex_lock(&rproc->lock); | |
947 | if (rproc->state == RPROC_OFFLINE) | |
948 | goto out; | |
949 | ||
950 | if (rproc->state != RPROC_SUSPENDED) { | |
951 | ret = -EBUSY; | |
952 | goto out; | |
953 | } | |
954 | ||
5f31b232 SA |
955 | /* |
956 | * remoteproc was auto-suspended at the time of system suspend, | |
957 | * so no need to wake-up the processor (leave it in suspended | |
958 | * state, will be woken up during a subsequent runtime_resume) | |
959 | */ | |
960 | if (!oproc->need_resume) | |
961 | goto out; | |
962 | ||
963 | ret = _omap_rproc_resume(rproc, false); | |
9077ac1a SA |
964 | if (ret) { |
965 | dev_err(dev, "resume failed %d\n", ret); | |
966 | goto out; | |
967 | } | |
968 | ||
5f31b232 SA |
969 | oproc->need_resume = false; |
970 | rproc->state = RPROC_RUNNING; | |
971 | ||
972 | pm_runtime_mark_last_busy(dev); | |
973 | out: | |
974 | mutex_unlock(&rproc->lock); | |
975 | return ret; | |
976 | } | |
977 | ||
978 | static int omap_rproc_runtime_suspend(struct device *dev) | |
979 | { | |
980 | struct rproc *rproc = dev_get_drvdata(dev); | |
981 | struct omap_rproc *oproc = rproc->priv; | |
982 | int ret; | |
983 | ||
984 | mutex_lock(&rproc->lock); | |
985 | if (rproc->state == RPROC_CRASHED) { | |
986 | dev_dbg(dev, "rproc cannot be runtime suspended when crashed!\n"); | |
987 | ret = -EBUSY; | |
988 | goto out; | |
989 | } | |
990 | ||
991 | if (WARN_ON(rproc->state != RPROC_RUNNING)) { | |
992 | dev_err(dev, "rproc cannot be runtime suspended when not running!\n"); | |
993 | ret = -EBUSY; | |
994 | goto out; | |
995 | } | |
996 | ||
997 | /* | |
998 | * do not even attempt suspend if the remote processor is not | |
999 | * idled for runtime auto-suspend | |
1000 | */ | |
1001 | if (!_is_rproc_in_standby(oproc)) { | |
1002 | ret = -EBUSY; | |
1003 | goto abort; | |
1004 | } | |
1005 | ||
1006 | ret = _omap_rproc_suspend(rproc, true); | |
1007 | if (ret) | |
1008 | goto abort; | |
1009 | ||
1010 | rproc->state = RPROC_SUSPENDED; | |
1011 | mutex_unlock(&rproc->lock); | |
1012 | return 0; | |
1013 | ||
1014 | abort: | |
1015 | pm_runtime_mark_last_busy(dev); | |
1016 | out: | |
1017 | mutex_unlock(&rproc->lock); | |
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | static int omap_rproc_runtime_resume(struct device *dev) | |
1022 | { | |
1023 | struct rproc *rproc = dev_get_drvdata(dev); | |
1024 | int ret; | |
1025 | ||
1026 | mutex_lock(&rproc->lock); | |
1027 | if (WARN_ON(rproc->state != RPROC_SUSPENDED)) { | |
1028 | dev_err(dev, "rproc cannot be runtime resumed if not suspended! state=%d\n", | |
1029 | rproc->state); | |
1030 | ret = -EBUSY; | |
1031 | goto out; | |
1032 | } | |
1033 | ||
1034 | ret = _omap_rproc_resume(rproc, true); | |
1035 | if (ret) { | |
1036 | dev_err(dev, "runtime resume failed %d\n", ret); | |
1037 | goto out; | |
1038 | } | |
1039 | ||
9077ac1a SA |
1040 | rproc->state = RPROC_RUNNING; |
1041 | out: | |
1042 | mutex_unlock(&rproc->lock); | |
1043 | return ret; | |
1044 | } | |
1045 | #endif /* CONFIG_PM */ | |
1046 | ||
4a032199 SA |
1047 | static const struct omap_rproc_mem_data ipu_mems[] = { |
1048 | { .name = "l2ram", .dev_addr = 0x20000000 }, | |
1049 | { }, | |
1050 | }; | |
1051 | ||
0aaf1913 SA |
1052 | static const struct omap_rproc_mem_data dra7_dsp_mems[] = { |
1053 | { .name = "l2ram", .dev_addr = 0x800000 }, | |
1054 | { .name = "l1pram", .dev_addr = 0xe00000 }, | |
1055 | { .name = "l1dram", .dev_addr = 0xf00000 }, | |
1056 | { }, | |
1057 | }; | |
1058 | ||
75242927 SA |
1059 | static const struct omap_rproc_dev_data omap4_dsp_dev_data = { |
1060 | .device_name = "dsp", | |
1061 | }; | |
1062 | ||
1063 | static const struct omap_rproc_dev_data omap4_ipu_dev_data = { | |
1064 | .device_name = "ipu", | |
4a032199 | 1065 | .mems = ipu_mems, |
75242927 SA |
1066 | }; |
1067 | ||
1068 | static const struct omap_rproc_dev_data omap5_dsp_dev_data = { | |
1069 | .device_name = "dsp", | |
1070 | }; | |
1071 | ||
1072 | static const struct omap_rproc_dev_data omap5_ipu_dev_data = { | |
1073 | .device_name = "ipu", | |
4a032199 | 1074 | .mems = ipu_mems, |
75242927 SA |
1075 | }; |
1076 | ||
0aaf1913 SA |
1077 | static const struct omap_rproc_dev_data dra7_dsp_dev_data = { |
1078 | .device_name = "dsp", | |
1079 | .mems = dra7_dsp_mems, | |
1080 | }; | |
1081 | ||
1082 | static const struct omap_rproc_dev_data dra7_ipu_dev_data = { | |
1083 | .device_name = "ipu", | |
1084 | .mems = ipu_mems, | |
1085 | }; | |
1086 | ||
75242927 SA |
1087 | static const struct of_device_id omap_rproc_of_match[] = { |
1088 | { | |
1089 | .compatible = "ti,omap4-dsp", | |
1090 | .data = &omap4_dsp_dev_data, | |
1091 | }, | |
1092 | { | |
1093 | .compatible = "ti,omap4-ipu", | |
1094 | .data = &omap4_ipu_dev_data, | |
1095 | }, | |
1096 | { | |
1097 | .compatible = "ti,omap5-dsp", | |
1098 | .data = &omap5_dsp_dev_data, | |
1099 | }, | |
1100 | { | |
1101 | .compatible = "ti,omap5-ipu", | |
1102 | .data = &omap5_ipu_dev_data, | |
1103 | }, | |
0aaf1913 SA |
1104 | { |
1105 | .compatible = "ti,dra7-dsp", | |
1106 | .data = &dra7_dsp_dev_data, | |
1107 | }, | |
1108 | { | |
1109 | .compatible = "ti,dra7-ipu", | |
1110 | .data = &dra7_ipu_dev_data, | |
1111 | }, | |
75242927 SA |
1112 | { |
1113 | /* end */ | |
1114 | }, | |
1115 | }; | |
1116 | MODULE_DEVICE_TABLE(of, omap_rproc_of_match); | |
1117 | ||
1118 | static const char *omap_rproc_get_firmware(struct platform_device *pdev) | |
1119 | { | |
1120 | const char *fw_name; | |
1121 | int ret; | |
1122 | ||
1123 | ret = of_property_read_string(pdev->dev.of_node, "firmware-name", | |
1124 | &fw_name); | |
1125 | if (ret) | |
1126 | return ERR_PTR(ret); | |
1127 | ||
1128 | return fw_name; | |
1129 | } | |
1130 | ||
1131 | static int omap_rproc_get_boot_data(struct platform_device *pdev, | |
1132 | struct rproc *rproc) | |
1133 | { | |
1134 | struct device_node *np = pdev->dev.of_node; | |
1135 | struct omap_rproc *oproc = rproc->priv; | |
1136 | const struct omap_rproc_dev_data *data; | |
1137 | int ret; | |
1138 | ||
1139 | data = of_device_get_match_data(&pdev->dev); | |
1140 | if (!data) | |
1141 | return -ENODEV; | |
1142 | ||
1143 | if (!of_property_read_bool(np, "ti,bootreg")) | |
1144 | return 0; | |
1145 | ||
1146 | oproc->boot_data = devm_kzalloc(&pdev->dev, sizeof(*oproc->boot_data), | |
1147 | GFP_KERNEL); | |
1148 | if (!oproc->boot_data) | |
1149 | return -ENOMEM; | |
1150 | ||
1151 | oproc->boot_data->syscon = | |
1152 | syscon_regmap_lookup_by_phandle(np, "ti,bootreg"); | |
1153 | if (IS_ERR(oproc->boot_data->syscon)) { | |
1154 | ret = PTR_ERR(oproc->boot_data->syscon); | |
1155 | return ret; | |
1156 | } | |
1157 | ||
1158 | if (of_property_read_u32_index(np, "ti,bootreg", 1, | |
1159 | &oproc->boot_data->boot_reg)) { | |
1160 | dev_err(&pdev->dev, "couldn't get the boot register\n"); | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | ||
0aaf1913 SA |
1164 | of_property_read_u32_index(np, "ti,bootreg", 2, |
1165 | &oproc->boot_data->boot_reg_shift); | |
1166 | ||
75242927 SA |
1167 | return 0; |
1168 | } | |
1169 | ||
4a032199 SA |
1170 | static int omap_rproc_of_get_internal_memories(struct platform_device *pdev, |
1171 | struct rproc *rproc) | |
1172 | { | |
1173 | struct omap_rproc *oproc = rproc->priv; | |
1174 | struct device *dev = &pdev->dev; | |
1175 | const struct omap_rproc_dev_data *data; | |
1176 | struct resource *res; | |
1177 | int num_mems; | |
1178 | int i; | |
1179 | ||
1180 | data = of_device_get_match_data(dev); | |
1181 | if (!data) | |
1182 | return -ENODEV; | |
1183 | ||
1184 | if (!data->mems) | |
1185 | return 0; | |
1186 | ||
1187 | num_mems = of_property_count_elems_of_size(dev->of_node, "reg", | |
1188 | sizeof(u32)) / 2; | |
1189 | ||
1190 | oproc->mem = devm_kcalloc(dev, num_mems, sizeof(*oproc->mem), | |
1191 | GFP_KERNEL); | |
1192 | if (!oproc->mem) | |
1193 | return -ENOMEM; | |
1194 | ||
1195 | for (i = 0; data->mems[i].name; i++) { | |
1196 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1197 | data->mems[i].name); | |
1198 | if (!res) { | |
1199 | dev_err(dev, "no memory defined for %s\n", | |
1200 | data->mems[i].name); | |
1201 | return -ENOMEM; | |
1202 | } | |
1203 | oproc->mem[i].cpu_addr = devm_ioremap_resource(dev, res); | |
1204 | if (IS_ERR(oproc->mem[i].cpu_addr)) { | |
1205 | dev_err(dev, "failed to parse and map %s memory\n", | |
1206 | data->mems[i].name); | |
1207 | return PTR_ERR(oproc->mem[i].cpu_addr); | |
1208 | } | |
1209 | oproc->mem[i].bus_addr = res->start; | |
1210 | oproc->mem[i].dev_addr = data->mems[i].dev_addr; | |
1211 | oproc->mem[i].size = resource_size(res); | |
1212 | ||
1213 | dev_dbg(dev, "memory %8s: bus addr %pa size 0x%x va %pK da 0x%x\n", | |
1214 | data->mems[i].name, &oproc->mem[i].bus_addr, | |
1215 | oproc->mem[i].size, oproc->mem[i].cpu_addr, | |
1216 | oproc->mem[i].dev_addr); | |
1217 | } | |
1218 | oproc->num_mems = num_mems; | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
69591e4a SA |
1223 | #ifdef CONFIG_OMAP_REMOTEPROC_WATCHDOG |
1224 | static int omap_rproc_count_wdog_timers(struct device *dev) | |
1225 | { | |
1226 | struct device_node *np = dev->of_node; | |
1227 | int ret; | |
1228 | ||
1229 | ret = of_count_phandle_with_args(np, "ti,watchdog-timers", NULL); | |
1230 | if (ret <= 0) { | |
1231 | dev_dbg(dev, "device does not have watchdog timers, status = %d\n", | |
1232 | ret); | |
1233 | ret = 0; | |
1234 | } | |
1235 | ||
1236 | return ret; | |
1237 | } | |
1238 | #else | |
1239 | static int omap_rproc_count_wdog_timers(struct device *dev) | |
1240 | { | |
1241 | return 0; | |
1242 | } | |
1243 | #endif | |
1244 | ||
e28edc57 SA |
1245 | static int omap_rproc_of_get_timers(struct platform_device *pdev, |
1246 | struct rproc *rproc) | |
1247 | { | |
1248 | struct device_node *np = pdev->dev.of_node; | |
1249 | struct omap_rproc *oproc = rproc->priv; | |
1250 | struct device *dev = &pdev->dev; | |
69591e4a | 1251 | int num_timers; |
e28edc57 SA |
1252 | |
1253 | /* | |
1254 | * Timer nodes are directly used in client nodes as phandles, so | |
1255 | * retrieve the count using appropriate size | |
1256 | */ | |
1257 | oproc->num_timers = of_count_phandle_with_args(np, "ti,timers", NULL); | |
1258 | if (oproc->num_timers <= 0) { | |
1259 | dev_dbg(dev, "device does not have timers, status = %d\n", | |
1260 | oproc->num_timers); | |
1261 | oproc->num_timers = 0; | |
1262 | } | |
1263 | ||
69591e4a SA |
1264 | oproc->num_wd_timers = omap_rproc_count_wdog_timers(dev); |
1265 | ||
1266 | num_timers = oproc->num_timers + oproc->num_wd_timers; | |
1267 | if (num_timers) { | |
1268 | oproc->timers = devm_kcalloc(dev, num_timers, | |
e28edc57 SA |
1269 | sizeof(*oproc->timers), |
1270 | GFP_KERNEL); | |
1271 | if (!oproc->timers) | |
1272 | return -ENOMEM; | |
1273 | ||
69591e4a SA |
1274 | dev_dbg(dev, "device has %d tick timers and %d watchdog timers\n", |
1275 | oproc->num_timers, oproc->num_wd_timers); | |
e28edc57 SA |
1276 | } |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
0fe763c5 | 1281 | static int omap_rproc_probe(struct platform_device *pdev) |
34ed5a33 | 1282 | { |
75242927 | 1283 | struct device_node *np = pdev->dev.of_node; |
34ed5a33 OBC |
1284 | struct omap_rproc *oproc; |
1285 | struct rproc *rproc; | |
75242927 | 1286 | const char *firmware; |
34ed5a33 | 1287 | int ret; |
75242927 SA |
1288 | struct reset_control *reset; |
1289 | ||
1290 | if (!np) { | |
1291 | dev_err(&pdev->dev, "only DT-based devices are supported\n"); | |
1292 | return -ENODEV; | |
1293 | } | |
1294 | ||
1295 | reset = devm_reset_control_array_get_exclusive(&pdev->dev); | |
1296 | if (IS_ERR(reset)) | |
1297 | return PTR_ERR(reset); | |
1298 | ||
1299 | firmware = omap_rproc_get_firmware(pdev); | |
1300 | if (IS_ERR(firmware)) | |
1301 | return PTR_ERR(firmware); | |
34ed5a33 OBC |
1302 | |
1303 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1304 | if (ret) { | |
6b039762 | 1305 | dev_err(&pdev->dev, "dma_set_coherent_mask: %d\n", ret); |
34ed5a33 OBC |
1306 | return ret; |
1307 | } | |
1308 | ||
75242927 SA |
1309 | rproc = rproc_alloc(&pdev->dev, dev_name(&pdev->dev), &omap_rproc_ops, |
1310 | firmware, sizeof(*oproc)); | |
34ed5a33 OBC |
1311 | if (!rproc) |
1312 | return -ENOMEM; | |
1313 | ||
1314 | oproc = rproc->priv; | |
1315 | oproc->rproc = rproc; | |
75242927 | 1316 | oproc->reset = reset; |
315491e5 SA |
1317 | /* All existing OMAP IPU and DSP processors have an MMU */ |
1318 | rproc->has_iommu = true; | |
34ed5a33 | 1319 | |
4a032199 SA |
1320 | ret = omap_rproc_of_get_internal_memories(pdev, rproc); |
1321 | if (ret) | |
1322 | goto free_rproc; | |
1323 | ||
75242927 SA |
1324 | ret = omap_rproc_get_boot_data(pdev, rproc); |
1325 | if (ret) | |
1326 | goto free_rproc; | |
e28edc57 SA |
1327 | |
1328 | ret = omap_rproc_of_get_timers(pdev, rproc); | |
1329 | if (ret) | |
1330 | goto free_rproc; | |
75242927 | 1331 | |
9077ac1a | 1332 | init_completion(&oproc->pm_comp); |
5f31b232 SA |
1333 | oproc->autosuspend_delay = DEFAULT_AUTOSUSPEND_DELAY; |
1334 | ||
1335 | of_property_read_u32(pdev->dev.of_node, "ti,autosuspend-delay-ms", | |
1336 | &oproc->autosuspend_delay); | |
1337 | ||
1338 | pm_runtime_set_autosuspend_delay(&pdev->dev, oproc->autosuspend_delay); | |
9077ac1a SA |
1339 | |
1340 | oproc->fck = devm_clk_get(&pdev->dev, 0); | |
1341 | if (IS_ERR(oproc->fck)) { | |
1342 | ret = PTR_ERR(oproc->fck); | |
1343 | goto free_rproc; | |
1344 | } | |
1345 | ||
f4af5bd2 SA |
1346 | ret = of_reserved_mem_device_init(&pdev->dev); |
1347 | if (ret) { | |
1348 | dev_warn(&pdev->dev, "device does not have specific CMA pool.\n"); | |
1349 | dev_warn(&pdev->dev, "Typically this should be provided,\n"); | |
1350 | dev_warn(&pdev->dev, "only omit if you know what you are doing.\n"); | |
1351 | } | |
1352 | ||
34ed5a33 OBC |
1353 | platform_set_drvdata(pdev, rproc); |
1354 | ||
160e7c84 | 1355 | ret = rproc_add(rproc); |
34ed5a33 | 1356 | if (ret) |
f4af5bd2 | 1357 | goto release_mem; |
34ed5a33 OBC |
1358 | |
1359 | return 0; | |
1360 | ||
f4af5bd2 SA |
1361 | release_mem: |
1362 | of_reserved_mem_device_release(&pdev->dev); | |
34ed5a33 | 1363 | free_rproc: |
433c0e04 | 1364 | rproc_free(rproc); |
34ed5a33 OBC |
1365 | return ret; |
1366 | } | |
1367 | ||
0fe763c5 | 1368 | static int omap_rproc_remove(struct platform_device *pdev) |
34ed5a33 OBC |
1369 | { |
1370 | struct rproc *rproc = platform_get_drvdata(pdev); | |
1371 | ||
160e7c84 | 1372 | rproc_del(rproc); |
433c0e04 | 1373 | rproc_free(rproc); |
f4af5bd2 | 1374 | of_reserved_mem_device_release(&pdev->dev); |
c6b5a276 OBC |
1375 | |
1376 | return 0; | |
34ed5a33 OBC |
1377 | } |
1378 | ||
9077ac1a SA |
1379 | static const struct dev_pm_ops omap_rproc_pm_ops = { |
1380 | SET_SYSTEM_SLEEP_PM_OPS(omap_rproc_suspend, omap_rproc_resume) | |
5f31b232 SA |
1381 | SET_RUNTIME_PM_OPS(omap_rproc_runtime_suspend, |
1382 | omap_rproc_runtime_resume, NULL) | |
9077ac1a SA |
1383 | }; |
1384 | ||
34ed5a33 OBC |
1385 | static struct platform_driver omap_rproc_driver = { |
1386 | .probe = omap_rproc_probe, | |
0fe763c5 | 1387 | .remove = omap_rproc_remove, |
34ed5a33 OBC |
1388 | .driver = { |
1389 | .name = "omap-rproc", | |
9077ac1a | 1390 | .pm = &omap_rproc_pm_ops, |
75242927 | 1391 | .of_match_table = omap_rproc_of_match, |
34ed5a33 OBC |
1392 | }, |
1393 | }; | |
1394 | ||
63d667bf | 1395 | module_platform_driver(omap_rproc_driver); |
34ed5a33 OBC |
1396 | |
1397 | MODULE_LICENSE("GPL v2"); | |
1398 | MODULE_DESCRIPTION("OMAP Remote Processor control driver"); |