]>
Commit | Line | Data |
---|---|---|
d4ce2de7 SA |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * PRU-ICSS remoteproc driver for various TI SoCs | |
4 | * | |
5 | * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ | |
6 | * | |
7 | * Author(s): | |
8 | * Suman Anna <s-anna@ti.com> | |
9 | * Andrew F. Davis <afd@ti.com> | |
10 | * Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments | |
11 | */ | |
12 | ||
13 | #include <linux/bitops.h> | |
20ad1de0 | 14 | #include <linux/debugfs.h> |
c75c9fda | 15 | #include <linux/irqdomain.h> |
d4ce2de7 SA |
16 | #include <linux/module.h> |
17 | #include <linux/of_device.h> | |
c75c9fda | 18 | #include <linux/of_irq.h> |
d4ce2de7 SA |
19 | #include <linux/pruss_driver.h> |
20 | #include <linux/remoteproc.h> | |
21 | ||
22 | #include "remoteproc_internal.h" | |
23 | #include "remoteproc_elf_helpers.h" | |
c75c9fda | 24 | #include "pru_rproc.h" |
d4ce2de7 SA |
25 | |
26 | /* PRU_ICSS_PRU_CTRL registers */ | |
27 | #define PRU_CTRL_CTRL 0x0000 | |
28 | #define PRU_CTRL_STS 0x0004 | |
20ad1de0 SA |
29 | #define PRU_CTRL_WAKEUP_EN 0x0008 |
30 | #define PRU_CTRL_CYCLE 0x000C | |
31 | #define PRU_CTRL_STALL 0x0010 | |
32 | #define PRU_CTRL_CTBIR0 0x0020 | |
33 | #define PRU_CTRL_CTBIR1 0x0024 | |
34 | #define PRU_CTRL_CTPPR0 0x0028 | |
35 | #define PRU_CTRL_CTPPR1 0x002C | |
d4ce2de7 SA |
36 | |
37 | /* CTRL register bit-fields */ | |
38 | #define CTRL_CTRL_SOFT_RST_N BIT(0) | |
39 | #define CTRL_CTRL_EN BIT(1) | |
40 | #define CTRL_CTRL_SLEEPING BIT(2) | |
41 | #define CTRL_CTRL_CTR_EN BIT(3) | |
42 | #define CTRL_CTRL_SINGLE_STEP BIT(8) | |
43 | #define CTRL_CTRL_RUNSTATE BIT(15) | |
44 | ||
20ad1de0 SA |
45 | /* PRU_ICSS_PRU_DEBUG registers */ |
46 | #define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) | |
47 | #define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) | |
48 | ||
1d39f4d1 | 49 | /* PRU/RTU/Tx_PRU Core IRAM address masks */ |
d4ce2de7 SA |
50 | #define PRU_IRAM_ADDR_MASK 0x3ffff |
51 | #define PRU0_IRAM_ADDR_MASK 0x34000 | |
52 | #define PRU1_IRAM_ADDR_MASK 0x38000 | |
1d39f4d1 SA |
53 | #define RTU0_IRAM_ADDR_MASK 0x4000 |
54 | #define RTU1_IRAM_ADDR_MASK 0x6000 | |
55 | #define TX_PRU0_IRAM_ADDR_MASK 0xa000 | |
56 | #define TX_PRU1_IRAM_ADDR_MASK 0xc000 | |
d4ce2de7 SA |
57 | |
58 | /* PRU device addresses for various type of PRU RAMs */ | |
59 | #define PRU_IRAM_DA 0 /* Instruction RAM */ | |
60 | #define PRU_PDRAM_DA 0 /* Primary Data RAM */ | |
61 | #define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ | |
62 | #define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ | |
63 | ||
c75c9fda GJ |
64 | #define MAX_PRU_SYS_EVENTS 160 |
65 | ||
d4ce2de7 SA |
66 | /** |
67 | * enum pru_iomem - PRU core memory/register range identifiers | |
68 | * | |
69 | * @PRU_IOMEM_IRAM: PRU Instruction RAM range | |
70 | * @PRU_IOMEM_CTRL: PRU Control register range | |
71 | * @PRU_IOMEM_DEBUG: PRU Debug register range | |
72 | * @PRU_IOMEM_MAX: just keep this one at the end | |
73 | */ | |
74 | enum pru_iomem { | |
75 | PRU_IOMEM_IRAM = 0, | |
76 | PRU_IOMEM_CTRL, | |
77 | PRU_IOMEM_DEBUG, | |
78 | PRU_IOMEM_MAX, | |
79 | }; | |
80 | ||
1d39f4d1 SA |
81 | /** |
82 | * enum pru_type - PRU core type identifier | |
83 | * | |
84 | * @PRU_TYPE_PRU: Programmable Real-time Unit | |
85 | * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit | |
86 | * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit | |
87 | * @PRU_TYPE_MAX: just keep this one at the end | |
88 | */ | |
89 | enum pru_type { | |
90 | PRU_TYPE_PRU = 0, | |
91 | PRU_TYPE_RTU, | |
92 | PRU_TYPE_TX_PRU, | |
93 | PRU_TYPE_MAX, | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct pru_private_data - device data for a PRU core | |
98 | * @type: type of the PRU core (PRU, RTU, Tx_PRU) | |
99 | * @is_k3: flag used to identify the need for special load handling | |
100 | */ | |
101 | struct pru_private_data { | |
102 | enum pru_type type; | |
103 | unsigned int is_k3 : 1; | |
104 | }; | |
105 | ||
d4ce2de7 SA |
106 | /** |
107 | * struct pru_rproc - PRU remoteproc structure | |
108 | * @id: id of the PRU core within the PRUSS | |
109 | * @dev: PRU core device pointer | |
110 | * @pruss: back-reference to parent PRUSS structure | |
111 | * @rproc: remoteproc pointer for this PRU core | |
1d39f4d1 | 112 | * @data: PRU core specific data |
d4ce2de7 SA |
113 | * @mem_regions: data for each of the PRU memory regions |
114 | * @fw_name: name of firmware image used during loading | |
c75c9fda GJ |
115 | * @mapped_irq: virtual interrupt numbers of created fw specific mapping |
116 | * @pru_interrupt_map: pointer to interrupt mapping description (firmware) | |
117 | * @pru_interrupt_map_sz: pru_interrupt_map size | |
20ad1de0 SA |
118 | * @dbg_single_step: debug state variable to set PRU into single step mode |
119 | * @dbg_continuous: debug state variable to restore PRU execution mode | |
c75c9fda | 120 | * @evt_count: number of mapped events |
d4ce2de7 SA |
121 | */ |
122 | struct pru_rproc { | |
123 | int id; | |
124 | struct device *dev; | |
125 | struct pruss *pruss; | |
126 | struct rproc *rproc; | |
1d39f4d1 | 127 | const struct pru_private_data *data; |
d4ce2de7 SA |
128 | struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; |
129 | const char *fw_name; | |
c75c9fda GJ |
130 | unsigned int *mapped_irq; |
131 | struct pru_irq_rsc *pru_interrupt_map; | |
132 | size_t pru_interrupt_map_sz; | |
20ad1de0 SA |
133 | u32 dbg_single_step; |
134 | u32 dbg_continuous; | |
c75c9fda | 135 | u8 evt_count; |
d4ce2de7 SA |
136 | }; |
137 | ||
138 | static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) | |
139 | { | |
140 | return readl_relaxed(pru->mem_regions[PRU_IOMEM_CTRL].va + reg); | |
141 | } | |
142 | ||
143 | static inline | |
144 | void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) | |
145 | { | |
146 | writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); | |
147 | } | |
148 | ||
20ad1de0 SA |
149 | static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg) |
150 | { | |
151 | return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg); | |
152 | } | |
153 | ||
154 | static int regs_show(struct seq_file *s, void *data) | |
155 | { | |
156 | struct rproc *rproc = s->private; | |
157 | struct pru_rproc *pru = rproc->priv; | |
158 | int i, nregs = 32; | |
159 | u32 pru_sts; | |
160 | int pru_is_running; | |
161 | ||
162 | seq_puts(s, "============== Control Registers ==============\n"); | |
163 | seq_printf(s, "CTRL := 0x%08x\n", | |
164 | pru_control_read_reg(pru, PRU_CTRL_CTRL)); | |
165 | pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS); | |
166 | seq_printf(s, "STS (PC) := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2); | |
167 | seq_printf(s, "WAKEUP_EN := 0x%08x\n", | |
168 | pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN)); | |
169 | seq_printf(s, "CYCLE := 0x%08x\n", | |
170 | pru_control_read_reg(pru, PRU_CTRL_CYCLE)); | |
171 | seq_printf(s, "STALL := 0x%08x\n", | |
172 | pru_control_read_reg(pru, PRU_CTRL_STALL)); | |
173 | seq_printf(s, "CTBIR0 := 0x%08x\n", | |
174 | pru_control_read_reg(pru, PRU_CTRL_CTBIR0)); | |
175 | seq_printf(s, "CTBIR1 := 0x%08x\n", | |
176 | pru_control_read_reg(pru, PRU_CTRL_CTBIR1)); | |
177 | seq_printf(s, "CTPPR0 := 0x%08x\n", | |
178 | pru_control_read_reg(pru, PRU_CTRL_CTPPR0)); | |
179 | seq_printf(s, "CTPPR1 := 0x%08x\n", | |
180 | pru_control_read_reg(pru, PRU_CTRL_CTPPR1)); | |
181 | ||
182 | seq_puts(s, "=============== Debug Registers ===============\n"); | |
183 | pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) & | |
184 | CTRL_CTRL_RUNSTATE; | |
185 | if (pru_is_running) { | |
186 | seq_puts(s, "PRU is executing, cannot print/access debug registers.\n"); | |
187 | return 0; | |
188 | } | |
189 | ||
190 | for (i = 0; i < nregs; i++) { | |
191 | seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n", | |
192 | i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)), | |
193 | i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i))); | |
194 | } | |
195 | ||
196 | return 0; | |
197 | } | |
198 | DEFINE_SHOW_ATTRIBUTE(regs); | |
199 | ||
200 | /* | |
201 | * Control PRU single-step mode | |
202 | * | |
203 | * This is a debug helper function used for controlling the single-step | |
204 | * mode of the PRU. The PRU Debug registers are not accessible when the | |
205 | * PRU is in RUNNING state. | |
206 | * | |
207 | * Writing a non-zero value sets the PRU into single-step mode irrespective | |
208 | * of its previous state. The PRU mode is saved only on the first set into | |
209 | * a single-step mode. Writing a zero value will restore the PRU into its | |
210 | * original mode. | |
211 | */ | |
212 | static int pru_rproc_debug_ss_set(void *data, u64 val) | |
213 | { | |
214 | struct rproc *rproc = data; | |
215 | struct pru_rproc *pru = rproc->priv; | |
216 | u32 reg_val; | |
217 | ||
218 | val = val ? 1 : 0; | |
219 | if (!val && !pru->dbg_single_step) | |
220 | return 0; | |
221 | ||
222 | reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL); | |
223 | ||
224 | if (val && !pru->dbg_single_step) | |
225 | pru->dbg_continuous = reg_val; | |
226 | ||
227 | if (val) | |
228 | reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN; | |
229 | else | |
230 | reg_val = pru->dbg_continuous; | |
231 | ||
232 | pru->dbg_single_step = val; | |
233 | pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static int pru_rproc_debug_ss_get(void *data, u64 *val) | |
239 | { | |
240 | struct rproc *rproc = data; | |
241 | struct pru_rproc *pru = rproc->priv; | |
242 | ||
243 | *val = pru->dbg_single_step; | |
244 | ||
245 | return 0; | |
246 | } | |
247 | DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get, | |
248 | pru_rproc_debug_ss_set, "%llu\n"); | |
249 | ||
250 | /* | |
251 | * Create PRU-specific debugfs entries | |
252 | * | |
253 | * The entries are created only if the parent remoteproc debugfs directory | |
254 | * exists, and will be cleaned up by the remoteproc core. | |
255 | */ | |
256 | static void pru_rproc_create_debug_entries(struct rproc *rproc) | |
257 | { | |
258 | if (!rproc->dbg_dir) | |
259 | return; | |
260 | ||
261 | debugfs_create_file("regs", 0400, rproc->dbg_dir, | |
262 | rproc, ®s_fops); | |
263 | debugfs_create_file("single_step", 0600, rproc->dbg_dir, | |
264 | rproc, &pru_rproc_debug_ss_fops); | |
265 | } | |
266 | ||
c75c9fda GJ |
267 | static void pru_dispose_irq_mapping(struct pru_rproc *pru) |
268 | { | |
269 | while (pru->evt_count--) { | |
270 | if (pru->mapped_irq[pru->evt_count] > 0) | |
271 | irq_dispose_mapping(pru->mapped_irq[pru->evt_count]); | |
272 | } | |
273 | ||
274 | kfree(pru->mapped_irq); | |
275 | } | |
276 | ||
277 | /* | |
278 | * Parse the custom PRU interrupt map resource and configure the INTC | |
279 | * appropriately. | |
280 | */ | |
281 | static int pru_handle_intrmap(struct rproc *rproc) | |
282 | { | |
283 | struct device *dev = rproc->dev.parent; | |
284 | struct pru_rproc *pru = rproc->priv; | |
285 | struct pru_irq_rsc *rsc = pru->pru_interrupt_map; | |
286 | struct irq_fwspec fwspec; | |
287 | struct device_node *irq_parent; | |
288 | int i, ret = 0; | |
289 | ||
290 | /* not having pru_interrupt_map is not an error */ | |
291 | if (!rsc) | |
292 | return 0; | |
293 | ||
294 | /* currently supporting only type 0 */ | |
295 | if (rsc->type != 0) { | |
296 | dev_err(dev, "unsupported rsc type: %d\n", rsc->type); | |
297 | return -EINVAL; | |
298 | } | |
299 | ||
300 | if (rsc->num_evts > MAX_PRU_SYS_EVENTS) | |
301 | return -EINVAL; | |
302 | ||
303 | if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) != | |
304 | pru->pru_interrupt_map_sz) | |
305 | return -EINVAL; | |
306 | ||
307 | pru->evt_count = rsc->num_evts; | |
308 | pru->mapped_irq = kcalloc(pru->evt_count, sizeof(unsigned int), | |
309 | GFP_KERNEL); | |
310 | if (!pru->mapped_irq) | |
311 | return -ENOMEM; | |
312 | ||
313 | /* | |
314 | * parse and fill in system event to interrupt channel and | |
315 | * channel-to-host mapping | |
316 | */ | |
317 | irq_parent = of_irq_find_parent(pru->dev->of_node); | |
318 | if (!irq_parent) { | |
319 | kfree(pru->mapped_irq); | |
320 | return -ENODEV; | |
321 | } | |
322 | ||
323 | fwspec.fwnode = of_node_to_fwnode(irq_parent); | |
324 | fwspec.param_count = 3; | |
325 | for (i = 0; i < pru->evt_count; i++) { | |
326 | fwspec.param[0] = rsc->pru_intc_map[i].event; | |
327 | fwspec.param[1] = rsc->pru_intc_map[i].chnl; | |
328 | fwspec.param[2] = rsc->pru_intc_map[i].host; | |
329 | ||
330 | dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", | |
331 | i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); | |
332 | ||
333 | pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec); | |
334 | if (!pru->mapped_irq[i]) { | |
335 | dev_err(dev, "failed to get virq\n"); | |
336 | ret = pru->mapped_irq[i]; | |
337 | goto map_fail; | |
338 | } | |
339 | } | |
340 | ||
341 | return ret; | |
342 | ||
343 | map_fail: | |
344 | pru_dispose_irq_mapping(pru); | |
345 | ||
346 | return ret; | |
347 | } | |
348 | ||
d4ce2de7 SA |
349 | static int pru_rproc_start(struct rproc *rproc) |
350 | { | |
351 | struct device *dev = &rproc->dev; | |
352 | struct pru_rproc *pru = rproc->priv; | |
1d39f4d1 | 353 | const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; |
d4ce2de7 | 354 | u32 val; |
c75c9fda | 355 | int ret; |
d4ce2de7 | 356 | |
1d39f4d1 SA |
357 | dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n", |
358 | names[pru->data->type], pru->id, (rproc->bootaddr >> 2)); | |
d4ce2de7 | 359 | |
c75c9fda GJ |
360 | ret = pru_handle_intrmap(rproc); |
361 | /* | |
362 | * reset references to pru interrupt map - they will stop being valid | |
363 | * after rproc_start returns | |
364 | */ | |
365 | pru->pru_interrupt_map = NULL; | |
366 | pru->pru_interrupt_map_sz = 0; | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
d4ce2de7 SA |
370 | val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); |
371 | pru_control_write_reg(pru, PRU_CTRL_CTRL, val); | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | static int pru_rproc_stop(struct rproc *rproc) | |
377 | { | |
378 | struct device *dev = &rproc->dev; | |
379 | struct pru_rproc *pru = rproc->priv; | |
1d39f4d1 | 380 | const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; |
d4ce2de7 SA |
381 | u32 val; |
382 | ||
1d39f4d1 | 383 | dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id); |
d4ce2de7 SA |
384 | |
385 | val = pru_control_read_reg(pru, PRU_CTRL_CTRL); | |
386 | val &= ~CTRL_CTRL_EN; | |
387 | pru_control_write_reg(pru, PRU_CTRL_CTRL, val); | |
388 | ||
c75c9fda GJ |
389 | /* dispose irq mapping - new firmware can provide new mapping */ |
390 | if (pru->mapped_irq) | |
391 | pru_dispose_irq_mapping(pru); | |
392 | ||
d4ce2de7 SA |
393 | return 0; |
394 | } | |
395 | ||
396 | /* | |
397 | * Convert PRU device address (data spaces only) to kernel virtual address. | |
398 | * | |
399 | * Each PRU has access to all data memories within the PRUSS, accessible at | |
400 | * different ranges. So, look through both its primary and secondary Data | |
401 | * RAMs as well as any shared Data RAM to convert a PRU device address to | |
402 | * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data | |
403 | * RAM1 is primary Data RAM for PRU1. | |
404 | */ | |
405 | static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len) | |
406 | { | |
407 | struct pruss_mem_region dram0, dram1, shrd_ram; | |
408 | struct pruss *pruss = pru->pruss; | |
409 | u32 offset; | |
410 | void *va = NULL; | |
411 | ||
412 | if (len == 0) | |
413 | return NULL; | |
414 | ||
415 | dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0]; | |
416 | dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1]; | |
417 | /* PRU1 has its local RAM addresses reversed */ | |
418 | if (pru->id == 1) | |
419 | swap(dram0, dram1); | |
420 | shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2]; | |
421 | ||
422 | if (da >= PRU_PDRAM_DA && da + len <= PRU_PDRAM_DA + dram0.size) { | |
423 | offset = da - PRU_PDRAM_DA; | |
424 | va = (__force void *)(dram0.va + offset); | |
425 | } else if (da >= PRU_SDRAM_DA && | |
426 | da + len <= PRU_SDRAM_DA + dram1.size) { | |
427 | offset = da - PRU_SDRAM_DA; | |
428 | va = (__force void *)(dram1.va + offset); | |
429 | } else if (da >= PRU_SHRDRAM_DA && | |
430 | da + len <= PRU_SHRDRAM_DA + shrd_ram.size) { | |
431 | offset = da - PRU_SHRDRAM_DA; | |
432 | va = (__force void *)(shrd_ram.va + offset); | |
433 | } | |
434 | ||
435 | return va; | |
436 | } | |
437 | ||
438 | /* | |
439 | * Convert PRU device address (instruction space) to kernel virtual address. | |
440 | * | |
441 | * A PRU does not have an unified address space. Each PRU has its very own | |
442 | * private Instruction RAM, and its device address is identical to that of | |
443 | * its primary Data RAM device address. | |
444 | */ | |
445 | static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len) | |
446 | { | |
447 | u32 offset; | |
448 | void *va = NULL; | |
449 | ||
450 | if (len == 0) | |
451 | return NULL; | |
452 | ||
453 | if (da >= PRU_IRAM_DA && | |
454 | da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) { | |
455 | offset = da - PRU_IRAM_DA; | |
456 | va = (__force void *)(pru->mem_regions[PRU_IOMEM_IRAM].va + | |
457 | offset); | |
458 | } | |
459 | ||
460 | return va; | |
461 | } | |
462 | ||
463 | /* | |
464 | * Provide address translations for only PRU Data RAMs through the remoteproc | |
465 | * core for any PRU client drivers. The PRU Instruction RAM access is restricted | |
466 | * only to the PRU loader code. | |
467 | */ | |
468 | static void *pru_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) | |
469 | { | |
470 | struct pru_rproc *pru = rproc->priv; | |
471 | ||
472 | return pru_d_da_to_va(pru, da, len); | |
473 | } | |
474 | ||
475 | /* PRU-specific address translator used by PRU loader. */ | |
476 | static void *pru_da_to_va(struct rproc *rproc, u64 da, size_t len, bool is_iram) | |
477 | { | |
478 | struct pru_rproc *pru = rproc->priv; | |
479 | void *va; | |
480 | ||
481 | if (is_iram) | |
482 | va = pru_i_da_to_va(pru, da, len); | |
483 | else | |
484 | va = pru_d_da_to_va(pru, da, len); | |
485 | ||
486 | return va; | |
487 | } | |
488 | ||
489 | static struct rproc_ops pru_rproc_ops = { | |
490 | .start = pru_rproc_start, | |
491 | .stop = pru_rproc_stop, | |
492 | .da_to_va = pru_rproc_da_to_va, | |
493 | }; | |
494 | ||
1d39f4d1 SA |
495 | /* |
496 | * Custom memory copy implementation for ICSSG PRU/RTU/Tx_PRU Cores | |
497 | * | |
498 | * The ICSSG PRU/RTU/Tx_PRU cores have a memory copying issue with IRAM | |
499 | * memories, that is not seen on previous generation SoCs. The data is reflected | |
500 | * properly in the IRAM memories only for integer (4-byte) copies. Any unaligned | |
501 | * copies result in all the other pre-existing bytes zeroed out within that | |
502 | * 4-byte boundary, thereby resulting in wrong text/code in the IRAMs. Also, the | |
503 | * IRAM memory port interface does not allow any 8-byte copies (as commonly used | |
504 | * by ARM64 memcpy implementation) and throws an exception. The DRAM memory | |
505 | * ports do not show this behavior. | |
506 | */ | |
507 | static int pru_rproc_memcpy(void *dest, const void *src, size_t count) | |
508 | { | |
509 | const u32 *s = src; | |
510 | u32 *d = dest; | |
511 | size_t size = count / 4; | |
512 | u32 *tmp_src = NULL; | |
513 | ||
514 | /* | |
515 | * TODO: relax limitation of 4-byte aligned dest addresses and copy | |
516 | * sizes | |
517 | */ | |
518 | if ((long)dest % 4 || count % 4) | |
519 | return -EINVAL; | |
520 | ||
521 | /* src offsets in ELF firmware image can be non-aligned */ | |
522 | if ((long)src % 4) { | |
523 | tmp_src = kmemdup(src, count, GFP_KERNEL); | |
524 | if (!tmp_src) | |
525 | return -ENOMEM; | |
526 | s = tmp_src; | |
527 | } | |
528 | ||
529 | while (size--) | |
530 | *d++ = *s++; | |
531 | ||
532 | kfree(tmp_src); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
d4ce2de7 SA |
537 | static int |
538 | pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) | |
539 | { | |
1d39f4d1 | 540 | struct pru_rproc *pru = rproc->priv; |
d4ce2de7 SA |
541 | struct device *dev = &rproc->dev; |
542 | struct elf32_hdr *ehdr; | |
543 | struct elf32_phdr *phdr; | |
544 | int i, ret = 0; | |
545 | const u8 *elf_data = fw->data; | |
546 | ||
547 | ehdr = (struct elf32_hdr *)elf_data; | |
548 | phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff); | |
549 | ||
550 | /* go through the available ELF segments */ | |
551 | for (i = 0; i < ehdr->e_phnum; i++, phdr++) { | |
552 | u32 da = phdr->p_paddr; | |
553 | u32 memsz = phdr->p_memsz; | |
554 | u32 filesz = phdr->p_filesz; | |
555 | u32 offset = phdr->p_offset; | |
556 | bool is_iram; | |
557 | void *ptr; | |
558 | ||
559 | if (phdr->p_type != PT_LOAD || !filesz) | |
560 | continue; | |
561 | ||
562 | dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", | |
563 | phdr->p_type, da, memsz, filesz); | |
564 | ||
565 | if (filesz > memsz) { | |
566 | dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n", | |
567 | filesz, memsz); | |
568 | ret = -EINVAL; | |
569 | break; | |
570 | } | |
571 | ||
572 | if (offset + filesz > fw->size) { | |
573 | dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n", | |
574 | offset + filesz, fw->size); | |
575 | ret = -EINVAL; | |
576 | break; | |
577 | } | |
578 | ||
579 | /* grab the kernel address for this device address */ | |
580 | is_iram = phdr->p_flags & PF_X; | |
581 | ptr = pru_da_to_va(rproc, da, memsz, is_iram); | |
582 | if (!ptr) { | |
583 | dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); | |
584 | ret = -EINVAL; | |
585 | break; | |
586 | } | |
587 | ||
1d39f4d1 SA |
588 | if (pru->data->is_k3 && is_iram) { |
589 | ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset, | |
590 | filesz); | |
591 | if (ret) { | |
592 | dev_err(dev, "PRU memory copy failed for da 0x%x memsz 0x%x\n", | |
593 | da, memsz); | |
594 | break; | |
595 | } | |
596 | } else { | |
597 | memcpy(ptr, elf_data + phdr->p_offset, filesz); | |
598 | } | |
d4ce2de7 SA |
599 | |
600 | /* skip the memzero logic performed by remoteproc ELF loader */ | |
601 | } | |
602 | ||
603 | return ret; | |
604 | } | |
605 | ||
c75c9fda GJ |
606 | static const void * |
607 | pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw) | |
608 | { | |
609 | struct elf32_shdr *shdr, *name_table_shdr; | |
610 | const char *name_table; | |
611 | const u8 *elf_data = fw->data; | |
612 | struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data; | |
613 | u16 shnum = ehdr->e_shnum; | |
614 | u16 shstrndx = ehdr->e_shstrndx; | |
615 | int i; | |
616 | ||
617 | /* first, get the section header */ | |
618 | shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff); | |
619 | /* compute name table section header entry in shdr array */ | |
620 | name_table_shdr = shdr + shstrndx; | |
621 | /* finally, compute the name table section address in elf */ | |
622 | name_table = elf_data + name_table_shdr->sh_offset; | |
623 | ||
624 | for (i = 0; i < shnum; i++, shdr++) { | |
625 | u32 size = shdr->sh_size; | |
626 | u32 offset = shdr->sh_offset; | |
627 | u32 name = shdr->sh_name; | |
628 | ||
629 | if (strcmp(name_table + name, ".pru_irq_map")) | |
630 | continue; | |
631 | ||
632 | /* make sure we have the entire irq map */ | |
633 | if (offset + size > fw->size || offset + size < size) { | |
634 | dev_err(dev, ".pru_irq_map section truncated\n"); | |
635 | return ERR_PTR(-EINVAL); | |
636 | } | |
637 | ||
638 | /* make sure irq map has at least the header */ | |
639 | if (sizeof(struct pru_irq_rsc) > size) { | |
640 | dev_err(dev, "header-less .pru_irq_map section\n"); | |
641 | return ERR_PTR(-EINVAL); | |
642 | } | |
643 | ||
644 | return shdr; | |
645 | } | |
646 | ||
647 | dev_dbg(dev, "no .pru_irq_map section found for this fw\n"); | |
648 | ||
649 | return NULL; | |
650 | } | |
651 | ||
d4ce2de7 SA |
652 | /* |
653 | * Use a custom parse_fw callback function for dealing with PRU firmware | |
654 | * specific sections. | |
c75c9fda GJ |
655 | * |
656 | * The firmware blob can contain optional ELF sections: .resource_table section | |
657 | * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping | |
658 | * description, which needs to be setup before powering on the PRU core. To | |
659 | * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the | |
660 | * firmware linker) and therefore is not loaded to PRU memory. | |
d4ce2de7 SA |
661 | */ |
662 | static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) | |
663 | { | |
c75c9fda GJ |
664 | struct device *dev = &rproc->dev; |
665 | struct pru_rproc *pru = rproc->priv; | |
666 | const u8 *elf_data = fw->data; | |
667 | const void *shdr; | |
668 | u8 class = fw_elf_get_class(fw); | |
669 | u64 sh_offset; | |
d4ce2de7 SA |
670 | int ret; |
671 | ||
672 | /* load optional rsc table */ | |
673 | ret = rproc_elf_load_rsc_table(rproc, fw); | |
674 | if (ret == -EINVAL) | |
675 | dev_dbg(&rproc->dev, "no resource table found for this fw\n"); | |
676 | else if (ret) | |
677 | return ret; | |
678 | ||
c75c9fda GJ |
679 | /* find .pru_interrupt_map section, not having it is not an error */ |
680 | shdr = pru_rproc_find_interrupt_map(dev, fw); | |
681 | if (IS_ERR(shdr)) | |
682 | return PTR_ERR(shdr); | |
683 | ||
684 | if (!shdr) | |
685 | return 0; | |
686 | ||
687 | /* preserve pointer to PRU interrupt map together with it size */ | |
688 | sh_offset = elf_shdr_get_sh_offset(class, shdr); | |
689 | pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset); | |
690 | pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr); | |
691 | ||
d4ce2de7 SA |
692 | return 0; |
693 | } | |
694 | ||
695 | /* | |
696 | * Compute PRU id based on the IRAM addresses. The PRU IRAMs are | |
697 | * always at a particular offset within the PRUSS address space. | |
698 | */ | |
699 | static int pru_rproc_set_id(struct pru_rproc *pru) | |
700 | { | |
701 | int ret = 0; | |
702 | ||
703 | switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { | |
1d39f4d1 SA |
704 | case TX_PRU0_IRAM_ADDR_MASK: |
705 | fallthrough; | |
706 | case RTU0_IRAM_ADDR_MASK: | |
707 | fallthrough; | |
d4ce2de7 SA |
708 | case PRU0_IRAM_ADDR_MASK: |
709 | pru->id = 0; | |
710 | break; | |
1d39f4d1 SA |
711 | case TX_PRU1_IRAM_ADDR_MASK: |
712 | fallthrough; | |
713 | case RTU1_IRAM_ADDR_MASK: | |
714 | fallthrough; | |
d4ce2de7 SA |
715 | case PRU1_IRAM_ADDR_MASK: |
716 | pru->id = 1; | |
717 | break; | |
718 | default: | |
719 | ret = -EINVAL; | |
720 | } | |
721 | ||
722 | return ret; | |
723 | } | |
724 | ||
725 | static int pru_rproc_probe(struct platform_device *pdev) | |
726 | { | |
727 | struct device *dev = &pdev->dev; | |
728 | struct device_node *np = dev->of_node; | |
729 | struct platform_device *ppdev = to_platform_device(dev->parent); | |
730 | struct pru_rproc *pru; | |
731 | const char *fw_name; | |
732 | struct rproc *rproc = NULL; | |
733 | struct resource *res; | |
734 | int i, ret; | |
1d39f4d1 | 735 | const struct pru_private_data *data; |
d4ce2de7 SA |
736 | const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; |
737 | ||
1d39f4d1 SA |
738 | data = of_device_get_match_data(&pdev->dev); |
739 | if (!data) | |
740 | return -ENODEV; | |
741 | ||
d4ce2de7 SA |
742 | ret = of_property_read_string(np, "firmware-name", &fw_name); |
743 | if (ret) { | |
744 | dev_err(dev, "unable to retrieve firmware-name %d\n", ret); | |
745 | return ret; | |
746 | } | |
747 | ||
748 | rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name, | |
749 | sizeof(*pru)); | |
750 | if (!rproc) { | |
751 | dev_err(dev, "rproc_alloc failed\n"); | |
752 | return -ENOMEM; | |
753 | } | |
754 | /* use a custom load function to deal with PRU-specific quirks */ | |
755 | rproc->ops->load = pru_rproc_load_elf_segments; | |
756 | ||
757 | /* use a custom parse function to deal with PRU-specific resources */ | |
758 | rproc->ops->parse_fw = pru_rproc_parse_fw; | |
759 | ||
760 | /* error recovery is not supported for PRUs */ | |
761 | rproc->recovery_disabled = true; | |
762 | ||
763 | /* | |
764 | * rproc_add will auto-boot the processor normally, but this is not | |
765 | * desired with PRU client driven boot-flow methodology. A PRU | |
766 | * application/client driver will boot the corresponding PRU | |
767 | * remote-processor as part of its state machine either through the | |
768 | * remoteproc sysfs interface or through the equivalent kernel API. | |
769 | */ | |
770 | rproc->auto_boot = false; | |
771 | ||
772 | pru = rproc->priv; | |
773 | pru->dev = dev; | |
1d39f4d1 | 774 | pru->data = data; |
d4ce2de7 SA |
775 | pru->pruss = platform_get_drvdata(ppdev); |
776 | pru->rproc = rproc; | |
777 | pru->fw_name = fw_name; | |
778 | ||
779 | for (i = 0; i < ARRAY_SIZE(mem_names); i++) { | |
780 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
781 | mem_names[i]); | |
782 | pru->mem_regions[i].va = devm_ioremap_resource(dev, res); | |
783 | if (IS_ERR(pru->mem_regions[i].va)) { | |
784 | dev_err(dev, "failed to parse and map memory resource %d %s\n", | |
785 | i, mem_names[i]); | |
786 | ret = PTR_ERR(pru->mem_regions[i].va); | |
787 | return ret; | |
788 | } | |
789 | pru->mem_regions[i].pa = res->start; | |
790 | pru->mem_regions[i].size = resource_size(res); | |
791 | ||
792 | dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n", | |
793 | mem_names[i], &pru->mem_regions[i].pa, | |
794 | pru->mem_regions[i].size, pru->mem_regions[i].va); | |
795 | } | |
796 | ||
797 | ret = pru_rproc_set_id(pru); | |
798 | if (ret < 0) | |
799 | return ret; | |
800 | ||
801 | platform_set_drvdata(pdev, rproc); | |
802 | ||
803 | ret = devm_rproc_add(dev, pru->rproc); | |
804 | if (ret) { | |
805 | dev_err(dev, "rproc_add failed: %d\n", ret); | |
806 | return ret; | |
807 | } | |
808 | ||
20ad1de0 SA |
809 | pru_rproc_create_debug_entries(rproc); |
810 | ||
d4ce2de7 SA |
811 | dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | static int pru_rproc_remove(struct platform_device *pdev) | |
817 | { | |
818 | struct device *dev = &pdev->dev; | |
819 | struct rproc *rproc = platform_get_drvdata(pdev); | |
820 | ||
821 | dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
1d39f4d1 SA |
826 | static const struct pru_private_data pru_data = { |
827 | .type = PRU_TYPE_PRU, | |
828 | }; | |
829 | ||
830 | static const struct pru_private_data k3_pru_data = { | |
831 | .type = PRU_TYPE_PRU, | |
832 | .is_k3 = 1, | |
833 | }; | |
834 | ||
835 | static const struct pru_private_data k3_rtu_data = { | |
836 | .type = PRU_TYPE_RTU, | |
837 | .is_k3 = 1, | |
838 | }; | |
839 | ||
840 | static const struct pru_private_data k3_tx_pru_data = { | |
841 | .type = PRU_TYPE_TX_PRU, | |
842 | .is_k3 = 1, | |
843 | }; | |
844 | ||
d4ce2de7 | 845 | static const struct of_device_id pru_rproc_match[] = { |
1d39f4d1 SA |
846 | { .compatible = "ti,am3356-pru", .data = &pru_data }, |
847 | { .compatible = "ti,am4376-pru", .data = &pru_data }, | |
848 | { .compatible = "ti,am5728-pru", .data = &pru_data }, | |
849 | { .compatible = "ti,k2g-pru", .data = &pru_data }, | |
850 | { .compatible = "ti,am654-pru", .data = &k3_pru_data }, | |
851 | { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, | |
852 | { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, | |
b44786c9 SA |
853 | { .compatible = "ti,j721e-pru", .data = &k3_pru_data }, |
854 | { .compatible = "ti,j721e-rtu", .data = &k3_rtu_data }, | |
855 | { .compatible = "ti,j721e-tx-pru", .data = &k3_tx_pru_data }, | |
d4ce2de7 SA |
856 | {}, |
857 | }; | |
858 | MODULE_DEVICE_TABLE(of, pru_rproc_match); | |
859 | ||
860 | static struct platform_driver pru_rproc_driver = { | |
861 | .driver = { | |
862 | .name = "pru-rproc", | |
863 | .of_match_table = pru_rproc_match, | |
864 | .suppress_bind_attrs = true, | |
865 | }, | |
866 | .probe = pru_rproc_probe, | |
867 | .remove = pru_rproc_remove, | |
868 | }; | |
869 | module_platform_driver(pru_rproc_driver); | |
870 | ||
871 | MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); | |
872 | MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); | |
873 | MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>"); | |
874 | MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver"); | |
875 | MODULE_LICENSE("GPL v2"); |