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d4ce2de7 SA |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * PRU-ICSS remoteproc driver for various TI SoCs | |
4 | * | |
5 | * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ | |
6 | * | |
7 | * Author(s): | |
8 | * Suman Anna <s-anna@ti.com> | |
9 | * Andrew F. Davis <afd@ti.com> | |
10 | * Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments | |
11 | */ | |
12 | ||
13 | #include <linux/bitops.h> | |
20ad1de0 | 14 | #include <linux/debugfs.h> |
c75c9fda | 15 | #include <linux/irqdomain.h> |
d4ce2de7 SA |
16 | #include <linux/module.h> |
17 | #include <linux/of_device.h> | |
c75c9fda | 18 | #include <linux/of_irq.h> |
d4ce2de7 SA |
19 | #include <linux/pruss_driver.h> |
20 | #include <linux/remoteproc.h> | |
21 | ||
22 | #include "remoteproc_internal.h" | |
23 | #include "remoteproc_elf_helpers.h" | |
c75c9fda | 24 | #include "pru_rproc.h" |
d4ce2de7 SA |
25 | |
26 | /* PRU_ICSS_PRU_CTRL registers */ | |
27 | #define PRU_CTRL_CTRL 0x0000 | |
28 | #define PRU_CTRL_STS 0x0004 | |
20ad1de0 SA |
29 | #define PRU_CTRL_WAKEUP_EN 0x0008 |
30 | #define PRU_CTRL_CYCLE 0x000C | |
31 | #define PRU_CTRL_STALL 0x0010 | |
32 | #define PRU_CTRL_CTBIR0 0x0020 | |
33 | #define PRU_CTRL_CTBIR1 0x0024 | |
34 | #define PRU_CTRL_CTPPR0 0x0028 | |
35 | #define PRU_CTRL_CTPPR1 0x002C | |
d4ce2de7 SA |
36 | |
37 | /* CTRL register bit-fields */ | |
38 | #define CTRL_CTRL_SOFT_RST_N BIT(0) | |
39 | #define CTRL_CTRL_EN BIT(1) | |
40 | #define CTRL_CTRL_SLEEPING BIT(2) | |
41 | #define CTRL_CTRL_CTR_EN BIT(3) | |
42 | #define CTRL_CTRL_SINGLE_STEP BIT(8) | |
43 | #define CTRL_CTRL_RUNSTATE BIT(15) | |
44 | ||
20ad1de0 SA |
45 | /* PRU_ICSS_PRU_DEBUG registers */ |
46 | #define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) | |
47 | #define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) | |
48 | ||
d4ce2de7 SA |
49 | /* PRU Core IRAM address masks */ |
50 | #define PRU_IRAM_ADDR_MASK 0x3ffff | |
51 | #define PRU0_IRAM_ADDR_MASK 0x34000 | |
52 | #define PRU1_IRAM_ADDR_MASK 0x38000 | |
53 | ||
54 | /* PRU device addresses for various type of PRU RAMs */ | |
55 | #define PRU_IRAM_DA 0 /* Instruction RAM */ | |
56 | #define PRU_PDRAM_DA 0 /* Primary Data RAM */ | |
57 | #define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ | |
58 | #define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ | |
59 | ||
c75c9fda GJ |
60 | #define MAX_PRU_SYS_EVENTS 160 |
61 | ||
d4ce2de7 SA |
62 | /** |
63 | * enum pru_iomem - PRU core memory/register range identifiers | |
64 | * | |
65 | * @PRU_IOMEM_IRAM: PRU Instruction RAM range | |
66 | * @PRU_IOMEM_CTRL: PRU Control register range | |
67 | * @PRU_IOMEM_DEBUG: PRU Debug register range | |
68 | * @PRU_IOMEM_MAX: just keep this one at the end | |
69 | */ | |
70 | enum pru_iomem { | |
71 | PRU_IOMEM_IRAM = 0, | |
72 | PRU_IOMEM_CTRL, | |
73 | PRU_IOMEM_DEBUG, | |
74 | PRU_IOMEM_MAX, | |
75 | }; | |
76 | ||
77 | /** | |
78 | * struct pru_rproc - PRU remoteproc structure | |
79 | * @id: id of the PRU core within the PRUSS | |
80 | * @dev: PRU core device pointer | |
81 | * @pruss: back-reference to parent PRUSS structure | |
82 | * @rproc: remoteproc pointer for this PRU core | |
83 | * @mem_regions: data for each of the PRU memory regions | |
84 | * @fw_name: name of firmware image used during loading | |
c75c9fda GJ |
85 | * @mapped_irq: virtual interrupt numbers of created fw specific mapping |
86 | * @pru_interrupt_map: pointer to interrupt mapping description (firmware) | |
87 | * @pru_interrupt_map_sz: pru_interrupt_map size | |
20ad1de0 SA |
88 | * @dbg_single_step: debug state variable to set PRU into single step mode |
89 | * @dbg_continuous: debug state variable to restore PRU execution mode | |
c75c9fda | 90 | * @evt_count: number of mapped events |
d4ce2de7 SA |
91 | */ |
92 | struct pru_rproc { | |
93 | int id; | |
94 | struct device *dev; | |
95 | struct pruss *pruss; | |
96 | struct rproc *rproc; | |
97 | struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; | |
98 | const char *fw_name; | |
c75c9fda GJ |
99 | unsigned int *mapped_irq; |
100 | struct pru_irq_rsc *pru_interrupt_map; | |
101 | size_t pru_interrupt_map_sz; | |
20ad1de0 SA |
102 | u32 dbg_single_step; |
103 | u32 dbg_continuous; | |
c75c9fda | 104 | u8 evt_count; |
d4ce2de7 SA |
105 | }; |
106 | ||
107 | static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) | |
108 | { | |
109 | return readl_relaxed(pru->mem_regions[PRU_IOMEM_CTRL].va + reg); | |
110 | } | |
111 | ||
112 | static inline | |
113 | void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) | |
114 | { | |
115 | writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); | |
116 | } | |
117 | ||
20ad1de0 SA |
118 | static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg) |
119 | { | |
120 | return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg); | |
121 | } | |
122 | ||
123 | static int regs_show(struct seq_file *s, void *data) | |
124 | { | |
125 | struct rproc *rproc = s->private; | |
126 | struct pru_rproc *pru = rproc->priv; | |
127 | int i, nregs = 32; | |
128 | u32 pru_sts; | |
129 | int pru_is_running; | |
130 | ||
131 | seq_puts(s, "============== Control Registers ==============\n"); | |
132 | seq_printf(s, "CTRL := 0x%08x\n", | |
133 | pru_control_read_reg(pru, PRU_CTRL_CTRL)); | |
134 | pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS); | |
135 | seq_printf(s, "STS (PC) := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2); | |
136 | seq_printf(s, "WAKEUP_EN := 0x%08x\n", | |
137 | pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN)); | |
138 | seq_printf(s, "CYCLE := 0x%08x\n", | |
139 | pru_control_read_reg(pru, PRU_CTRL_CYCLE)); | |
140 | seq_printf(s, "STALL := 0x%08x\n", | |
141 | pru_control_read_reg(pru, PRU_CTRL_STALL)); | |
142 | seq_printf(s, "CTBIR0 := 0x%08x\n", | |
143 | pru_control_read_reg(pru, PRU_CTRL_CTBIR0)); | |
144 | seq_printf(s, "CTBIR1 := 0x%08x\n", | |
145 | pru_control_read_reg(pru, PRU_CTRL_CTBIR1)); | |
146 | seq_printf(s, "CTPPR0 := 0x%08x\n", | |
147 | pru_control_read_reg(pru, PRU_CTRL_CTPPR0)); | |
148 | seq_printf(s, "CTPPR1 := 0x%08x\n", | |
149 | pru_control_read_reg(pru, PRU_CTRL_CTPPR1)); | |
150 | ||
151 | seq_puts(s, "=============== Debug Registers ===============\n"); | |
152 | pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) & | |
153 | CTRL_CTRL_RUNSTATE; | |
154 | if (pru_is_running) { | |
155 | seq_puts(s, "PRU is executing, cannot print/access debug registers.\n"); | |
156 | return 0; | |
157 | } | |
158 | ||
159 | for (i = 0; i < nregs; i++) { | |
160 | seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n", | |
161 | i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)), | |
162 | i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i))); | |
163 | } | |
164 | ||
165 | return 0; | |
166 | } | |
167 | DEFINE_SHOW_ATTRIBUTE(regs); | |
168 | ||
169 | /* | |
170 | * Control PRU single-step mode | |
171 | * | |
172 | * This is a debug helper function used for controlling the single-step | |
173 | * mode of the PRU. The PRU Debug registers are not accessible when the | |
174 | * PRU is in RUNNING state. | |
175 | * | |
176 | * Writing a non-zero value sets the PRU into single-step mode irrespective | |
177 | * of its previous state. The PRU mode is saved only on the first set into | |
178 | * a single-step mode. Writing a zero value will restore the PRU into its | |
179 | * original mode. | |
180 | */ | |
181 | static int pru_rproc_debug_ss_set(void *data, u64 val) | |
182 | { | |
183 | struct rproc *rproc = data; | |
184 | struct pru_rproc *pru = rproc->priv; | |
185 | u32 reg_val; | |
186 | ||
187 | val = val ? 1 : 0; | |
188 | if (!val && !pru->dbg_single_step) | |
189 | return 0; | |
190 | ||
191 | reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL); | |
192 | ||
193 | if (val && !pru->dbg_single_step) | |
194 | pru->dbg_continuous = reg_val; | |
195 | ||
196 | if (val) | |
197 | reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN; | |
198 | else | |
199 | reg_val = pru->dbg_continuous; | |
200 | ||
201 | pru->dbg_single_step = val; | |
202 | pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val); | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static int pru_rproc_debug_ss_get(void *data, u64 *val) | |
208 | { | |
209 | struct rproc *rproc = data; | |
210 | struct pru_rproc *pru = rproc->priv; | |
211 | ||
212 | *val = pru->dbg_single_step; | |
213 | ||
214 | return 0; | |
215 | } | |
216 | DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get, | |
217 | pru_rproc_debug_ss_set, "%llu\n"); | |
218 | ||
219 | /* | |
220 | * Create PRU-specific debugfs entries | |
221 | * | |
222 | * The entries are created only if the parent remoteproc debugfs directory | |
223 | * exists, and will be cleaned up by the remoteproc core. | |
224 | */ | |
225 | static void pru_rproc_create_debug_entries(struct rproc *rproc) | |
226 | { | |
227 | if (!rproc->dbg_dir) | |
228 | return; | |
229 | ||
230 | debugfs_create_file("regs", 0400, rproc->dbg_dir, | |
231 | rproc, ®s_fops); | |
232 | debugfs_create_file("single_step", 0600, rproc->dbg_dir, | |
233 | rproc, &pru_rproc_debug_ss_fops); | |
234 | } | |
235 | ||
c75c9fda GJ |
236 | static void pru_dispose_irq_mapping(struct pru_rproc *pru) |
237 | { | |
238 | while (pru->evt_count--) { | |
239 | if (pru->mapped_irq[pru->evt_count] > 0) | |
240 | irq_dispose_mapping(pru->mapped_irq[pru->evt_count]); | |
241 | } | |
242 | ||
243 | kfree(pru->mapped_irq); | |
244 | } | |
245 | ||
246 | /* | |
247 | * Parse the custom PRU interrupt map resource and configure the INTC | |
248 | * appropriately. | |
249 | */ | |
250 | static int pru_handle_intrmap(struct rproc *rproc) | |
251 | { | |
252 | struct device *dev = rproc->dev.parent; | |
253 | struct pru_rproc *pru = rproc->priv; | |
254 | struct pru_irq_rsc *rsc = pru->pru_interrupt_map; | |
255 | struct irq_fwspec fwspec; | |
256 | struct device_node *irq_parent; | |
257 | int i, ret = 0; | |
258 | ||
259 | /* not having pru_interrupt_map is not an error */ | |
260 | if (!rsc) | |
261 | return 0; | |
262 | ||
263 | /* currently supporting only type 0 */ | |
264 | if (rsc->type != 0) { | |
265 | dev_err(dev, "unsupported rsc type: %d\n", rsc->type); | |
266 | return -EINVAL; | |
267 | } | |
268 | ||
269 | if (rsc->num_evts > MAX_PRU_SYS_EVENTS) | |
270 | return -EINVAL; | |
271 | ||
272 | if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) != | |
273 | pru->pru_interrupt_map_sz) | |
274 | return -EINVAL; | |
275 | ||
276 | pru->evt_count = rsc->num_evts; | |
277 | pru->mapped_irq = kcalloc(pru->evt_count, sizeof(unsigned int), | |
278 | GFP_KERNEL); | |
279 | if (!pru->mapped_irq) | |
280 | return -ENOMEM; | |
281 | ||
282 | /* | |
283 | * parse and fill in system event to interrupt channel and | |
284 | * channel-to-host mapping | |
285 | */ | |
286 | irq_parent = of_irq_find_parent(pru->dev->of_node); | |
287 | if (!irq_parent) { | |
288 | kfree(pru->mapped_irq); | |
289 | return -ENODEV; | |
290 | } | |
291 | ||
292 | fwspec.fwnode = of_node_to_fwnode(irq_parent); | |
293 | fwspec.param_count = 3; | |
294 | for (i = 0; i < pru->evt_count; i++) { | |
295 | fwspec.param[0] = rsc->pru_intc_map[i].event; | |
296 | fwspec.param[1] = rsc->pru_intc_map[i].chnl; | |
297 | fwspec.param[2] = rsc->pru_intc_map[i].host; | |
298 | ||
299 | dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", | |
300 | i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); | |
301 | ||
302 | pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec); | |
303 | if (!pru->mapped_irq[i]) { | |
304 | dev_err(dev, "failed to get virq\n"); | |
305 | ret = pru->mapped_irq[i]; | |
306 | goto map_fail; | |
307 | } | |
308 | } | |
309 | ||
310 | return ret; | |
311 | ||
312 | map_fail: | |
313 | pru_dispose_irq_mapping(pru); | |
314 | ||
315 | return ret; | |
316 | } | |
317 | ||
d4ce2de7 SA |
318 | static int pru_rproc_start(struct rproc *rproc) |
319 | { | |
320 | struct device *dev = &rproc->dev; | |
321 | struct pru_rproc *pru = rproc->priv; | |
322 | u32 val; | |
c75c9fda | 323 | int ret; |
d4ce2de7 SA |
324 | |
325 | dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", | |
326 | pru->id, (rproc->bootaddr >> 2)); | |
327 | ||
c75c9fda GJ |
328 | ret = pru_handle_intrmap(rproc); |
329 | /* | |
330 | * reset references to pru interrupt map - they will stop being valid | |
331 | * after rproc_start returns | |
332 | */ | |
333 | pru->pru_interrupt_map = NULL; | |
334 | pru->pru_interrupt_map_sz = 0; | |
335 | if (ret) | |
336 | return ret; | |
337 | ||
d4ce2de7 SA |
338 | val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); |
339 | pru_control_write_reg(pru, PRU_CTRL_CTRL, val); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | static int pru_rproc_stop(struct rproc *rproc) | |
345 | { | |
346 | struct device *dev = &rproc->dev; | |
347 | struct pru_rproc *pru = rproc->priv; | |
348 | u32 val; | |
349 | ||
350 | dev_dbg(dev, "stopping PRU%d\n", pru->id); | |
351 | ||
352 | val = pru_control_read_reg(pru, PRU_CTRL_CTRL); | |
353 | val &= ~CTRL_CTRL_EN; | |
354 | pru_control_write_reg(pru, PRU_CTRL_CTRL, val); | |
355 | ||
c75c9fda GJ |
356 | /* dispose irq mapping - new firmware can provide new mapping */ |
357 | if (pru->mapped_irq) | |
358 | pru_dispose_irq_mapping(pru); | |
359 | ||
d4ce2de7 SA |
360 | return 0; |
361 | } | |
362 | ||
363 | /* | |
364 | * Convert PRU device address (data spaces only) to kernel virtual address. | |
365 | * | |
366 | * Each PRU has access to all data memories within the PRUSS, accessible at | |
367 | * different ranges. So, look through both its primary and secondary Data | |
368 | * RAMs as well as any shared Data RAM to convert a PRU device address to | |
369 | * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data | |
370 | * RAM1 is primary Data RAM for PRU1. | |
371 | */ | |
372 | static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len) | |
373 | { | |
374 | struct pruss_mem_region dram0, dram1, shrd_ram; | |
375 | struct pruss *pruss = pru->pruss; | |
376 | u32 offset; | |
377 | void *va = NULL; | |
378 | ||
379 | if (len == 0) | |
380 | return NULL; | |
381 | ||
382 | dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0]; | |
383 | dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1]; | |
384 | /* PRU1 has its local RAM addresses reversed */ | |
385 | if (pru->id == 1) | |
386 | swap(dram0, dram1); | |
387 | shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2]; | |
388 | ||
389 | if (da >= PRU_PDRAM_DA && da + len <= PRU_PDRAM_DA + dram0.size) { | |
390 | offset = da - PRU_PDRAM_DA; | |
391 | va = (__force void *)(dram0.va + offset); | |
392 | } else if (da >= PRU_SDRAM_DA && | |
393 | da + len <= PRU_SDRAM_DA + dram1.size) { | |
394 | offset = da - PRU_SDRAM_DA; | |
395 | va = (__force void *)(dram1.va + offset); | |
396 | } else if (da >= PRU_SHRDRAM_DA && | |
397 | da + len <= PRU_SHRDRAM_DA + shrd_ram.size) { | |
398 | offset = da - PRU_SHRDRAM_DA; | |
399 | va = (__force void *)(shrd_ram.va + offset); | |
400 | } | |
401 | ||
402 | return va; | |
403 | } | |
404 | ||
405 | /* | |
406 | * Convert PRU device address (instruction space) to kernel virtual address. | |
407 | * | |
408 | * A PRU does not have an unified address space. Each PRU has its very own | |
409 | * private Instruction RAM, and its device address is identical to that of | |
410 | * its primary Data RAM device address. | |
411 | */ | |
412 | static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len) | |
413 | { | |
414 | u32 offset; | |
415 | void *va = NULL; | |
416 | ||
417 | if (len == 0) | |
418 | return NULL; | |
419 | ||
420 | if (da >= PRU_IRAM_DA && | |
421 | da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) { | |
422 | offset = da - PRU_IRAM_DA; | |
423 | va = (__force void *)(pru->mem_regions[PRU_IOMEM_IRAM].va + | |
424 | offset); | |
425 | } | |
426 | ||
427 | return va; | |
428 | } | |
429 | ||
430 | /* | |
431 | * Provide address translations for only PRU Data RAMs through the remoteproc | |
432 | * core for any PRU client drivers. The PRU Instruction RAM access is restricted | |
433 | * only to the PRU loader code. | |
434 | */ | |
435 | static void *pru_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) | |
436 | { | |
437 | struct pru_rproc *pru = rproc->priv; | |
438 | ||
439 | return pru_d_da_to_va(pru, da, len); | |
440 | } | |
441 | ||
442 | /* PRU-specific address translator used by PRU loader. */ | |
443 | static void *pru_da_to_va(struct rproc *rproc, u64 da, size_t len, bool is_iram) | |
444 | { | |
445 | struct pru_rproc *pru = rproc->priv; | |
446 | void *va; | |
447 | ||
448 | if (is_iram) | |
449 | va = pru_i_da_to_va(pru, da, len); | |
450 | else | |
451 | va = pru_d_da_to_va(pru, da, len); | |
452 | ||
453 | return va; | |
454 | } | |
455 | ||
456 | static struct rproc_ops pru_rproc_ops = { | |
457 | .start = pru_rproc_start, | |
458 | .stop = pru_rproc_stop, | |
459 | .da_to_va = pru_rproc_da_to_va, | |
460 | }; | |
461 | ||
462 | static int | |
463 | pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) | |
464 | { | |
465 | struct device *dev = &rproc->dev; | |
466 | struct elf32_hdr *ehdr; | |
467 | struct elf32_phdr *phdr; | |
468 | int i, ret = 0; | |
469 | const u8 *elf_data = fw->data; | |
470 | ||
471 | ehdr = (struct elf32_hdr *)elf_data; | |
472 | phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff); | |
473 | ||
474 | /* go through the available ELF segments */ | |
475 | for (i = 0; i < ehdr->e_phnum; i++, phdr++) { | |
476 | u32 da = phdr->p_paddr; | |
477 | u32 memsz = phdr->p_memsz; | |
478 | u32 filesz = phdr->p_filesz; | |
479 | u32 offset = phdr->p_offset; | |
480 | bool is_iram; | |
481 | void *ptr; | |
482 | ||
483 | if (phdr->p_type != PT_LOAD || !filesz) | |
484 | continue; | |
485 | ||
486 | dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", | |
487 | phdr->p_type, da, memsz, filesz); | |
488 | ||
489 | if (filesz > memsz) { | |
490 | dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n", | |
491 | filesz, memsz); | |
492 | ret = -EINVAL; | |
493 | break; | |
494 | } | |
495 | ||
496 | if (offset + filesz > fw->size) { | |
497 | dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n", | |
498 | offset + filesz, fw->size); | |
499 | ret = -EINVAL; | |
500 | break; | |
501 | } | |
502 | ||
503 | /* grab the kernel address for this device address */ | |
504 | is_iram = phdr->p_flags & PF_X; | |
505 | ptr = pru_da_to_va(rproc, da, memsz, is_iram); | |
506 | if (!ptr) { | |
507 | dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); | |
508 | ret = -EINVAL; | |
509 | break; | |
510 | } | |
511 | ||
512 | memcpy(ptr, elf_data + phdr->p_offset, filesz); | |
513 | ||
514 | /* skip the memzero logic performed by remoteproc ELF loader */ | |
515 | } | |
516 | ||
517 | return ret; | |
518 | } | |
519 | ||
c75c9fda GJ |
520 | static const void * |
521 | pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw) | |
522 | { | |
523 | struct elf32_shdr *shdr, *name_table_shdr; | |
524 | const char *name_table; | |
525 | const u8 *elf_data = fw->data; | |
526 | struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data; | |
527 | u16 shnum = ehdr->e_shnum; | |
528 | u16 shstrndx = ehdr->e_shstrndx; | |
529 | int i; | |
530 | ||
531 | /* first, get the section header */ | |
532 | shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff); | |
533 | /* compute name table section header entry in shdr array */ | |
534 | name_table_shdr = shdr + shstrndx; | |
535 | /* finally, compute the name table section address in elf */ | |
536 | name_table = elf_data + name_table_shdr->sh_offset; | |
537 | ||
538 | for (i = 0; i < shnum; i++, shdr++) { | |
539 | u32 size = shdr->sh_size; | |
540 | u32 offset = shdr->sh_offset; | |
541 | u32 name = shdr->sh_name; | |
542 | ||
543 | if (strcmp(name_table + name, ".pru_irq_map")) | |
544 | continue; | |
545 | ||
546 | /* make sure we have the entire irq map */ | |
547 | if (offset + size > fw->size || offset + size < size) { | |
548 | dev_err(dev, ".pru_irq_map section truncated\n"); | |
549 | return ERR_PTR(-EINVAL); | |
550 | } | |
551 | ||
552 | /* make sure irq map has at least the header */ | |
553 | if (sizeof(struct pru_irq_rsc) > size) { | |
554 | dev_err(dev, "header-less .pru_irq_map section\n"); | |
555 | return ERR_PTR(-EINVAL); | |
556 | } | |
557 | ||
558 | return shdr; | |
559 | } | |
560 | ||
561 | dev_dbg(dev, "no .pru_irq_map section found for this fw\n"); | |
562 | ||
563 | return NULL; | |
564 | } | |
565 | ||
d4ce2de7 SA |
566 | /* |
567 | * Use a custom parse_fw callback function for dealing with PRU firmware | |
568 | * specific sections. | |
c75c9fda GJ |
569 | * |
570 | * The firmware blob can contain optional ELF sections: .resource_table section | |
571 | * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping | |
572 | * description, which needs to be setup before powering on the PRU core. To | |
573 | * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the | |
574 | * firmware linker) and therefore is not loaded to PRU memory. | |
d4ce2de7 SA |
575 | */ |
576 | static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) | |
577 | { | |
c75c9fda GJ |
578 | struct device *dev = &rproc->dev; |
579 | struct pru_rproc *pru = rproc->priv; | |
580 | const u8 *elf_data = fw->data; | |
581 | const void *shdr; | |
582 | u8 class = fw_elf_get_class(fw); | |
583 | u64 sh_offset; | |
d4ce2de7 SA |
584 | int ret; |
585 | ||
586 | /* load optional rsc table */ | |
587 | ret = rproc_elf_load_rsc_table(rproc, fw); | |
588 | if (ret == -EINVAL) | |
589 | dev_dbg(&rproc->dev, "no resource table found for this fw\n"); | |
590 | else if (ret) | |
591 | return ret; | |
592 | ||
c75c9fda GJ |
593 | /* find .pru_interrupt_map section, not having it is not an error */ |
594 | shdr = pru_rproc_find_interrupt_map(dev, fw); | |
595 | if (IS_ERR(shdr)) | |
596 | return PTR_ERR(shdr); | |
597 | ||
598 | if (!shdr) | |
599 | return 0; | |
600 | ||
601 | /* preserve pointer to PRU interrupt map together with it size */ | |
602 | sh_offset = elf_shdr_get_sh_offset(class, shdr); | |
603 | pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset); | |
604 | pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr); | |
605 | ||
d4ce2de7 SA |
606 | return 0; |
607 | } | |
608 | ||
609 | /* | |
610 | * Compute PRU id based on the IRAM addresses. The PRU IRAMs are | |
611 | * always at a particular offset within the PRUSS address space. | |
612 | */ | |
613 | static int pru_rproc_set_id(struct pru_rproc *pru) | |
614 | { | |
615 | int ret = 0; | |
616 | ||
617 | switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { | |
618 | case PRU0_IRAM_ADDR_MASK: | |
619 | pru->id = 0; | |
620 | break; | |
621 | case PRU1_IRAM_ADDR_MASK: | |
622 | pru->id = 1; | |
623 | break; | |
624 | default: | |
625 | ret = -EINVAL; | |
626 | } | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
631 | static int pru_rproc_probe(struct platform_device *pdev) | |
632 | { | |
633 | struct device *dev = &pdev->dev; | |
634 | struct device_node *np = dev->of_node; | |
635 | struct platform_device *ppdev = to_platform_device(dev->parent); | |
636 | struct pru_rproc *pru; | |
637 | const char *fw_name; | |
638 | struct rproc *rproc = NULL; | |
639 | struct resource *res; | |
640 | int i, ret; | |
641 | const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; | |
642 | ||
643 | ret = of_property_read_string(np, "firmware-name", &fw_name); | |
644 | if (ret) { | |
645 | dev_err(dev, "unable to retrieve firmware-name %d\n", ret); | |
646 | return ret; | |
647 | } | |
648 | ||
649 | rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name, | |
650 | sizeof(*pru)); | |
651 | if (!rproc) { | |
652 | dev_err(dev, "rproc_alloc failed\n"); | |
653 | return -ENOMEM; | |
654 | } | |
655 | /* use a custom load function to deal with PRU-specific quirks */ | |
656 | rproc->ops->load = pru_rproc_load_elf_segments; | |
657 | ||
658 | /* use a custom parse function to deal with PRU-specific resources */ | |
659 | rproc->ops->parse_fw = pru_rproc_parse_fw; | |
660 | ||
661 | /* error recovery is not supported for PRUs */ | |
662 | rproc->recovery_disabled = true; | |
663 | ||
664 | /* | |
665 | * rproc_add will auto-boot the processor normally, but this is not | |
666 | * desired with PRU client driven boot-flow methodology. A PRU | |
667 | * application/client driver will boot the corresponding PRU | |
668 | * remote-processor as part of its state machine either through the | |
669 | * remoteproc sysfs interface or through the equivalent kernel API. | |
670 | */ | |
671 | rproc->auto_boot = false; | |
672 | ||
673 | pru = rproc->priv; | |
674 | pru->dev = dev; | |
675 | pru->pruss = platform_get_drvdata(ppdev); | |
676 | pru->rproc = rproc; | |
677 | pru->fw_name = fw_name; | |
678 | ||
679 | for (i = 0; i < ARRAY_SIZE(mem_names); i++) { | |
680 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
681 | mem_names[i]); | |
682 | pru->mem_regions[i].va = devm_ioremap_resource(dev, res); | |
683 | if (IS_ERR(pru->mem_regions[i].va)) { | |
684 | dev_err(dev, "failed to parse and map memory resource %d %s\n", | |
685 | i, mem_names[i]); | |
686 | ret = PTR_ERR(pru->mem_regions[i].va); | |
687 | return ret; | |
688 | } | |
689 | pru->mem_regions[i].pa = res->start; | |
690 | pru->mem_regions[i].size = resource_size(res); | |
691 | ||
692 | dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n", | |
693 | mem_names[i], &pru->mem_regions[i].pa, | |
694 | pru->mem_regions[i].size, pru->mem_regions[i].va); | |
695 | } | |
696 | ||
697 | ret = pru_rproc_set_id(pru); | |
698 | if (ret < 0) | |
699 | return ret; | |
700 | ||
701 | platform_set_drvdata(pdev, rproc); | |
702 | ||
703 | ret = devm_rproc_add(dev, pru->rproc); | |
704 | if (ret) { | |
705 | dev_err(dev, "rproc_add failed: %d\n", ret); | |
706 | return ret; | |
707 | } | |
708 | ||
20ad1de0 SA |
709 | pru_rproc_create_debug_entries(rproc); |
710 | ||
d4ce2de7 SA |
711 | dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int pru_rproc_remove(struct platform_device *pdev) | |
717 | { | |
718 | struct device *dev = &pdev->dev; | |
719 | struct rproc *rproc = platform_get_drvdata(pdev); | |
720 | ||
721 | dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
726 | static const struct of_device_id pru_rproc_match[] = { | |
727 | { .compatible = "ti,am3356-pru", }, | |
728 | { .compatible = "ti,am4376-pru", }, | |
729 | { .compatible = "ti,am5728-pru", }, | |
730 | { .compatible = "ti,k2g-pru", }, | |
731 | {}, | |
732 | }; | |
733 | MODULE_DEVICE_TABLE(of, pru_rproc_match); | |
734 | ||
735 | static struct platform_driver pru_rproc_driver = { | |
736 | .driver = { | |
737 | .name = "pru-rproc", | |
738 | .of_match_table = pru_rproc_match, | |
739 | .suppress_bind_attrs = true, | |
740 | }, | |
741 | .probe = pru_rproc_probe, | |
742 | .remove = pru_rproc_remove, | |
743 | }; | |
744 | module_platform_driver(pru_rproc_driver); | |
745 | ||
746 | MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); | |
747 | MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); | |
748 | MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>"); | |
749 | MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver"); | |
750 | MODULE_LICENSE("GPL v2"); |