[mirror_ubuntu-hirsute-kernel.git] / drivers / remoteproc / qcom_q6v5_pas.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
 *
 * Copyright (C) 2016 Linaro Ltd
 * Copyright (C) 2014 Sony Mobile Communications AB
 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>

#include "qcom_common.h"
#include "qcom_q6v5.h"
#include "remoteproc_internal.h"

struct adsp_data {
	int crash_reason_smem;
	const char *firmware_name;
	int pas_id;
	bool has_aggre2_clk;
	bool auto_boot;

	char **active_pd_names;
	char **proxy_pd_names;

	const char *ssr_name;
	const char *sysmon_name;
	int ssctl_id;
};

struct qcom_adsp {
	struct device *dev;
	struct rproc *rproc;

	struct qcom_q6v5 q6v5;

	struct clk *xo;
	struct clk *aggre2_clk;

	struct regulator *cx_supply;
	struct regulator *px_supply;

	struct device *active_pds[1];
	struct device *proxy_pds[3];

	int active_pd_count;
	int proxy_pd_count;

	int pas_id;
	int crash_reason_smem;
	bool has_aggre2_clk;

	struct completion start_done;
	struct completion stop_done;

	phys_addr_t mem_phys;
	phys_addr_t mem_reloc;
	void *mem_region;
	size_t mem_size;

	struct qcom_rproc_glink glink_subdev;
	struct qcom_rproc_subdev smd_subdev;
	struct qcom_rproc_ssr ssr_subdev;
	struct qcom_sysmon *sysmon;
};

static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds,
			   size_t pd_count)
{
	int ret;
	int i;

	for (i = 0; i < pd_count; i++) {
		dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
		ret = pm_runtime_get_sync(pds[i]);
		if (ret < 0)
			goto unroll_pd_votes;
	}

	return 0;

unroll_pd_votes:
	for (i--; i >= 0; i--) {
		dev_pm_genpd_set_performance_state(pds[i], 0);
		pm_runtime_put(pds[i]);
	}

	return ret;
};

static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds,
			     size_t pd_count)
{
	int i;

	for (i = 0; i < pd_count; i++) {
		dev_pm_genpd_set_performance_state(pds[i], 0);
		pm_runtime_put(pds[i]);
	}
}

static int adsp_load(struct rproc *rproc, const struct firmware *fw)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;

	return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
			     adsp->mem_region, adsp->mem_phys, adsp->mem_size,
			     &adsp->mem_reloc);

}

static int adsp_start(struct rproc *rproc)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int ret;

	qcom_q6v5_prepare(&adsp->q6v5);

	ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
	if (ret < 0)
		goto disable_irqs;

	ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
	if (ret < 0)
		goto disable_active_pds;

	ret = clk_prepare_enable(adsp->xo);
	if (ret)
		goto disable_proxy_pds;

	ret = clk_prepare_enable(adsp->aggre2_clk);
	if (ret)
		goto disable_xo_clk;

	ret = regulator_enable(adsp->cx_supply);
	if (ret)
		goto disable_aggre2_clk;

	ret = regulator_enable(adsp->px_supply);
	if (ret)
		goto disable_cx_supply;

	ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
	if (ret) {
		dev_err(adsp->dev,
			"failed to authenticate image and release reset\n");
		goto disable_px_supply;
	}

	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
	if (ret == -ETIMEDOUT) {
		dev_err(adsp->dev, "start timed out\n");
		qcom_scm_pas_shutdown(adsp->pas_id);
		goto disable_px_supply;
	}

	return 0;

disable_px_supply:
	regulator_disable(adsp->px_supply);
disable_cx_supply:
	regulator_disable(adsp->cx_supply);
disable_aggre2_clk:
	clk_disable_unprepare(adsp->aggre2_clk);
disable_xo_clk:
	clk_disable_unprepare(adsp->xo);
disable_proxy_pds:
	adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
disable_active_pds:
	adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
disable_irqs:
	qcom_q6v5_unprepare(&adsp->q6v5);

	return ret;
}

static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
{
	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);

	regulator_disable(adsp->px_supply);
	regulator_disable(adsp->cx_supply);
	clk_disable_unprepare(adsp->aggre2_clk);
	clk_disable_unprepare(adsp->xo);
	adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
}

static int adsp_stop(struct rproc *rproc)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int handover;
	int ret;

	ret = qcom_q6v5_request_stop(&adsp->q6v5);
	if (ret == -ETIMEDOUT)
		dev_err(adsp->dev, "timed out on wait\n");

	ret = qcom_scm_pas_shutdown(adsp->pas_id);
	if (ret)
		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);

	adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
	handover = qcom_q6v5_unprepare(&adsp->q6v5);
	if (handover)
		qcom_pas_handover(&adsp->q6v5);

	return ret;
}

static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int offset;

	offset = da - adsp->mem_reloc;
	if (offset < 0 || offset + len > adsp->mem_size)
		return NULL;

	return adsp->mem_region + offset;
}

static const struct rproc_ops adsp_ops = {
	.start = adsp_start,
	.stop = adsp_stop,
	.da_to_va = adsp_da_to_va,
	.parse_fw = qcom_register_dump_segments,
	.load = adsp_load,
};

static int adsp_init_clock(struct qcom_adsp *adsp)
{
	int ret;

	adsp->xo = devm_clk_get(adsp->dev, "xo");
	if (IS_ERR(adsp->xo)) {
		ret = PTR_ERR(adsp->xo);
		if (ret != -EPROBE_DEFER)
			dev_err(adsp->dev, "failed to get xo clock");
		return ret;
	}

	if (adsp->has_aggre2_clk) {
		adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
		if (IS_ERR(adsp->aggre2_clk)) {
			ret = PTR_ERR(adsp->aggre2_clk);
			if (ret != -EPROBE_DEFER)
				dev_err(adsp->dev,
					"failed to get aggre2 clock");
			return ret;
		}
	}

	return 0;
}

static int adsp_init_regulator(struct qcom_adsp *adsp)
{
	adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
	if (IS_ERR(adsp->cx_supply))
		return PTR_ERR(adsp->cx_supply);

	regulator_set_load(adsp->cx_supply, 100000);

	adsp->px_supply = devm_regulator_get(adsp->dev, "px");
	return PTR_ERR_OR_ZERO(adsp->px_supply);
}

static int adsp_pds_attach(struct device *dev, struct device **devs,
			   char **pd_names)
{
	size_t num_pds = 0;
	int ret;
	int i;

	if (!pd_names)
		return 0;

	/* Handle single power domain */
	if (dev->pm_domain) {
		devs[0] = dev;
		pm_runtime_enable(dev);
		return 1;
	}

	while (pd_names[num_pds])
		num_pds++;

	for (i = 0; i < num_pds; i++) {
		devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
		if (IS_ERR_OR_NULL(devs[i])) {
			ret = PTR_ERR(devs[i]) ? : -ENODATA;
			goto unroll_attach;
		}
	}

	return num_pds;

unroll_attach:
	for (i--; i >= 0; i--)
		dev_pm_domain_detach(devs[i], false);

	return ret;
};

static void adsp_pds_detach(struct qcom_adsp *adsp, struct device **pds,
			    size_t pd_count)
{
	struct device *dev = adsp->dev;
	int i;

	/* Handle single power domain */
	if (dev->pm_domain && pd_count) {
		pm_runtime_disable(dev);
		return;
	}

	for (i = 0; i < pd_count; i++)
		dev_pm_domain_detach(pds[i], false);
}

static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
{
	struct device_node *node;
	struct resource r;
	int ret;

	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
	if (!node) {
		dev_err(adsp->dev, "no memory-region specified\n");
		return -EINVAL;
	}

	ret = of_address_to_resource(node, 0, &r);
	if (ret)
		return ret;

	adsp->mem_phys = adsp->mem_reloc = r.start;
	adsp->mem_size = resource_size(&r);
	adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
	if (!adsp->mem_region) {
		dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
			&r.start, adsp->mem_size);
		return -EBUSY;
	}

	return 0;
}

static int adsp_probe(struct platform_device *pdev)
{
	const struct adsp_data *desc;
	struct qcom_adsp *adsp;
	struct rproc *rproc;
	const char *fw_name;
	int ret;

	desc = of_device_get_match_data(&pdev->dev);
	if (!desc)
		return -EINVAL;

	if (!qcom_scm_is_available())
		return -EPROBE_DEFER;

	fw_name = desc->firmware_name;
	ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
				      &fw_name);
	if (ret < 0 && ret != -EINVAL)
		return ret;

	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
			    fw_name, sizeof(*adsp));
	if (!rproc) {
		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
		return -ENOMEM;
	}

	rproc->auto_boot = desc->auto_boot;

	adsp = (struct qcom_adsp *)rproc->priv;
	adsp->dev = &pdev->dev;
	adsp->rproc = rproc;
	adsp->pas_id = desc->pas_id;
	adsp->has_aggre2_clk = desc->has_aggre2_clk;
	platform_set_drvdata(pdev, adsp);

	ret = adsp_alloc_memory_region(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_init_clock(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_init_regulator(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
			      desc->active_pd_names);
	if (ret < 0)
		goto free_rproc;
	adsp->active_pd_count = ret;

	ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
			      desc->proxy_pd_names);
	if (ret < 0)
		goto detach_active_pds;
	adsp->proxy_pd_count = ret;

	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
			     qcom_pas_handover);
	if (ret)
		goto detach_proxy_pds;

	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
					      desc->sysmon_name,
					      desc->ssctl_id);
	if (IS_ERR(adsp->sysmon)) {
		ret = PTR_ERR(adsp->sysmon);
		goto detach_proxy_pds;
	}

	ret = rproc_add(rproc);
	if (ret)
		goto detach_proxy_pds;

	return 0;

detach_proxy_pds:
	adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
detach_active_pds:
	adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
free_rproc:
	rproc_free(rproc);

	return ret;
}

static int adsp_remove(struct platform_device *pdev)
{
	struct qcom_adsp *adsp = platform_get_drvdata(pdev);

	rproc_del(adsp->rproc);

	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
	qcom_remove_sysmon_subdev(adsp->sysmon);
	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
	rproc_free(adsp->rproc);

	return 0;
}

static const struct adsp_data adsp_resource_init = {
		.crash_reason_smem = 423,
		.firmware_name = "adsp.mdt",
		.pas_id = 1,
		.has_aggre2_clk = false,
		.auto_boot = true,
		.ssr_name = "lpass",
		.sysmon_name = "adsp",
		.ssctl_id = 0x14,
};

static const struct adsp_data sm8150_adsp_resource = {
		.crash_reason_smem = 423,
		.firmware_name = "adsp.mdt",
		.pas_id = 1,
		.has_aggre2_clk = false,
		.auto_boot = true,
		.active_pd_names = (char*[]){
			"load_state",
			NULL
		},
		.proxy_pd_names = (char*[]){
			"cx",
			NULL
		},
		.ssr_name = "lpass",
		.sysmon_name = "adsp",
		.ssctl_id = 0x14,
};

static const struct adsp_data msm8998_adsp_resource = {
		.crash_reason_smem = 423,
		.firmware_name = "adsp.mdt",
		.pas_id = 1,
		.has_aggre2_clk = false,
		.auto_boot = true,
		.proxy_pd_names = (char*[]){
			"cx",
			NULL
		},
		.ssr_name = "lpass",
		.sysmon_name = "adsp",
		.ssctl_id = 0x14,
};

static const struct adsp_data cdsp_resource_init = {
	.crash_reason_smem = 601,
	.firmware_name = "cdsp.mdt",
	.pas_id = 18,
	.has_aggre2_clk = false,
	.auto_boot = true,
	.ssr_name = "cdsp",
	.sysmon_name = "cdsp",
	.ssctl_id = 0x17,
};

static const struct adsp_data sm8150_cdsp_resource = {
	.crash_reason_smem = 601,
	.firmware_name = "cdsp.mdt",
	.pas_id = 18,
	.has_aggre2_clk = false,
	.auto_boot = true,
	.active_pd_names = (char*[]){
		"load_state",
		NULL
	},
	.proxy_pd_names = (char*[]){
		"cx",
		NULL
	},
	.ssr_name = "cdsp",
	.sysmon_name = "cdsp",
	.ssctl_id = 0x17,
};

static const struct adsp_data mpss_resource_init = {
	.crash_reason_smem = 421,
	.firmware_name = "modem.mdt",
	.pas_id = 4,
	.has_aggre2_clk = false,
	.auto_boot = false,
	.active_pd_names = (char*[]){
		"load_state",
		NULL
	},
	.proxy_pd_names = (char*[]){
		"cx",
		"mss",
		NULL
	},
	.ssr_name = "mpss",
	.sysmon_name = "modem",
	.ssctl_id = 0x12,
};

static const struct adsp_data slpi_resource_init = {
		.crash_reason_smem = 424,
		.firmware_name = "slpi.mdt",
		.pas_id = 12,
		.has_aggre2_clk = true,
		.auto_boot = true,
		.ssr_name = "dsps",
		.sysmon_name = "slpi",
		.ssctl_id = 0x16,
};

static const struct adsp_data sm8150_slpi_resource = {
		.crash_reason_smem = 424,
		.firmware_name = "slpi.mdt",
		.pas_id = 12,
		.has_aggre2_clk = false,
		.auto_boot = true,
		.active_pd_names = (char*[]){
			"load_state",
			NULL
		},
		.proxy_pd_names = (char*[]){
			"lcx",
			"lmx",
			NULL
		},
		.ssr_name = "dsps",
		.sysmon_name = "slpi",
		.ssctl_id = 0x16,
};

static const struct adsp_data msm8998_slpi_resource = {
		.crash_reason_smem = 424,
		.firmware_name = "slpi.mdt",
		.pas_id = 12,
		.has_aggre2_clk = true,
		.auto_boot = true,
		.proxy_pd_names = (char*[]){
			"ssc_cx",
			NULL
		},
		.ssr_name = "dsps",
		.sysmon_name = "slpi",
		.ssctl_id = 0x16,
};

static const struct adsp_data wcss_resource_init = {
	.crash_reason_smem = 421,
	.firmware_name = "wcnss.mdt",
	.pas_id = 6,
	.auto_boot = true,
	.ssr_name = "mpss",
	.sysmon_name = "wcnss",
	.ssctl_id = 0x12,
};

static const struct of_device_id adsp_of_match[] = {
	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
	{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource},
	{ .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource},
	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
	{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
	{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
	{ .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
	{ .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource},
	{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);

static struct platform_driver adsp_driver = {
	.probe = adsp_probe,
	.remove = adsp_remove,
	.driver = {
		.name = "qcom_q6v5_pas",
		.of_match_table = adsp_of_match,
	},
};

module_platform_driver(adsp_driver);
MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
b9e718e9	2	/*
90a068ed	3	* Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
b9e718e9 BA	4	*
	5	* Copyright (C) 2016 Linaro Ltd
	6	* Copyright (C) 2014 Sony Mobile Communications AB
	7	* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
b9e718e9 BA	8	*/
b9e718e9 BA	9
f33a7358	10	#include <linux/clk.h>
b9e718e9 BA	11	#include <linux/firmware.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
17ee2fb4 SS	18	#include <linux/pm_domain.h>
17ee2fb4 SS	19	#include <linux/pm_runtime.h>
b9e718e9 BA	20	#include <linux/qcom_scm.h>
	21	#include <linux/regulator/consumer.h>
	22	#include <linux/remoteproc.h>
2aad40d9	23	#include <linux/soc/qcom/mdt_loader.h>
b9e718e9 BA	24	#include <linux/soc/qcom/smem.h>
	25	#include <linux/soc/qcom/smem_state.h>
	26
bde440ee	27	#include "qcom_common.h"
6103b1a6	28	#include "qcom_q6v5.h"
b9e718e9 BA	29	#include "remoteproc_internal.h"
b9e718e9 BA	30
c7715e47 AKD	31	struct adsp_data {
	32	int crash_reason_smem;
	33	const char *firmware_name;
	34	int pas_id;
e323fc03	35	bool has_aggre2_clk;
b7ff96cc	36	bool auto_boot;
1fb82ee8	37
17ee2fb4 SS	38	char **active_pd_names;
	39	char **proxy_pd_names;
	40
1e140df0	41	const char *ssr_name;
1fb82ee8 BA	42	const char *sysmon_name;
1fb82ee8 BA	43	int ssctl_id;
c7715e47	44	};
b9e718e9 BA	45
	46	struct qcom_adsp {
	47	struct device *dev;
	48	struct rproc *rproc;
	49
6103b1a6	50	struct qcom_q6v5 q6v5;
b9e718e9	51
f33a7358	52	struct clk *xo;
e323fc03	53	struct clk *aggre2_clk;
f33a7358	54
b9e718e9	55	struct regulator *cx_supply;
e323fc03	56	struct regulator *px_supply;
b9e718e9	57
17ee2fb4 SS	58	struct device *active_pds[1];
	59	struct device *proxy_pds[3];
	60
	61	int active_pd_count;
	62	int proxy_pd_count;
	63
c7715e47 AKD	64	int pas_id;
c7715e47 AKD	65	int crash_reason_smem;
e323fc03	66	bool has_aggre2_clk;
c7715e47	67
b9e718e9 BA	68	struct completion start_done;
	69	struct completion stop_done;
	70
	71	phys_addr_t mem_phys;
	72	phys_addr_t mem_reloc;
	73	void *mem_region;
	74	size_t mem_size;
4b48921a	75
eea07023	76	struct qcom_rproc_glink glink_subdev;
4b48921a	77	struct qcom_rproc_subdev smd_subdev;
1e140df0	78	struct qcom_rproc_ssr ssr_subdev;
1fb82ee8	79	struct qcom_sysmon *sysmon;
b9e718e9 BA	80	};
b9e718e9 BA	81
17ee2fb4 SS	82	static int adsp_pds_enable(struct qcom_adsp adsp, struct device *pds,
	83	size_t pd_count)
	84	{
	85	int ret;
	86	int i;
	87
	88	for (i = 0; i < pd_count; i++) {
	89	dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
	90	ret = pm_runtime_get_sync(pds[i]);
	91	if (ret < 0)
	92	goto unroll_pd_votes;
	93	}
	94
	95	return 0;
	96
	97	unroll_pd_votes:
	98	for (i--; i >= 0; i--) {
	99	dev_pm_genpd_set_performance_state(pds[i], 0);
	100	pm_runtime_put(pds[i]);
	101	}
	102
	103	return ret;
	104	};
	105
	106	static void adsp_pds_disable(struct qcom_adsp adsp, struct device *pds,
	107	size_t pd_count)
	108	{
	109	int i;
	110
	111	for (i = 0; i < pd_count; i++) {
	112	dev_pm_genpd_set_performance_state(pds[i], 0);
	113	pm_runtime_put(pds[i]);
	114	}
	115	}
	116
b9e718e9 BA	117	static int adsp_load(struct rproc rproc, const struct firmware fw)
	118	{
	119	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
b9e718e9	120
7f0dd07a	121	return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
4dd27f54 BA	122	adsp->mem_region, adsp->mem_phys, adsp->mem_size,
	123	&adsp->mem_reloc);
	124
b9e718e9 BA	125	}
b9e718e9 BA	126
b9e718e9 BA	127	static int adsp_start(struct rproc *rproc)
	128	{
	129	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
	130	int ret;
	131
6103b1a6 BA	132	qcom_q6v5_prepare(&adsp->q6v5);
6103b1a6 BA	133
17ee2fb4 SS	134	ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
	135	if (ret < 0)
	136	goto disable_irqs;
	137
	138	ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
	139	if (ret < 0)
	140	goto disable_active_pds;
	141
f33a7358	142	ret = clk_prepare_enable(adsp->xo);
b9e718e9	143	if (ret)
17ee2fb4	144	goto disable_proxy_pds;
b9e718e9	145
e323fc03 AKD	146	ret = clk_prepare_enable(adsp->aggre2_clk);
	147	if (ret)
	148	goto disable_xo_clk;
	149
f33a7358 SJ	150	ret = regulator_enable(adsp->cx_supply);
f33a7358 SJ	151	if (ret)
e323fc03 AKD	152	goto disable_aggre2_clk;
	153
	154	ret = regulator_enable(adsp->px_supply);
	155	if (ret)
	156	goto disable_cx_supply;
f33a7358	157
c7715e47	158	ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
b9e718e9 BA	159	if (ret) {
	160	dev_err(adsp->dev,
	161	"failed to authenticate image and release reset\n");
e323fc03	162	goto disable_px_supply;
b9e718e9 BA	163	}
b9e718e9 BA	164
6103b1a6 BA	165	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
6103b1a6 BA	166	if (ret == -ETIMEDOUT) {
b9e718e9	167	dev_err(adsp->dev, "start timed out\n");
c7715e47	168	qcom_scm_pas_shutdown(adsp->pas_id);
e323fc03	169	goto disable_px_supply;
b9e718e9 BA	170	}
b9e718e9 BA	171
6103b1a6	172	return 0;
b9e718e9	173
e323fc03 AKD	174	disable_px_supply:
	175	regulator_disable(adsp->px_supply);
	176	disable_cx_supply:
b9e718e9	177	regulator_disable(adsp->cx_supply);
e323fc03 AKD	178	disable_aggre2_clk:
	179	clk_disable_unprepare(adsp->aggre2_clk);
	180	disable_xo_clk:
f33a7358	181	clk_disable_unprepare(adsp->xo);
17ee2fb4 SS	182	disable_proxy_pds:
	183	adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
	184	disable_active_pds:
	185	adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
2ac91aad SS	186	disable_irqs:
2ac91aad SS	187	qcom_q6v5_unprepare(&adsp->q6v5);
b9e718e9 BA	188
	189	return ret;
	190	}
	191
6103b1a6 BA	192	static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
	193	{
	194	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
	195
	196	regulator_disable(adsp->px_supply);
	197	regulator_disable(adsp->cx_supply);
	198	clk_disable_unprepare(adsp->aggre2_clk);
	199	clk_disable_unprepare(adsp->xo);
17ee2fb4	200	adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
6103b1a6 BA	201	}
6103b1a6 BA	202
b9e718e9 BA	203	static int adsp_stop(struct rproc *rproc)
	204	{
	205	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
6103b1a6	206	int handover;
b9e718e9 BA	207	int ret;
b9e718e9 BA	208
6103b1a6 BA	209	ret = qcom_q6v5_request_stop(&adsp->q6v5);
6103b1a6 BA	210	if (ret == -ETIMEDOUT)
b9e718e9 BA	211	dev_err(adsp->dev, "timed out on wait\n");
b9e718e9 BA	212
c7715e47	213	ret = qcom_scm_pas_shutdown(adsp->pas_id);
b9e718e9 BA	214	if (ret)
	215	dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
	216
17ee2fb4	217	adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
6103b1a6 BA	218	handover = qcom_q6v5_unprepare(&adsp->q6v5);
	219	if (handover)
	220	qcom_pas_handover(&adsp->q6v5);
	221
b9e718e9 BA	222	return ret;
	223	}
	224
	225	static void adsp_da_to_va(struct rproc rproc, u64 da, int len)
	226	{
	227	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
	228	int offset;
	229
	230	offset = da - adsp->mem_reloc;
	231	if (offset < 0 \|\| offset + len > adsp->mem_size)
	232	return NULL;
	233
	234	return adsp->mem_region + offset;
	235	}
	236
	237	static const struct rproc_ops adsp_ops = {
	238	.start = adsp_start,
	239	.stop = adsp_stop,
	240	.da_to_va = adsp_da_to_va,
dcb57ed4	241	.parse_fw = qcom_register_dump_segments,
0f21f9cc	242	.load = adsp_load,
b9e718e9 BA	243	};
b9e718e9 BA	244
f33a7358 SJ	245	static int adsp_init_clock(struct qcom_adsp *adsp)
	246	{
	247	int ret;
	248
	249	adsp->xo = devm_clk_get(adsp->dev, "xo");
	250	if (IS_ERR(adsp->xo)) {
	251	ret = PTR_ERR(adsp->xo);
	252	if (ret != -EPROBE_DEFER)
	253	dev_err(adsp->dev, "failed to get xo clock");
	254	return ret;
	255	}
	256
e323fc03 AKD	257	if (adsp->has_aggre2_clk) {
	258	adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
	259	if (IS_ERR(adsp->aggre2_clk)) {
	260	ret = PTR_ERR(adsp->aggre2_clk);
	261	if (ret != -EPROBE_DEFER)
	262	dev_err(adsp->dev,
	263	"failed to get aggre2 clock");
	264	return ret;
	265	}
	266	}
	267
f33a7358 SJ	268	return 0;
	269	}
	270
b9e718e9 BA	271	static int adsp_init_regulator(struct qcom_adsp *adsp)
	272	{
	273	adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
	274	if (IS_ERR(adsp->cx_supply))
	275	return PTR_ERR(adsp->cx_supply);
	276
	277	regulator_set_load(adsp->cx_supply, 100000);
	278
e323fc03	279	adsp->px_supply = devm_regulator_get(adsp->dev, "px");
c76929b3	280	return PTR_ERR_OR_ZERO(adsp->px_supply);
b9e718e9 BA	281	}
b9e718e9 BA	282
17ee2fb4 SS	283	static int adsp_pds_attach(struct device dev, struct device *devs,
	284	char **pd_names)
	285	{
	286	size_t num_pds = 0;
	287	int ret;
	288	int i;
	289
	290	if (!pd_names)
	291	return 0;
	292
	293	/* Handle single power domain */
	294	if (dev->pm_domain) {
	295	devs[0] = dev;
	296	pm_runtime_enable(dev);
	297	return 1;
	298	}
	299
	300	while (pd_names[num_pds])
	301	num_pds++;
	302
	303	for (i = 0; i < num_pds; i++) {
	304	devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
	305	if (IS_ERR_OR_NULL(devs[i])) {
	306	ret = PTR_ERR(devs[i]) ? : -ENODATA;
	307	goto unroll_attach;
	308	}
	309	}
	310
	311	return num_pds;
	312
	313	unroll_attach:
	314	for (i--; i >= 0; i--)
	315	dev_pm_domain_detach(devs[i], false);
	316
	317	return ret;
	318	};
	319
	320	static void adsp_pds_detach(struct qcom_adsp adsp, struct device *pds,
	321	size_t pd_count)
	322	{
	323	struct device *dev = adsp->dev;
	324	int i;
	325
	326	/* Handle single power domain */
	327	if (dev->pm_domain && pd_count) {
	328	pm_runtime_disable(dev);
	329	return;
	330	}
	331
	332	for (i = 0; i < pd_count; i++)
	333	dev_pm_domain_detach(pds[i], false);
	334	}
	335
b9e718e9 BA	336	static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
	337	{
	338	struct device_node *node;
	339	struct resource r;
	340	int ret;
	341
	342	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
	343	if (!node) {
	344	dev_err(adsp->dev, "no memory-region specified\n");
	345	return -EINVAL;
	346	}
	347
	348	ret = of_address_to_resource(node, 0, &r);
	349	if (ret)
	350	return ret;
	351
	352	adsp->mem_phys = adsp->mem_reloc = r.start;
	353	adsp->mem_size = resource_size(&r);
	354	adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
	355	if (!adsp->mem_region) {
	356	dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
	357	&r.start, adsp->mem_size);
	358	return -EBUSY;
	359	}
	360
	361	return 0;
	362	}
	363
	364	static int adsp_probe(struct platform_device *pdev)
	365	{
c7715e47	366	const struct adsp_data *desc;
b9e718e9 BA	367	struct qcom_adsp *adsp;
b9e718e9 BA	368	struct rproc *rproc;
a5a4e02d	369	const char *fw_name;
b9e718e9 BA	370	int ret;
b9e718e9 BA	371
c7715e47 AKD	372	desc = of_device_get_match_data(&pdev->dev);
	373	if (!desc)
	374	return -EINVAL;
	375
b9e718e9 BA	376	if (!qcom_scm_is_available())
	377	return -EPROBE_DEFER;
	378
a5a4e02d SS	379	fw_name = desc->firmware_name;
	380	ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
	381	&fw_name);
	382	if (ret < 0 && ret != -EINVAL)
	383	return ret;
	384
b9e718e9	385	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
a5a4e02d	386	fw_name, sizeof(*adsp));
b9e718e9 BA	387	if (!rproc) {
	388	dev_err(&pdev->dev, "unable to allocate remoteproc\n");
	389	return -ENOMEM;
	390	}
	391
b7ff96cc SS	392	rproc->auto_boot = desc->auto_boot;
b7ff96cc SS	393
b9e718e9 BA	394	adsp = (struct qcom_adsp *)rproc->priv;
	395	adsp->dev = &pdev->dev;
	396	adsp->rproc = rproc;
c7715e47	397	adsp->pas_id = desc->pas_id;
e323fc03	398	adsp->has_aggre2_clk = desc->has_aggre2_clk;
b9e718e9 BA	399	platform_set_drvdata(pdev, adsp);
b9e718e9 BA	400
b9e718e9 BA	401	ret = adsp_alloc_memory_region(adsp);
	402	if (ret)
	403	goto free_rproc;
	404
f33a7358 SJ	405	ret = adsp_init_clock(adsp);
	406	if (ret)
	407	goto free_rproc;
	408
b9e718e9 BA	409	ret = adsp_init_regulator(adsp);
	410	if (ret)
	411	goto free_rproc;
	412
17ee2fb4 SS	413	ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
	414	desc->active_pd_names);
	415	if (ret < 0)
	416	goto free_rproc;
	417	adsp->active_pd_count = ret;
	418
	419	ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
	420	desc->proxy_pd_names);
	421	if (ret < 0)
	422	goto detach_active_pds;
	423	adsp->proxy_pd_count = ret;
	424
6103b1a6 BA	425	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
	426	qcom_pas_handover);
	427	if (ret)
17ee2fb4	428	goto detach_proxy_pds;
b9e718e9	429
eea07023	430	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
4b48921a	431	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
1e140df0	432	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
1fb82ee8 BA	433	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
	434	desc->sysmon_name,
	435	desc->ssctl_id);
027045a6 SS	436	if (IS_ERR(adsp->sysmon)) {
027045a6 SS	437	ret = PTR_ERR(adsp->sysmon);
17ee2fb4	438	goto detach_proxy_pds;
027045a6	439	}
4b48921a	440
b9e718e9 BA	441	ret = rproc_add(rproc);
b9e718e9 BA	442	if (ret)
17ee2fb4	443	goto detach_proxy_pds;
b9e718e9 BA	444
	445	return 0;
	446
17ee2fb4 SS	447	detach_proxy_pds:
	448	adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
	449	detach_active_pds:
	450	adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
b9e718e9	451	free_rproc:
90a80d88	452	rproc_free(rproc);
b9e718e9 BA	453
	454	return ret;
	455	}
	456
	457	static int adsp_remove(struct platform_device *pdev)
	458	{
	459	struct qcom_adsp *adsp = platform_get_drvdata(pdev);
	460
b9e718e9	461	rproc_del(adsp->rproc);
4b48921a	462
eea07023	463	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
1fb82ee8	464	qcom_remove_sysmon_subdev(adsp->sysmon);
4b48921a	465	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
1e140df0	466	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
90a80d88	467	rproc_free(adsp->rproc);
b9e718e9 BA	468
	469	return 0;
	470	}
	471
c7715e47 AKD	472	static const struct adsp_data adsp_resource_init = {
	473	.crash_reason_smem = 423,
	474	.firmware_name = "adsp.mdt",
	475	.pas_id = 1,
e323fc03	476	.has_aggre2_clk = false,
b7ff96cc	477	.auto_boot = true,
1e140df0	478	.ssr_name = "lpass",
1fb82ee8 BA	479	.sysmon_name = "adsp",
1fb82ee8 BA	480	.ssctl_id = 0x14,
c7715e47 AKD	481	};
c7715e47 AKD	482
15f4ae1e SS	483	static const struct adsp_data sm8150_adsp_resource = {
	484	.crash_reason_smem = 423,
	485	.firmware_name = "adsp.mdt",
	486	.pas_id = 1,
	487	.has_aggre2_clk = false,
b7ff96cc	488	.auto_boot = true,
15f4ae1e SS	489	.active_pd_names = (char*[]){
	490	"load_state",
	491	NULL
	492	},
	493	.proxy_pd_names = (char*[]){
	494	"cx",
	495	NULL
	496	},
	497	.ssr_name = "lpass",
	498	.sysmon_name = "adsp",
	499	.ssctl_id = 0x14,
	500	};
	501
7c77e317 SS	502	static const struct adsp_data msm8998_adsp_resource = {
	503	.crash_reason_smem = 423,
	504	.firmware_name = "adsp.mdt",
	505	.pas_id = 1,
	506	.has_aggre2_clk = false,
	507	.auto_boot = true,
	508	.proxy_pd_names = (char*[]){
	509	"cx",
	510	NULL
	511	},
	512	.ssr_name = "lpass",
	513	.sysmon_name = "adsp",
	514	.ssctl_id = 0x14,
	515	};
	516
3b0d1b65 BA	517	static const struct adsp_data cdsp_resource_init = {
	518	.crash_reason_smem = 601,
	519	.firmware_name = "cdsp.mdt",
	520	.pas_id = 18,
	521	.has_aggre2_clk = false,
b7ff96cc	522	.auto_boot = true,
3b0d1b65 BA	523	.ssr_name = "cdsp",
	524	.sysmon_name = "cdsp",
	525	.ssctl_id = 0x17,
	526	};
	527
15f4ae1e SS	528	static const struct adsp_data sm8150_cdsp_resource = {
	529	.crash_reason_smem = 601,
	530	.firmware_name = "cdsp.mdt",
	531	.pas_id = 18,
	532	.has_aggre2_clk = false,
b7ff96cc	533	.auto_boot = true,
15f4ae1e SS	534	.active_pd_names = (char*[]){
	535	"load_state",
	536	NULL
	537	},
	538	.proxy_pd_names = (char*[]){
	539	"cx",
	540	NULL
	541	},
	542	.ssr_name = "cdsp",
	543	.sysmon_name = "cdsp",
	544	.ssctl_id = 0x17,
	545	};
	546
	547	static const struct adsp_data mpss_resource_init = {
	548	.crash_reason_smem = 421,
	549	.firmware_name = "modem.mdt",
	550	.pas_id = 4,
	551	.has_aggre2_clk = false,
b7ff96cc	552	.auto_boot = false,
15f4ae1e SS	553	.active_pd_names = (char*[]){
	554	"load_state",
	555	NULL
	556	},
	557	.proxy_pd_names = (char*[]){
	558	"cx",
	559	"mss",
	560	NULL
	561	},
	562	.ssr_name = "mpss",
	563	.sysmon_name = "modem",
	564	.ssctl_id = 0x12,
	565	};
	566
90a068ed AKD	567	static const struct adsp_data slpi_resource_init = {
	568	.crash_reason_smem = 424,
	569	.firmware_name = "slpi.mdt",
	570	.pas_id = 12,
	571	.has_aggre2_clk = true,
b7ff96cc	572	.auto_boot = true,
1e140df0	573	.ssr_name = "dsps",
1fb82ee8 BA	574	.sysmon_name = "slpi",
1fb82ee8 BA	575	.ssctl_id = 0x16,
90a068ed AKD	576	};
90a068ed AKD	577
15f4ae1e SS	578	static const struct adsp_data sm8150_slpi_resource = {
	579	.crash_reason_smem = 424,
	580	.firmware_name = "slpi.mdt",
	581	.pas_id = 12,
	582	.has_aggre2_clk = false,
b7ff96cc	583	.auto_boot = true,
15f4ae1e SS	584	.active_pd_names = (char*[]){
	585	"load_state",
	586	NULL
	587	},
	588	.proxy_pd_names = (char*[]){
	589	"lcx",
	590	"lmx",
	591	NULL
	592	},
	593	.ssr_name = "dsps",
	594	.sysmon_name = "slpi",
	595	.ssctl_id = 0x16,
	596	};
	597
7c77e317 SS	598	static const struct adsp_data msm8998_slpi_resource = {
	599	.crash_reason_smem = 424,
	600	.firmware_name = "slpi.mdt",
	601	.pas_id = 12,
	602	.has_aggre2_clk = true,
	603	.auto_boot = true,
	604	.proxy_pd_names = (char*[]){
	605	"ssc_cx",
	606	NULL
	607	},
	608	.ssr_name = "dsps",
	609	.sysmon_name = "slpi",
	610	.ssctl_id = 0x16,
	611	};
	612
0af93682 BA	613	static const struct adsp_data wcss_resource_init = {
	614	.crash_reason_smem = 421,
	615	.firmware_name = "wcnss.mdt",
	616	.pas_id = 6,
b7ff96cc	617	.auto_boot = true,
0af93682 BA	618	.ssr_name = "mpss",
	619	.sysmon_name = "wcnss",
	620	.ssctl_id = 0x12,
	621	};
	622
b9e718e9	623	static const struct of_device_id adsp_of_match[] = {
c7715e47 AKD	624	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
c7715e47 AKD	625	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
90a068ed	626	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
7c77e317 SS	627	{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource},
7c77e317 SS	628	{ .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource},
0af93682 BA	629	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
	630	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
	631	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
3b0d1b65 BA	632	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
3b0d1b65 BA	633	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
15f4ae1e SS	634	{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
	635	{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
	636	{ .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
	637	{ .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource},
b9e718e9 BA	638	{ },
b9e718e9 BA	639	};
62423472	640	MODULE_DEVICE_TABLE(of, adsp_of_match);
b9e718e9 BA	641
	642	static struct platform_driver adsp_driver = {
	643	.probe = adsp_probe,
	644	.remove = adsp_remove,
	645	.driver = {
9e004f97	646	.name = "qcom_q6v5_pas",
b9e718e9 BA	647	.of_match_table = adsp_of_match,
	648	},
	649	};
	650
	651	module_platform_driver(adsp_driver);
9e004f97	652	MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
b9e718e9	653	MODULE_LICENSE("GPL v2");