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Commit | Line | Data |
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051fb70f BA |
1 | /* |
2 | * Qualcomm Peripheral Image Loader | |
3 | * | |
4 | * Copyright (C) 2016 Linaro Ltd. | |
5 | * Copyright (C) 2014 Sony Mobile Communications AB | |
6 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/mfd/syscon.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of_address.h> | |
7a8ffe1f | 26 | #include <linux/of_device.h> |
051fb70f BA |
27 | #include <linux/platform_device.h> |
28 | #include <linux/regmap.h> | |
29 | #include <linux/regulator/consumer.h> | |
30 | #include <linux/remoteproc.h> | |
31 | #include <linux/reset.h> | |
2aad40d9 | 32 | #include <linux/soc/qcom/mdt_loader.h> |
051fb70f BA |
33 | #include <linux/soc/qcom/smem.h> |
34 | #include <linux/soc/qcom/smem_state.h> | |
9f058fa2 | 35 | #include <linux/iopoll.h> |
051fb70f BA |
36 | |
37 | #include "remoteproc_internal.h" | |
bde440ee | 38 | #include "qcom_common.h" |
051fb70f BA |
39 | |
40 | #include <linux/qcom_scm.h> | |
41 | ||
051fb70f BA |
42 | #define MPSS_CRASH_REASON_SMEM 421 |
43 | ||
44 | /* RMB Status Register Values */ | |
45 | #define RMB_PBL_SUCCESS 0x1 | |
46 | ||
47 | #define RMB_MBA_XPU_UNLOCKED 0x1 | |
48 | #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2 | |
49 | #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3 | |
50 | #define RMB_MBA_AUTH_COMPLETE 0x4 | |
51 | ||
52 | /* PBL/MBA interface registers */ | |
53 | #define RMB_MBA_IMAGE_REG 0x00 | |
54 | #define RMB_PBL_STATUS_REG 0x04 | |
55 | #define RMB_MBA_COMMAND_REG 0x08 | |
56 | #define RMB_MBA_STATUS_REG 0x0C | |
57 | #define RMB_PMI_META_DATA_REG 0x10 | |
58 | #define RMB_PMI_CODE_START_REG 0x14 | |
59 | #define RMB_PMI_CODE_LENGTH_REG 0x18 | |
60 | ||
61 | #define RMB_CMD_META_DATA_READY 0x1 | |
62 | #define RMB_CMD_LOAD_READY 0x2 | |
63 | ||
64 | /* QDSP6SS Register Offsets */ | |
65 | #define QDSP6SS_RESET_REG 0x014 | |
66 | #define QDSP6SS_GFMUX_CTL_REG 0x020 | |
67 | #define QDSP6SS_PWR_CTL_REG 0x030 | |
9f058fa2 AKD |
68 | #define QDSP6SS_MEM_PWR_CTL 0x0B0 |
69 | #define QDSP6SS_STRAP_ACC 0x110 | |
051fb70f BA |
70 | |
71 | /* AXI Halt Register Offsets */ | |
72 | #define AXI_HALTREQ_REG 0x0 | |
73 | #define AXI_HALTACK_REG 0x4 | |
74 | #define AXI_IDLE_REG 0x8 | |
75 | ||
76 | #define HALT_ACK_TIMEOUT_MS 100 | |
77 | ||
78 | /* QDSP6SS_RESET */ | |
79 | #define Q6SS_STOP_CORE BIT(0) | |
80 | #define Q6SS_CORE_ARES BIT(1) | |
81 | #define Q6SS_BUS_ARES_ENABLE BIT(2) | |
82 | ||
83 | /* QDSP6SS_GFMUX_CTL */ | |
84 | #define Q6SS_CLK_ENABLE BIT(1) | |
85 | ||
86 | /* QDSP6SS_PWR_CTL */ | |
87 | #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) | |
88 | #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) | |
89 | #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) | |
90 | #define Q6SS_L2TAG_SLP_NRET_N BIT(16) | |
91 | #define Q6SS_ETB_SLP_NRET_N BIT(17) | |
92 | #define Q6SS_L2DATA_STBY_N BIT(18) | |
93 | #define Q6SS_SLP_RET_N BIT(19) | |
94 | #define Q6SS_CLAMP_IO BIT(20) | |
95 | #define QDSS_BHS_ON BIT(21) | |
96 | #define QDSS_LDO_BYP BIT(22) | |
97 | ||
9f058fa2 AKD |
98 | /* QDSP6v56 parameters */ |
99 | #define QDSP6v56_LDO_BYP BIT(25) | |
100 | #define QDSP6v56_BHS_ON BIT(24) | |
101 | #define QDSP6v56_CLAMP_WL BIT(21) | |
102 | #define QDSP6v56_CLAMP_QMC_MEM BIT(22) | |
103 | #define HALT_CHECK_MAX_LOOPS 200 | |
104 | #define QDSP6SS_XO_CBCR 0x0038 | |
105 | #define QDSP6SS_ACC_OVERRIDE_VAL 0x20 | |
106 | ||
19f902b5 AKD |
107 | struct reg_info { |
108 | struct regulator *reg; | |
109 | int uV; | |
110 | int uA; | |
111 | }; | |
112 | ||
113 | struct qcom_mss_reg_res { | |
114 | const char *supply; | |
115 | int uV; | |
116 | int uA; | |
117 | }; | |
118 | ||
7a8ffe1f AKD |
119 | struct rproc_hexagon_res { |
120 | const char *hexagon_mba_image; | |
ec671b53 AB |
121 | struct qcom_mss_reg_res *proxy_supply; |
122 | struct qcom_mss_reg_res *active_supply; | |
39b2410b AKD |
123 | char **proxy_clk_names; |
124 | char **active_clk_names; | |
9f058fa2 | 125 | int version; |
6c5a9dc2 | 126 | bool need_mem_protection; |
7a8ffe1f AKD |
127 | }; |
128 | ||
051fb70f BA |
129 | struct q6v5 { |
130 | struct device *dev; | |
131 | struct rproc *rproc; | |
132 | ||
133 | void __iomem *reg_base; | |
134 | void __iomem *rmb_base; | |
135 | ||
136 | struct regmap *halt_map; | |
137 | u32 halt_q6; | |
138 | u32 halt_modem; | |
139 | u32 halt_nc; | |
140 | ||
141 | struct reset_control *mss_restart; | |
142 | ||
143 | struct qcom_smem_state *state; | |
144 | unsigned stop_bit; | |
145 | ||
39b2410b AKD |
146 | struct clk *active_clks[8]; |
147 | struct clk *proxy_clks[4]; | |
148 | int active_clk_count; | |
149 | int proxy_clk_count; | |
150 | ||
19f902b5 AKD |
151 | struct reg_info active_regs[1]; |
152 | struct reg_info proxy_regs[3]; | |
153 | int active_reg_count; | |
154 | int proxy_reg_count; | |
051fb70f BA |
155 | |
156 | struct completion start_done; | |
157 | struct completion stop_done; | |
158 | bool running; | |
159 | ||
160 | phys_addr_t mba_phys; | |
161 | void *mba_region; | |
162 | size_t mba_size; | |
163 | ||
164 | phys_addr_t mpss_phys; | |
165 | phys_addr_t mpss_reloc; | |
166 | void *mpss_region; | |
167 | size_t mpss_size; | |
4b48921a BA |
168 | |
169 | struct qcom_rproc_subdev smd_subdev; | |
1e140df0 | 170 | struct qcom_rproc_ssr ssr_subdev; |
1fb82ee8 | 171 | struct qcom_sysmon *sysmon; |
6c5a9dc2 AKD |
172 | bool need_mem_protection; |
173 | int mpss_perm; | |
174 | int mba_perm; | |
9f058fa2 AKD |
175 | int version; |
176 | }; | |
6c5a9dc2 | 177 | |
9f058fa2 AKD |
178 | enum { |
179 | MSS_MSM8916, | |
180 | MSS_MSM8974, | |
181 | MSS_MSM8996, | |
051fb70f BA |
182 | }; |
183 | ||
19f902b5 AKD |
184 | static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, |
185 | const struct qcom_mss_reg_res *reg_res) | |
051fb70f | 186 | { |
19f902b5 AKD |
187 | int rc; |
188 | int i; | |
051fb70f | 189 | |
2bb5d906 BA |
190 | if (!reg_res) |
191 | return 0; | |
192 | ||
19f902b5 AKD |
193 | for (i = 0; reg_res[i].supply; i++) { |
194 | regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); | |
195 | if (IS_ERR(regs[i].reg)) { | |
196 | rc = PTR_ERR(regs[i].reg); | |
197 | if (rc != -EPROBE_DEFER) | |
198 | dev_err(dev, "Failed to get %s\n regulator", | |
199 | reg_res[i].supply); | |
200 | return rc; | |
201 | } | |
051fb70f | 202 | |
19f902b5 AKD |
203 | regs[i].uV = reg_res[i].uV; |
204 | regs[i].uA = reg_res[i].uA; | |
051fb70f BA |
205 | } |
206 | ||
19f902b5 | 207 | return i; |
051fb70f BA |
208 | } |
209 | ||
19f902b5 AKD |
210 | static int q6v5_regulator_enable(struct q6v5 *qproc, |
211 | struct reg_info *regs, int count) | |
051fb70f | 212 | { |
051fb70f | 213 | int ret; |
19f902b5 | 214 | int i; |
051fb70f | 215 | |
19f902b5 AKD |
216 | for (i = 0; i < count; i++) { |
217 | if (regs[i].uV > 0) { | |
218 | ret = regulator_set_voltage(regs[i].reg, | |
219 | regs[i].uV, INT_MAX); | |
220 | if (ret) { | |
221 | dev_err(qproc->dev, | |
222 | "Failed to request voltage for %d.\n", | |
223 | i); | |
224 | goto err; | |
225 | } | |
226 | } | |
051fb70f | 227 | |
19f902b5 AKD |
228 | if (regs[i].uA > 0) { |
229 | ret = regulator_set_load(regs[i].reg, | |
230 | regs[i].uA); | |
231 | if (ret < 0) { | |
232 | dev_err(qproc->dev, | |
233 | "Failed to set regulator mode\n"); | |
234 | goto err; | |
235 | } | |
236 | } | |
237 | ||
238 | ret = regulator_enable(regs[i].reg); | |
239 | if (ret) { | |
240 | dev_err(qproc->dev, "Regulator enable failed\n"); | |
241 | goto err; | |
242 | } | |
243 | } | |
244 | ||
245 | return 0; | |
246 | err: | |
247 | for (; i >= 0; i--) { | |
248 | if (regs[i].uV > 0) | |
249 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
250 | ||
251 | if (regs[i].uA > 0) | |
252 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 253 | |
19f902b5 AKD |
254 | regulator_disable(regs[i].reg); |
255 | } | |
051fb70f | 256 | |
19f902b5 | 257 | return ret; |
051fb70f BA |
258 | } |
259 | ||
19f902b5 AKD |
260 | static void q6v5_regulator_disable(struct q6v5 *qproc, |
261 | struct reg_info *regs, int count) | |
051fb70f | 262 | { |
19f902b5 AKD |
263 | int i; |
264 | ||
265 | for (i = 0; i < count; i++) { | |
266 | if (regs[i].uV > 0) | |
267 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
051fb70f | 268 | |
19f902b5 AKD |
269 | if (regs[i].uA > 0) |
270 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 271 | |
19f902b5 AKD |
272 | regulator_disable(regs[i].reg); |
273 | } | |
051fb70f BA |
274 | } |
275 | ||
39b2410b AKD |
276 | static int q6v5_clk_enable(struct device *dev, |
277 | struct clk **clks, int count) | |
278 | { | |
279 | int rc; | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < count; i++) { | |
283 | rc = clk_prepare_enable(clks[i]); | |
284 | if (rc) { | |
285 | dev_err(dev, "Clock enable failed\n"); | |
286 | goto err; | |
287 | } | |
288 | } | |
289 | ||
290 | return 0; | |
291 | err: | |
292 | for (i--; i >= 0; i--) | |
293 | clk_disable_unprepare(clks[i]); | |
294 | ||
295 | return rc; | |
296 | } | |
297 | ||
298 | static void q6v5_clk_disable(struct device *dev, | |
299 | struct clk **clks, int count) | |
300 | { | |
301 | int i; | |
302 | ||
303 | for (i = 0; i < count; i++) | |
304 | clk_disable_unprepare(clks[i]); | |
305 | } | |
306 | ||
6c5a9dc2 AKD |
307 | static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, |
308 | bool remote_owner, phys_addr_t addr, | |
309 | size_t size) | |
310 | { | |
311 | struct qcom_scm_vmperm next; | |
6c5a9dc2 AKD |
312 | |
313 | if (!qproc->need_mem_protection) | |
314 | return 0; | |
315 | if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA)) | |
316 | return 0; | |
317 | if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS)) | |
318 | return 0; | |
319 | ||
320 | next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS; | |
321 | next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX; | |
322 | ||
9f2a4342 BA |
323 | return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), |
324 | current_perm, &next, 1); | |
6c5a9dc2 AKD |
325 | } |
326 | ||
051fb70f BA |
327 | static int q6v5_load(struct rproc *rproc, const struct firmware *fw) |
328 | { | |
329 | struct q6v5 *qproc = rproc->priv; | |
330 | ||
331 | memcpy(qproc->mba_region, fw->data, fw->size); | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
051fb70f BA |
336 | static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms) |
337 | { | |
338 | unsigned long timeout; | |
339 | s32 val; | |
340 | ||
341 | timeout = jiffies + msecs_to_jiffies(ms); | |
342 | for (;;) { | |
343 | val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); | |
344 | if (val) | |
345 | break; | |
346 | ||
347 | if (time_after(jiffies, timeout)) | |
348 | return -ETIMEDOUT; | |
349 | ||
350 | msleep(1); | |
351 | } | |
352 | ||
353 | return val; | |
354 | } | |
355 | ||
356 | static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) | |
357 | { | |
358 | ||
359 | unsigned long timeout; | |
360 | s32 val; | |
361 | ||
362 | timeout = jiffies + msecs_to_jiffies(ms); | |
363 | for (;;) { | |
364 | val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); | |
365 | if (val < 0) | |
366 | break; | |
367 | ||
368 | if (!status && val) | |
369 | break; | |
370 | else if (status && val == status) | |
371 | break; | |
372 | ||
373 | if (time_after(jiffies, timeout)) | |
374 | return -ETIMEDOUT; | |
375 | ||
376 | msleep(1); | |
377 | } | |
378 | ||
379 | return val; | |
380 | } | |
381 | ||
382 | static int q6v5proc_reset(struct q6v5 *qproc) | |
383 | { | |
384 | u32 val; | |
385 | int ret; | |
9f058fa2 | 386 | int i; |
051fb70f | 387 | |
051fb70f | 388 | |
9f058fa2 AKD |
389 | if (qproc->version == MSS_MSM8996) { |
390 | /* Override the ACC value if required */ | |
391 | writel(QDSP6SS_ACC_OVERRIDE_VAL, | |
392 | qproc->reg_base + QDSP6SS_STRAP_ACC); | |
051fb70f | 393 | |
9f058fa2 AKD |
394 | /* Assert resets, stop core */ |
395 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
396 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
397 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
398 | ||
399 | /* BHS require xo cbcr to be enabled */ | |
400 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
401 | val |= 0x1; | |
402 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); | |
403 | ||
404 | /* Read CLKOFF bit to go low indicating CLK is enabled */ | |
405 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
406 | val, !(val & BIT(31)), 1, | |
407 | HALT_CHECK_MAX_LOOPS); | |
408 | if (ret) { | |
409 | dev_err(qproc->dev, | |
410 | "xo cbcr enabling timed out (rc:%d)\n", ret); | |
411 | return ret; | |
412 | } | |
413 | /* Enable power block headswitch and wait for it to stabilize */ | |
414 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
415 | val |= QDSP6v56_BHS_ON; | |
416 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
417 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
418 | udelay(1); | |
419 | ||
420 | /* Put LDO in bypass mode */ | |
421 | val |= QDSP6v56_LDO_BYP; | |
422 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
423 | ||
424 | /* Deassert QDSP6 compiler memory clamp */ | |
425 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
426 | val &= ~QDSP6v56_CLAMP_QMC_MEM; | |
427 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
428 | ||
429 | /* Deassert memory peripheral sleep and L2 memory standby */ | |
430 | val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; | |
431 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
432 | ||
433 | /* Turn on L1, L2, ETB and JU memories 1 at a time */ | |
434 | val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); | |
435 | for (i = 19; i >= 0; i--) { | |
436 | val |= BIT(i); | |
437 | writel(val, qproc->reg_base + | |
438 | QDSP6SS_MEM_PWR_CTL); | |
439 | /* | |
440 | * Read back value to ensure the write is done then | |
441 | * wait for 1us for both memory peripheral and data | |
442 | * array to turn on. | |
443 | */ | |
444 | val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); | |
445 | udelay(1); | |
446 | } | |
447 | /* Remove word line clamp */ | |
448 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
449 | val &= ~QDSP6v56_CLAMP_WL; | |
450 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
451 | } else { | |
452 | /* Assert resets, stop core */ | |
453 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
454 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
455 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
456 | ||
457 | /* Enable power block headswitch and wait for it to stabilize */ | |
458 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
459 | val |= QDSS_BHS_ON | QDSS_LDO_BYP; | |
460 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
461 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
462 | udelay(1); | |
463 | /* | |
464 | * Turn on memories. L2 banks should be done individually | |
465 | * to minimize inrush current. | |
466 | */ | |
467 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
468 | val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | | |
469 | Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; | |
470 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
471 | val |= Q6SS_L2DATA_SLP_NRET_N_2; | |
472 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
473 | val |= Q6SS_L2DATA_SLP_NRET_N_1; | |
474 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
475 | val |= Q6SS_L2DATA_SLP_NRET_N_0; | |
476 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
477 | } | |
051fb70f BA |
478 | /* Remove IO clamp */ |
479 | val &= ~Q6SS_CLAMP_IO; | |
480 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
481 | ||
482 | /* Bring core out of reset */ | |
483 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
484 | val &= ~Q6SS_CORE_ARES; | |
485 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
486 | ||
487 | /* Turn on core clock */ | |
488 | val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
489 | val |= Q6SS_CLK_ENABLE; | |
490 | writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
491 | ||
492 | /* Start core execution */ | |
493 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
494 | val &= ~Q6SS_STOP_CORE; | |
495 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
496 | ||
497 | /* Wait for PBL status */ | |
498 | ret = q6v5_rmb_pbl_wait(qproc, 1000); | |
499 | if (ret == -ETIMEDOUT) { | |
500 | dev_err(qproc->dev, "PBL boot timed out\n"); | |
501 | } else if (ret != RMB_PBL_SUCCESS) { | |
502 | dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret); | |
503 | ret = -EINVAL; | |
504 | } else { | |
505 | ret = 0; | |
506 | } | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
511 | static void q6v5proc_halt_axi_port(struct q6v5 *qproc, | |
512 | struct regmap *halt_map, | |
513 | u32 offset) | |
514 | { | |
515 | unsigned long timeout; | |
516 | unsigned int val; | |
517 | int ret; | |
518 | ||
519 | /* Check if we're already idle */ | |
520 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
521 | if (!ret && val) | |
522 | return; | |
523 | ||
524 | /* Assert halt request */ | |
525 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); | |
526 | ||
527 | /* Wait for halt */ | |
528 | timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS); | |
529 | for (;;) { | |
530 | ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); | |
531 | if (ret || val || time_after(jiffies, timeout)) | |
532 | break; | |
533 | ||
534 | msleep(1); | |
535 | } | |
536 | ||
537 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
538 | if (ret || !val) | |
539 | dev_err(qproc->dev, "port failed halt\n"); | |
540 | ||
541 | /* Clear halt request (port will remain halted until reset) */ | |
542 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); | |
543 | } | |
544 | ||
545 | static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) | |
546 | { | |
00085f1e | 547 | unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; |
051fb70f | 548 | dma_addr_t phys; |
6c5a9dc2 AKD |
549 | int mdata_perm; |
550 | int xferop_ret; | |
051fb70f BA |
551 | void *ptr; |
552 | int ret; | |
553 | ||
00085f1e | 554 | ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs); |
051fb70f BA |
555 | if (!ptr) { |
556 | dev_err(qproc->dev, "failed to allocate mdt buffer\n"); | |
557 | return -ENOMEM; | |
558 | } | |
559 | ||
560 | memcpy(ptr, fw->data, fw->size); | |
561 | ||
6c5a9dc2 AKD |
562 | /* Hypervisor mapping to access metadata by modem */ |
563 | mdata_perm = BIT(QCOM_SCM_VMID_HLOS); | |
564 | ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, | |
565 | true, phys, fw->size); | |
9f2a4342 BA |
566 | if (ret) { |
567 | dev_err(qproc->dev, | |
568 | "assigning Q6 access to metadata failed: %d\n", ret); | |
1a5d5c59 CJ |
569 | ret = -EAGAIN; |
570 | goto free_dma_attrs; | |
9f2a4342 | 571 | } |
6c5a9dc2 | 572 | |
051fb70f BA |
573 | writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG); |
574 | writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
575 | ||
576 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000); | |
577 | if (ret == -ETIMEDOUT) | |
578 | dev_err(qproc->dev, "MPSS header authentication timed out\n"); | |
579 | else if (ret < 0) | |
580 | dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret); | |
581 | ||
6c5a9dc2 AKD |
582 | /* Metadata authentication done, remove modem access */ |
583 | xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, | |
584 | false, phys, fw->size); | |
585 | if (xferop_ret) | |
586 | dev_warn(qproc->dev, | |
587 | "mdt buffer not reclaimed system may become unstable\n"); | |
588 | ||
1a5d5c59 | 589 | free_dma_attrs: |
00085f1e | 590 | dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs); |
051fb70f BA |
591 | |
592 | return ret < 0 ? ret : 0; | |
593 | } | |
594 | ||
e7fd2522 BA |
595 | static bool q6v5_phdr_valid(const struct elf32_phdr *phdr) |
596 | { | |
597 | if (phdr->p_type != PT_LOAD) | |
598 | return false; | |
599 | ||
600 | if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) | |
601 | return false; | |
602 | ||
603 | if (!phdr->p_memsz) | |
604 | return false; | |
605 | ||
606 | return true; | |
607 | } | |
608 | ||
609 | static int q6v5_mpss_load(struct q6v5 *qproc) | |
051fb70f BA |
610 | { |
611 | const struct elf32_phdr *phdrs; | |
612 | const struct elf32_phdr *phdr; | |
e7fd2522 BA |
613 | const struct firmware *seg_fw; |
614 | const struct firmware *fw; | |
051fb70f | 615 | struct elf32_hdr *ehdr; |
e7fd2522 | 616 | phys_addr_t mpss_reloc; |
051fb70f | 617 | phys_addr_t boot_addr; |
e7fd2522 BA |
618 | phys_addr_t min_addr = (phys_addr_t)ULLONG_MAX; |
619 | phys_addr_t max_addr = 0; | |
620 | bool relocate = false; | |
621 | char seg_name[10]; | |
01625cc5 | 622 | ssize_t offset; |
94c90785 | 623 | size_t size = 0; |
e7fd2522 | 624 | void *ptr; |
051fb70f BA |
625 | int ret; |
626 | int i; | |
627 | ||
e7fd2522 BA |
628 | ret = request_firmware(&fw, "modem.mdt", qproc->dev); |
629 | if (ret < 0) { | |
630 | dev_err(qproc->dev, "unable to load modem.mdt\n"); | |
051fb70f BA |
631 | return ret; |
632 | } | |
633 | ||
e7fd2522 BA |
634 | /* Initialize the RMB validator */ |
635 | writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
636 | ||
637 | ret = q6v5_mpss_init_image(qproc, fw); | |
638 | if (ret) | |
639 | goto release_firmware; | |
051fb70f BA |
640 | |
641 | ehdr = (struct elf32_hdr *)fw->data; | |
642 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
e7fd2522 BA |
643 | |
644 | for (i = 0; i < ehdr->e_phnum; i++) { | |
051fb70f BA |
645 | phdr = &phdrs[i]; |
646 | ||
e7fd2522 | 647 | if (!q6v5_phdr_valid(phdr)) |
051fb70f BA |
648 | continue; |
649 | ||
e7fd2522 BA |
650 | if (phdr->p_flags & QCOM_MDT_RELOCATABLE) |
651 | relocate = true; | |
051fb70f | 652 | |
e7fd2522 BA |
653 | if (phdr->p_paddr < min_addr) |
654 | min_addr = phdr->p_paddr; | |
655 | ||
656 | if (phdr->p_paddr + phdr->p_memsz > max_addr) | |
657 | max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); | |
658 | } | |
659 | ||
660 | mpss_reloc = relocate ? min_addr : qproc->mpss_phys; | |
94c90785 | 661 | /* Load firmware segments */ |
e7fd2522 BA |
662 | for (i = 0; i < ehdr->e_phnum; i++) { |
663 | phdr = &phdrs[i]; | |
664 | ||
665 | if (!q6v5_phdr_valid(phdr)) | |
051fb70f BA |
666 | continue; |
667 | ||
e7fd2522 BA |
668 | offset = phdr->p_paddr - mpss_reloc; |
669 | if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) { | |
670 | dev_err(qproc->dev, "segment outside memory range\n"); | |
671 | ret = -EINVAL; | |
672 | goto release_firmware; | |
673 | } | |
674 | ||
675 | ptr = qproc->mpss_region + offset; | |
676 | ||
677 | if (phdr->p_filesz) { | |
678 | snprintf(seg_name, sizeof(seg_name), "modem.b%02d", i); | |
679 | ret = request_firmware(&seg_fw, seg_name, qproc->dev); | |
680 | if (ret) { | |
681 | dev_err(qproc->dev, "failed to load %s\n", seg_name); | |
682 | goto release_firmware; | |
683 | } | |
684 | ||
685 | memcpy(ptr, seg_fw->data, seg_fw->size); | |
686 | ||
687 | release_firmware(seg_fw); | |
688 | } | |
689 | ||
690 | if (phdr->p_memsz > phdr->p_filesz) { | |
691 | memset(ptr + phdr->p_filesz, 0, | |
692 | phdr->p_memsz - phdr->p_filesz); | |
693 | } | |
051fb70f | 694 | size += phdr->p_memsz; |
051fb70f BA |
695 | } |
696 | ||
6c5a9dc2 AKD |
697 | /* Transfer ownership of modem ddr region to q6 */ |
698 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, | |
699 | qproc->mpss_phys, qproc->mpss_size); | |
9f2a4342 BA |
700 | if (ret) { |
701 | dev_err(qproc->dev, | |
702 | "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1a5d5c59 CJ |
703 | ret = -EAGAIN; |
704 | goto release_firmware; | |
9f2a4342 | 705 | } |
6c5a9dc2 | 706 | |
94c90785 AKD |
707 | boot_addr = relocate ? qproc->mpss_phys : min_addr; |
708 | writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG); | |
709 | writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
710 | writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
711 | ||
72beb490 BA |
712 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000); |
713 | if (ret == -ETIMEDOUT) | |
714 | dev_err(qproc->dev, "MPSS authentication timed out\n"); | |
715 | else if (ret < 0) | |
716 | dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret); | |
717 | ||
051fb70f BA |
718 | release_firmware: |
719 | release_firmware(fw); | |
720 | ||
721 | return ret < 0 ? ret : 0; | |
722 | } | |
723 | ||
724 | static int q6v5_start(struct rproc *rproc) | |
725 | { | |
726 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
6c5a9dc2 | 727 | int xfermemop_ret; |
051fb70f BA |
728 | int ret; |
729 | ||
19f902b5 AKD |
730 | ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, |
731 | qproc->proxy_reg_count); | |
051fb70f | 732 | if (ret) { |
19f902b5 | 733 | dev_err(qproc->dev, "failed to enable proxy supplies\n"); |
051fb70f BA |
734 | return ret; |
735 | } | |
736 | ||
39b2410b AKD |
737 | ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, |
738 | qproc->proxy_clk_count); | |
739 | if (ret) { | |
740 | dev_err(qproc->dev, "failed to enable proxy clocks\n"); | |
19f902b5 AKD |
741 | goto disable_proxy_reg; |
742 | } | |
743 | ||
744 | ret = q6v5_regulator_enable(qproc, qproc->active_regs, | |
745 | qproc->active_reg_count); | |
746 | if (ret) { | |
747 | dev_err(qproc->dev, "failed to enable supplies\n"); | |
748 | goto disable_proxy_clk; | |
39b2410b | 749 | } |
051fb70f BA |
750 | ret = reset_control_deassert(qproc->mss_restart); |
751 | if (ret) { | |
752 | dev_err(qproc->dev, "failed to deassert mss restart\n"); | |
19f902b5 | 753 | goto disable_vdd; |
051fb70f BA |
754 | } |
755 | ||
39b2410b AKD |
756 | ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, |
757 | qproc->active_clk_count); | |
758 | if (ret) { | |
759 | dev_err(qproc->dev, "failed to enable clocks\n"); | |
051fb70f | 760 | goto assert_reset; |
39b2410b | 761 | } |
051fb70f | 762 | |
6c5a9dc2 AKD |
763 | /* Assign MBA image access in DDR to q6 */ |
764 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, | |
765 | qproc->mba_phys, | |
766 | qproc->mba_size); | |
9f2a4342 BA |
767 | if (xfermemop_ret) { |
768 | dev_err(qproc->dev, | |
769 | "assigning Q6 access to mba memory failed: %d\n", | |
770 | xfermemop_ret); | |
6c5a9dc2 | 771 | goto disable_active_clks; |
9f2a4342 | 772 | } |
6c5a9dc2 | 773 | |
051fb70f BA |
774 | writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); |
775 | ||
776 | ret = q6v5proc_reset(qproc); | |
777 | if (ret) | |
6c5a9dc2 | 778 | goto reclaim_mba; |
051fb70f BA |
779 | |
780 | ret = q6v5_rmb_mba_wait(qproc, 0, 5000); | |
781 | if (ret == -ETIMEDOUT) { | |
782 | dev_err(qproc->dev, "MBA boot timed out\n"); | |
783 | goto halt_axi_ports; | |
784 | } else if (ret != RMB_MBA_XPU_UNLOCKED && | |
785 | ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) { | |
786 | dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret); | |
787 | ret = -EINVAL; | |
788 | goto halt_axi_ports; | |
789 | } | |
790 | ||
791 | dev_info(qproc->dev, "MBA booted, loading mpss\n"); | |
792 | ||
793 | ret = q6v5_mpss_load(qproc); | |
794 | if (ret) | |
6c5a9dc2 | 795 | goto reclaim_mpss; |
051fb70f BA |
796 | |
797 | ret = wait_for_completion_timeout(&qproc->start_done, | |
798 | msecs_to_jiffies(5000)); | |
799 | if (ret == 0) { | |
800 | dev_err(qproc->dev, "start timed out\n"); | |
801 | ret = -ETIMEDOUT; | |
6c5a9dc2 | 802 | goto reclaim_mpss; |
051fb70f BA |
803 | } |
804 | ||
6c5a9dc2 AKD |
805 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, |
806 | qproc->mba_phys, | |
807 | qproc->mba_size); | |
808 | if (xfermemop_ret) | |
809 | dev_err(qproc->dev, | |
810 | "Failed to reclaim mba buffer system may become unstable\n"); | |
051fb70f BA |
811 | qproc->running = true; |
812 | ||
39b2410b AKD |
813 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, |
814 | qproc->proxy_clk_count); | |
19f902b5 AKD |
815 | q6v5_regulator_disable(qproc, qproc->proxy_regs, |
816 | qproc->proxy_reg_count); | |
051fb70f BA |
817 | |
818 | return 0; | |
819 | ||
6c5a9dc2 AKD |
820 | reclaim_mpss: |
821 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
822 | false, qproc->mpss_phys, | |
823 | qproc->mpss_size); | |
824 | WARN_ON(xfermemop_ret); | |
825 | ||
051fb70f BA |
826 | halt_axi_ports: |
827 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
828 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); | |
829 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); | |
6c5a9dc2 AKD |
830 | |
831 | reclaim_mba: | |
832 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, | |
833 | qproc->mba_phys, | |
834 | qproc->mba_size); | |
835 | if (xfermemop_ret) { | |
836 | dev_err(qproc->dev, | |
837 | "Failed to reclaim mba buffer, system may become unstable\n"); | |
838 | } | |
839 | ||
840 | disable_active_clks: | |
39b2410b AKD |
841 | q6v5_clk_disable(qproc->dev, qproc->active_clks, |
842 | qproc->active_clk_count); | |
6c5a9dc2 | 843 | |
051fb70f BA |
844 | assert_reset: |
845 | reset_control_assert(qproc->mss_restart); | |
19f902b5 AKD |
846 | disable_vdd: |
847 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
848 | qproc->active_reg_count); | |
39b2410b AKD |
849 | disable_proxy_clk: |
850 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
851 | qproc->proxy_clk_count); | |
19f902b5 AKD |
852 | disable_proxy_reg: |
853 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
854 | qproc->proxy_reg_count); | |
051fb70f BA |
855 | |
856 | return ret; | |
857 | } | |
858 | ||
859 | static int q6v5_stop(struct rproc *rproc) | |
860 | { | |
861 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
862 | int ret; | |
6c5a9dc2 | 863 | u32 val; |
051fb70f BA |
864 | |
865 | qproc->running = false; | |
866 | ||
867 | qcom_smem_state_update_bits(qproc->state, | |
868 | BIT(qproc->stop_bit), BIT(qproc->stop_bit)); | |
869 | ||
870 | ret = wait_for_completion_timeout(&qproc->stop_done, | |
871 | msecs_to_jiffies(5000)); | |
872 | if (ret == 0) | |
873 | dev_err(qproc->dev, "timed out on wait\n"); | |
874 | ||
875 | qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0); | |
876 | ||
877 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
878 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); | |
879 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); | |
9f058fa2 AKD |
880 | if (qproc->version == MSS_MSM8996) { |
881 | /* | |
882 | * To avoid high MX current during LPASS/MSS restart. | |
883 | */ | |
884 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
885 | val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | | |
886 | QDSP6v56_CLAMP_QMC_MEM; | |
887 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
888 | } | |
889 | ||
051fb70f | 890 | |
6c5a9dc2 AKD |
891 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, |
892 | qproc->mpss_phys, qproc->mpss_size); | |
893 | WARN_ON(ret); | |
894 | ||
051fb70f | 895 | reset_control_assert(qproc->mss_restart); |
39b2410b AKD |
896 | q6v5_clk_disable(qproc->dev, qproc->active_clks, |
897 | qproc->active_clk_count); | |
19f902b5 AKD |
898 | q6v5_regulator_disable(qproc, qproc->active_regs, |
899 | qproc->active_reg_count); | |
051fb70f BA |
900 | |
901 | return 0; | |
902 | } | |
903 | ||
904 | static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len) | |
905 | { | |
906 | struct q6v5 *qproc = rproc->priv; | |
907 | int offset; | |
908 | ||
909 | offset = da - qproc->mpss_reloc; | |
910 | if (offset < 0 || offset + len > qproc->mpss_size) | |
911 | return NULL; | |
912 | ||
913 | return qproc->mpss_region + offset; | |
914 | } | |
915 | ||
916 | static const struct rproc_ops q6v5_ops = { | |
917 | .start = q6v5_start, | |
918 | .stop = q6v5_stop, | |
919 | .da_to_va = q6v5_da_to_va, | |
0f21f9cc | 920 | .load = q6v5_load, |
051fb70f BA |
921 | }; |
922 | ||
923 | static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev) | |
924 | { | |
925 | struct q6v5 *qproc = dev; | |
926 | size_t len; | |
927 | char *msg; | |
928 | ||
929 | /* Sometimes the stop triggers a watchdog rather than a stop-ack */ | |
930 | if (!qproc->running) { | |
931 | complete(&qproc->stop_done); | |
932 | return IRQ_HANDLED; | |
933 | } | |
934 | ||
935 | msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len); | |
936 | if (!IS_ERR(msg) && len > 0 && msg[0]) | |
937 | dev_err(qproc->dev, "watchdog received: %s\n", msg); | |
938 | else | |
939 | dev_err(qproc->dev, "watchdog without message\n"); | |
940 | ||
941 | rproc_report_crash(qproc->rproc, RPROC_WATCHDOG); | |
942 | ||
051fb70f BA |
943 | return IRQ_HANDLED; |
944 | } | |
945 | ||
946 | static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev) | |
947 | { | |
948 | struct q6v5 *qproc = dev; | |
949 | size_t len; | |
950 | char *msg; | |
951 | ||
952 | msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len); | |
953 | if (!IS_ERR(msg) && len > 0 && msg[0]) | |
954 | dev_err(qproc->dev, "fatal error received: %s\n", msg); | |
955 | else | |
956 | dev_err(qproc->dev, "fatal error without message\n"); | |
957 | ||
958 | rproc_report_crash(qproc->rproc, RPROC_FATAL_ERROR); | |
959 | ||
051fb70f BA |
960 | return IRQ_HANDLED; |
961 | } | |
962 | ||
963 | static irqreturn_t q6v5_handover_interrupt(int irq, void *dev) | |
964 | { | |
965 | struct q6v5 *qproc = dev; | |
966 | ||
967 | complete(&qproc->start_done); | |
968 | return IRQ_HANDLED; | |
969 | } | |
970 | ||
971 | static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev) | |
972 | { | |
973 | struct q6v5 *qproc = dev; | |
974 | ||
975 | complete(&qproc->stop_done); | |
976 | return IRQ_HANDLED; | |
977 | } | |
978 | ||
979 | static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) | |
980 | { | |
981 | struct of_phandle_args args; | |
982 | struct resource *res; | |
983 | int ret; | |
984 | ||
985 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); | |
986 | qproc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
b1653f23 | 987 | if (IS_ERR(qproc->reg_base)) |
051fb70f | 988 | return PTR_ERR(qproc->reg_base); |
051fb70f BA |
989 | |
990 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); | |
991 | qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res); | |
b1653f23 | 992 | if (IS_ERR(qproc->rmb_base)) |
051fb70f | 993 | return PTR_ERR(qproc->rmb_base); |
051fb70f BA |
994 | |
995 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
996 | "qcom,halt-regs", 3, 0, &args); | |
997 | if (ret < 0) { | |
998 | dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); | |
999 | return -EINVAL; | |
1000 | } | |
1001 | ||
1002 | qproc->halt_map = syscon_node_to_regmap(args.np); | |
1003 | of_node_put(args.np); | |
1004 | if (IS_ERR(qproc->halt_map)) | |
1005 | return PTR_ERR(qproc->halt_map); | |
1006 | ||
1007 | qproc->halt_q6 = args.args[0]; | |
1008 | qproc->halt_modem = args.args[1]; | |
1009 | qproc->halt_nc = args.args[2]; | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
39b2410b AKD |
1014 | static int q6v5_init_clocks(struct device *dev, struct clk **clks, |
1015 | char **clk_names) | |
051fb70f | 1016 | { |
39b2410b | 1017 | int i; |
051fb70f | 1018 | |
39b2410b AKD |
1019 | if (!clk_names) |
1020 | return 0; | |
1021 | ||
1022 | for (i = 0; clk_names[i]; i++) { | |
1023 | clks[i] = devm_clk_get(dev, clk_names[i]); | |
1024 | if (IS_ERR(clks[i])) { | |
1025 | int rc = PTR_ERR(clks[i]); | |
051fb70f | 1026 | |
39b2410b AKD |
1027 | if (rc != -EPROBE_DEFER) |
1028 | dev_err(dev, "Failed to get %s clock\n", | |
1029 | clk_names[i]); | |
1030 | return rc; | |
1031 | } | |
051fb70f BA |
1032 | } |
1033 | ||
39b2410b | 1034 | return i; |
051fb70f BA |
1035 | } |
1036 | ||
1037 | static int q6v5_init_reset(struct q6v5 *qproc) | |
1038 | { | |
5acbf7e5 PZ |
1039 | qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, |
1040 | NULL); | |
051fb70f BA |
1041 | if (IS_ERR(qproc->mss_restart)) { |
1042 | dev_err(qproc->dev, "failed to acquire mss restart\n"); | |
1043 | return PTR_ERR(qproc->mss_restart); | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int q6v5_request_irq(struct q6v5 *qproc, | |
1050 | struct platform_device *pdev, | |
1051 | const char *name, | |
1052 | irq_handler_t thread_fn) | |
1053 | { | |
1054 | int ret; | |
1055 | ||
1056 | ret = platform_get_irq_byname(pdev, name); | |
1057 | if (ret < 0) { | |
1058 | dev_err(&pdev->dev, "no %s IRQ defined\n", name); | |
1059 | return ret; | |
1060 | } | |
1061 | ||
1062 | ret = devm_request_threaded_irq(&pdev->dev, ret, | |
1063 | NULL, thread_fn, | |
1064 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, | |
1065 | "q6v5", qproc); | |
1066 | if (ret) | |
1067 | dev_err(&pdev->dev, "request %s IRQ failed\n", name); | |
1068 | ||
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | static int q6v5_alloc_memory_region(struct q6v5 *qproc) | |
1073 | { | |
1074 | struct device_node *child; | |
1075 | struct device_node *node; | |
1076 | struct resource r; | |
1077 | int ret; | |
1078 | ||
1079 | child = of_get_child_by_name(qproc->dev->of_node, "mba"); | |
1080 | node = of_parse_phandle(child, "memory-region", 0); | |
1081 | ret = of_address_to_resource(node, 0, &r); | |
1082 | if (ret) { | |
1083 | dev_err(qproc->dev, "unable to resolve mba region\n"); | |
1084 | return ret; | |
1085 | } | |
1086 | ||
1087 | qproc->mba_phys = r.start; | |
1088 | qproc->mba_size = resource_size(&r); | |
1089 | qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size); | |
1090 | if (!qproc->mba_region) { | |
1091 | dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", | |
1092 | &r.start, qproc->mba_size); | |
1093 | return -EBUSY; | |
1094 | } | |
1095 | ||
1096 | child = of_get_child_by_name(qproc->dev->of_node, "mpss"); | |
1097 | node = of_parse_phandle(child, "memory-region", 0); | |
1098 | ret = of_address_to_resource(node, 0, &r); | |
1099 | if (ret) { | |
1100 | dev_err(qproc->dev, "unable to resolve mpss region\n"); | |
1101 | return ret; | |
1102 | } | |
1103 | ||
1104 | qproc->mpss_phys = qproc->mpss_reloc = r.start; | |
1105 | qproc->mpss_size = resource_size(&r); | |
1106 | qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size); | |
1107 | if (!qproc->mpss_region) { | |
1108 | dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", | |
1109 | &r.start, qproc->mpss_size); | |
1110 | return -EBUSY; | |
1111 | } | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | static int q6v5_probe(struct platform_device *pdev) | |
1117 | { | |
7a8ffe1f | 1118 | const struct rproc_hexagon_res *desc; |
051fb70f BA |
1119 | struct q6v5 *qproc; |
1120 | struct rproc *rproc; | |
1121 | int ret; | |
1122 | ||
7a8ffe1f AKD |
1123 | desc = of_device_get_match_data(&pdev->dev); |
1124 | if (!desc) | |
1125 | return -EINVAL; | |
1126 | ||
051fb70f | 1127 | rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops, |
7a8ffe1f | 1128 | desc->hexagon_mba_image, sizeof(*qproc)); |
051fb70f BA |
1129 | if (!rproc) { |
1130 | dev_err(&pdev->dev, "failed to allocate rproc\n"); | |
1131 | return -ENOMEM; | |
1132 | } | |
1133 | ||
051fb70f BA |
1134 | qproc = (struct q6v5 *)rproc->priv; |
1135 | qproc->dev = &pdev->dev; | |
1136 | qproc->rproc = rproc; | |
1137 | platform_set_drvdata(pdev, qproc); | |
1138 | ||
1139 | init_completion(&qproc->start_done); | |
1140 | init_completion(&qproc->stop_done); | |
1141 | ||
1142 | ret = q6v5_init_mem(qproc, pdev); | |
1143 | if (ret) | |
1144 | goto free_rproc; | |
1145 | ||
1146 | ret = q6v5_alloc_memory_region(qproc); | |
1147 | if (ret) | |
1148 | goto free_rproc; | |
1149 | ||
39b2410b AKD |
1150 | ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks, |
1151 | desc->proxy_clk_names); | |
1152 | if (ret < 0) { | |
1153 | dev_err(&pdev->dev, "Failed to get proxy clocks.\n"); | |
051fb70f | 1154 | goto free_rproc; |
39b2410b AKD |
1155 | } |
1156 | qproc->proxy_clk_count = ret; | |
1157 | ||
1158 | ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks, | |
1159 | desc->active_clk_names); | |
1160 | if (ret < 0) { | |
1161 | dev_err(&pdev->dev, "Failed to get active clocks.\n"); | |
1162 | goto free_rproc; | |
1163 | } | |
1164 | qproc->active_clk_count = ret; | |
051fb70f | 1165 | |
19f902b5 AKD |
1166 | ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs, |
1167 | desc->proxy_supply); | |
1168 | if (ret < 0) { | |
1169 | dev_err(&pdev->dev, "Failed to get proxy regulators.\n"); | |
051fb70f | 1170 | goto free_rproc; |
19f902b5 AKD |
1171 | } |
1172 | qproc->proxy_reg_count = ret; | |
1173 | ||
1174 | ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs, | |
1175 | desc->active_supply); | |
1176 | if (ret < 0) { | |
1177 | dev_err(&pdev->dev, "Failed to get active regulators.\n"); | |
1178 | goto free_rproc; | |
1179 | } | |
1180 | qproc->active_reg_count = ret; | |
051fb70f BA |
1181 | |
1182 | ret = q6v5_init_reset(qproc); | |
1183 | if (ret) | |
1184 | goto free_rproc; | |
1185 | ||
9f058fa2 | 1186 | qproc->version = desc->version; |
6c5a9dc2 | 1187 | qproc->need_mem_protection = desc->need_mem_protection; |
051fb70f BA |
1188 | ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt); |
1189 | if (ret < 0) | |
1190 | goto free_rproc; | |
1191 | ||
1192 | ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt); | |
1193 | if (ret < 0) | |
1194 | goto free_rproc; | |
1195 | ||
1196 | ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt); | |
1197 | if (ret < 0) | |
1198 | goto free_rproc; | |
1199 | ||
1200 | ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt); | |
1201 | if (ret < 0) | |
1202 | goto free_rproc; | |
1203 | ||
1204 | qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit); | |
4e968d9e WY |
1205 | if (IS_ERR(qproc->state)) { |
1206 | ret = PTR_ERR(qproc->state); | |
051fb70f | 1207 | goto free_rproc; |
4e968d9e | 1208 | } |
6c5a9dc2 AKD |
1209 | qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); |
1210 | qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); | |
4b48921a | 1211 | qcom_add_smd_subdev(rproc, &qproc->smd_subdev); |
1e140df0 | 1212 | qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss"); |
1fb82ee8 | 1213 | qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); |
4b48921a | 1214 | |
051fb70f BA |
1215 | ret = rproc_add(rproc); |
1216 | if (ret) | |
1217 | goto free_rproc; | |
1218 | ||
1219 | return 0; | |
1220 | ||
1221 | free_rproc: | |
433c0e04 | 1222 | rproc_free(rproc); |
051fb70f BA |
1223 | |
1224 | return ret; | |
1225 | } | |
1226 | ||
1227 | static int q6v5_remove(struct platform_device *pdev) | |
1228 | { | |
1229 | struct q6v5 *qproc = platform_get_drvdata(pdev); | |
1230 | ||
1231 | rproc_del(qproc->rproc); | |
4b48921a | 1232 | |
1fb82ee8 | 1233 | qcom_remove_sysmon_subdev(qproc->sysmon); |
4b48921a | 1234 | qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev); |
1e140df0 | 1235 | qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev); |
433c0e04 | 1236 | rproc_free(qproc->rproc); |
051fb70f BA |
1237 | |
1238 | return 0; | |
1239 | } | |
1240 | ||
9f058fa2 AKD |
1241 | static const struct rproc_hexagon_res msm8996_mss = { |
1242 | .hexagon_mba_image = "mba.mbn", | |
1243 | .proxy_clk_names = (char*[]){ | |
1244 | "xo", | |
1245 | "pnoc", | |
1246 | NULL | |
1247 | }, | |
1248 | .active_clk_names = (char*[]){ | |
1249 | "iface", | |
1250 | "bus", | |
1251 | "mem", | |
1252 | "gpll0_mss_clk", | |
1253 | NULL | |
1254 | }, | |
1255 | .need_mem_protection = true, | |
1256 | .version = MSS_MSM8996, | |
1257 | }; | |
1258 | ||
7a8ffe1f AKD |
1259 | static const struct rproc_hexagon_res msm8916_mss = { |
1260 | .hexagon_mba_image = "mba.mbn", | |
19f902b5 AKD |
1261 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
1262 | { | |
1263 | .supply = "mx", | |
1264 | .uV = 1050000, | |
1265 | }, | |
1266 | { | |
1267 | .supply = "cx", | |
1268 | .uA = 100000, | |
1269 | }, | |
1270 | { | |
1271 | .supply = "pll", | |
1272 | .uA = 100000, | |
1273 | }, | |
1274 | {} | |
1275 | }, | |
39b2410b AKD |
1276 | .proxy_clk_names = (char*[]){ |
1277 | "xo", | |
1278 | NULL | |
1279 | }, | |
1280 | .active_clk_names = (char*[]){ | |
1281 | "iface", | |
1282 | "bus", | |
1283 | "mem", | |
1284 | NULL | |
1285 | }, | |
6c5a9dc2 | 1286 | .need_mem_protection = false, |
9f058fa2 | 1287 | .version = MSS_MSM8916, |
7a8ffe1f AKD |
1288 | }; |
1289 | ||
1290 | static const struct rproc_hexagon_res msm8974_mss = { | |
1291 | .hexagon_mba_image = "mba.b00", | |
19f902b5 AKD |
1292 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
1293 | { | |
1294 | .supply = "mx", | |
1295 | .uV = 1050000, | |
1296 | }, | |
1297 | { | |
1298 | .supply = "cx", | |
1299 | .uA = 100000, | |
1300 | }, | |
1301 | { | |
1302 | .supply = "pll", | |
1303 | .uA = 100000, | |
1304 | }, | |
1305 | {} | |
1306 | }, | |
1307 | .active_supply = (struct qcom_mss_reg_res[]) { | |
1308 | { | |
1309 | .supply = "mss", | |
1310 | .uV = 1050000, | |
1311 | .uA = 100000, | |
1312 | }, | |
1313 | {} | |
1314 | }, | |
39b2410b AKD |
1315 | .proxy_clk_names = (char*[]){ |
1316 | "xo", | |
1317 | NULL | |
1318 | }, | |
1319 | .active_clk_names = (char*[]){ | |
1320 | "iface", | |
1321 | "bus", | |
1322 | "mem", | |
1323 | NULL | |
1324 | }, | |
6c5a9dc2 | 1325 | .need_mem_protection = false, |
9f058fa2 | 1326 | .version = MSS_MSM8974, |
7a8ffe1f AKD |
1327 | }; |
1328 | ||
051fb70f | 1329 | static const struct of_device_id q6v5_of_match[] = { |
7a8ffe1f AKD |
1330 | { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, |
1331 | { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, | |
1332 | { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, | |
9f058fa2 | 1333 | { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, |
051fb70f BA |
1334 | { }, |
1335 | }; | |
3227c876 | 1336 | MODULE_DEVICE_TABLE(of, q6v5_of_match); |
051fb70f BA |
1337 | |
1338 | static struct platform_driver q6v5_driver = { | |
1339 | .probe = q6v5_probe, | |
1340 | .remove = q6v5_remove, | |
1341 | .driver = { | |
1342 | .name = "qcom-q6v5-pil", | |
1343 | .of_match_table = q6v5_of_match, | |
1344 | }, | |
1345 | }; | |
1346 | module_platform_driver(q6v5_driver); | |
1347 | ||
1348 | MODULE_DESCRIPTION("Peripheral Image Loader for Hexagon"); | |
1349 | MODULE_LICENSE("GPL v2"); |