[mirror_ubuntu-hirsute-kernel.git] / drivers / remoteproc / qcom_q6v5_wcss.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016-2018 Linaro Ltd.
 * Copyright (C) 2014 Sony Mobile Communications AB
 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
 */
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/soc/qcom/mdt_loader.h>
#include "qcom_common.h"
#include "qcom_pil_info.h"
#include "qcom_q6v5.h"

#define WCSS_CRASH_REASON		421

/* Q6SS Register Offsets */
#define Q6SS_RESET_REG		0x014
#define Q6SS_GFMUX_CTL_REG		0x020
#define Q6SS_PWR_CTL_REG		0x030
#define Q6SS_MEM_PWR_CTL		0x0B0

/* AXI Halt Register Offsets */
#define AXI_HALTREQ_REG			0x0
#define AXI_HALTACK_REG			0x4
#define AXI_IDLE_REG			0x8

#define HALT_ACK_TIMEOUT_MS		100

/* Q6SS_RESET */
#define Q6SS_STOP_CORE			BIT(0)
#define Q6SS_CORE_ARES			BIT(1)
#define Q6SS_BUS_ARES_ENABLE		BIT(2)

/* Q6SS_GFMUX_CTL */
#define Q6SS_CLK_ENABLE			BIT(1)

/* Q6SS_PWR_CTL */
#define Q6SS_L2DATA_STBY_N		BIT(18)
#define Q6SS_SLP_RET_N			BIT(19)
#define Q6SS_CLAMP_IO			BIT(20)
#define QDSS_BHS_ON			BIT(21)

/* Q6SS parameters */
#define Q6SS_LDO_BYP		BIT(25)
#define Q6SS_BHS_ON		BIT(24)
#define Q6SS_CLAMP_WL		BIT(21)
#define Q6SS_CLAMP_QMC_MEM		BIT(22)
#define HALT_CHECK_MAX_LOOPS		200
#define Q6SS_XO_CBCR		GENMASK(5, 3)

/* Q6SS config/status registers */
#define TCSR_GLOBAL_CFG0	0x0
#define TCSR_GLOBAL_CFG1	0x4
#define SSCAON_CONFIG		0x8
#define SSCAON_STATUS		0xc
#define Q6SS_BHS_STATUS		0x78
#define Q6SS_RST_EVB		0x10

#define BHS_EN_REST_ACK		BIT(0)
#define SSCAON_ENABLE		BIT(13)
#define SSCAON_BUS_EN		BIT(15)
#define SSCAON_BUS_MUX_MASK	GENMASK(18, 16)

#define MEM_BANKS		19
#define TCSR_WCSS_CLK_MASK	0x1F
#define TCSR_WCSS_CLK_ENABLE	0x14

struct q6v5_wcss {
	struct device *dev;

	void __iomem *reg_base;
	void __iomem *rmb_base;

	struct regmap *halt_map;
	u32 halt_q6;
	u32 halt_wcss;
	u32 halt_nc;

	struct reset_control *wcss_aon_reset;
	struct reset_control *wcss_reset;
	struct reset_control *wcss_q6_reset;

	struct qcom_q6v5 q6v5;

	phys_addr_t mem_phys;
	phys_addr_t mem_reloc;
	void *mem_region;
	size_t mem_size;

	struct qcom_rproc_glink glink_subdev;
	struct qcom_rproc_ssr ssr_subdev;
};

static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
{
	int ret;
	u32 val;
	int i;

	/* Assert resets, stop core */
	val = readl(wcss->reg_base + Q6SS_RESET_REG);
	val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
	writel(val, wcss->reg_base + Q6SS_RESET_REG);

	/* BHS require xo cbcr to be enabled */
	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
	val |= 0x1;
	writel(val, wcss->reg_base + Q6SS_XO_CBCR);

	/* Read CLKOFF bit to go low indicating CLK is enabled */
	ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
				 val, !(val & BIT(31)), 1,
				 HALT_CHECK_MAX_LOOPS);
	if (ret) {
		dev_err(wcss->dev,
			"xo cbcr enabling timed out (rc:%d)\n", ret);
		return ret;
	}
	/* Enable power block headswitch and wait for it to stabilize */
	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	val |= Q6SS_BHS_ON;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	udelay(1);

	/* Put LDO in bypass mode */
	val |= Q6SS_LDO_BYP;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* Deassert Q6 compiler memory clamp */
	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	val &= ~Q6SS_CLAMP_QMC_MEM;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* Deassert memory peripheral sleep and L2 memory standby */
	val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* Turn on L1, L2, ETB and JU memories 1 at a time */
	val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
	for (i = MEM_BANKS; i >= 0; i--) {
		val |= BIT(i);
		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
		/*
		 * Read back value to ensure the write is done then
		 * wait for 1us for both memory peripheral and data
		 * array to turn on.
		 */
		val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
		udelay(1);
	}
	/* Remove word line clamp */
	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	val &= ~Q6SS_CLAMP_WL;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* Remove IO clamp */
	val &= ~Q6SS_CLAMP_IO;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* Bring core out of reset */
	val = readl(wcss->reg_base + Q6SS_RESET_REG);
	val &= ~Q6SS_CORE_ARES;
	writel(val, wcss->reg_base + Q6SS_RESET_REG);

	/* Turn on core clock */
	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
	val |= Q6SS_CLK_ENABLE;
	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);

	/* Start core execution */
	val = readl(wcss->reg_base + Q6SS_RESET_REG);
	val &= ~Q6SS_STOP_CORE;
	writel(val, wcss->reg_base + Q6SS_RESET_REG);

	return 0;
}

static int q6v5_wcss_start(struct rproc *rproc)
{
	struct q6v5_wcss *wcss = rproc->priv;
	int ret;

	qcom_q6v5_prepare(&wcss->q6v5);

	/* Release Q6 and WCSS reset */
	ret = reset_control_deassert(wcss->wcss_reset);
	if (ret) {
		dev_err(wcss->dev, "wcss_reset failed\n");
		return ret;
	}

	ret = reset_control_deassert(wcss->wcss_q6_reset);
	if (ret) {
		dev_err(wcss->dev, "wcss_q6_reset failed\n");
		goto wcss_reset;
	}

	/* Lithium configuration - clock gating and bus arbitration */
	ret = regmap_update_bits(wcss->halt_map,
				 wcss->halt_nc + TCSR_GLOBAL_CFG0,
				 TCSR_WCSS_CLK_MASK,
				 TCSR_WCSS_CLK_ENABLE);
	if (ret)
		goto wcss_q6_reset;

	ret = regmap_update_bits(wcss->halt_map,
				 wcss->halt_nc + TCSR_GLOBAL_CFG1,
				 1, 0);
	if (ret)
		goto wcss_q6_reset;

	/* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);

	ret = q6v5_wcss_reset(wcss);
	if (ret)
		goto wcss_q6_reset;

	ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
	if (ret == -ETIMEDOUT)
		dev_err(wcss->dev, "start timed out\n");

	return ret;

wcss_q6_reset:
	reset_control_assert(wcss->wcss_q6_reset);

wcss_reset:
	reset_control_assert(wcss->wcss_reset);

	return ret;
}

static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
				    struct regmap *halt_map,
				    u32 offset)
{
	unsigned long timeout;
	unsigned int val;
	int ret;

	/* Check if we're already idle */
	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
	if (!ret && val)
		return;

	/* Assert halt request */
	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);

	/* Wait for halt */
	timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
	for (;;) {
		ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
		if (ret || val || time_after(jiffies, timeout))
			break;

		msleep(1);
	}

	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
	if (ret || !val)
		dev_err(wcss->dev, "port failed halt\n");

	/* Clear halt request (port will remain halted until reset) */
	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
}

static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
{
	int ret;
	u32 val;

	/* 1 - Assert WCSS/Q6 HALTREQ */
	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);

	/* 2 - Enable WCSSAON_CONFIG */
	val = readl(wcss->rmb_base + SSCAON_CONFIG);
	val |= SSCAON_ENABLE;
	writel(val, wcss->rmb_base + SSCAON_CONFIG);

	/* 3 - Set SSCAON_CONFIG */
	val |= SSCAON_BUS_EN;
	val &= ~SSCAON_BUS_MUX_MASK;
	writel(val, wcss->rmb_base + SSCAON_CONFIG);

	/* 4 - SSCAON_CONFIG 1 */
	val |= BIT(1);
	writel(val, wcss->rmb_base + SSCAON_CONFIG);

	/* 5 - wait for SSCAON_STATUS */
	ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS,
				 val, (val & 0xffff) == 0x400, 1000,
				 HALT_CHECK_MAX_LOOPS);
	if (ret) {
		dev_err(wcss->dev,
			"can't get SSCAON_STATUS rc:%d)\n", ret);
		return ret;
	}

	/* 6 - De-assert WCSS_AON reset */
	reset_control_assert(wcss->wcss_aon_reset);

	/* 7 - Disable WCSSAON_CONFIG 13 */
	val = readl(wcss->rmb_base + SSCAON_CONFIG);
	val &= ~SSCAON_ENABLE;
	writel(val, wcss->rmb_base + SSCAON_CONFIG);

	/* 8 - De-assert WCSS/Q6 HALTREQ */
	reset_control_assert(wcss->wcss_reset);

	return 0;
}

static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
{
	int ret;
	u32 val;
	int i;

	/* 1 - Halt Q6 bus interface */
	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6);

	/* 2 - Disable Q6 Core clock */
	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
	val &= ~Q6SS_CLK_ENABLE;
	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);

	/* 3 - Clamp I/O */
	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	val |= Q6SS_CLAMP_IO;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* 4 - Clamp WL */
	val |= QDSS_BHS_ON;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* 5 - Clear Erase standby */
	val &= ~Q6SS_L2DATA_STBY_N;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* 6 - Clear Sleep RTN */
	val &= ~Q6SS_SLP_RET_N;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* 7 - turn off Q6 memory foot/head switch one bank at a time */
	for (i = 0; i < 20; i++) {
		val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
		val &= ~BIT(i);
		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
		mdelay(1);
	}

	/* 8 - Assert QMC memory RTN */
	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	val |= Q6SS_CLAMP_QMC_MEM;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);

	/* 9 - Turn off BHS */
	val &= ~Q6SS_BHS_ON;
	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	udelay(1);

	/* 10 - Wait till BHS Reset is done */
	ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,
				 val, !(val & BHS_EN_REST_ACK), 1000,
				 HALT_CHECK_MAX_LOOPS);
	if (ret) {
		dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret);
		return ret;
	}

	/* 11 -  Assert WCSS reset */
	reset_control_assert(wcss->wcss_reset);

	/* 12 - Assert Q6 reset */
	reset_control_assert(wcss->wcss_q6_reset);

	return 0;
}

static int q6v5_wcss_stop(struct rproc *rproc)
{
	struct q6v5_wcss *wcss = rproc->priv;
	int ret;

	/* WCSS powerdown */
	ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
	if (ret == -ETIMEDOUT) {
		dev_err(wcss->dev, "timed out on wait\n");
		return ret;
	}

	ret = q6v5_wcss_powerdown(wcss);
	if (ret)
		return ret;

	/* Q6 Power down */
	ret = q6v5_q6_powerdown(wcss);
	if (ret)
		return ret;

	qcom_q6v5_unprepare(&wcss->q6v5);

	return 0;
}

static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len)
{
	struct q6v5_wcss *wcss = rproc->priv;
	int offset;

	offset = da - wcss->mem_reloc;
	if (offset < 0 || offset + len > wcss->mem_size)
		return NULL;

	return wcss->mem_region + offset;
}

static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
{
	struct q6v5_wcss *wcss = rproc->priv;
	int ret;

	ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
				    0, wcss->mem_region, wcss->mem_phys,
				    wcss->mem_size, &wcss->mem_reloc);
	if (ret)
		return ret;

	qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size);

	return ret;
}

static const struct rproc_ops q6v5_wcss_ops = {
	.start = q6v5_wcss_start,
	.stop = q6v5_wcss_stop,
	.da_to_va = q6v5_wcss_da_to_va,
	.load = q6v5_wcss_load,
	.get_boot_addr = rproc_elf_get_boot_addr,
};

static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
{
	struct device *dev = wcss->dev;

	wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
	if (IS_ERR(wcss->wcss_aon_reset)) {
		dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n");
		return PTR_ERR(wcss->wcss_aon_reset);
	}

	wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
	if (IS_ERR(wcss->wcss_reset)) {
		dev_err(wcss->dev, "unable to acquire wcss_reset\n");
		return PTR_ERR(wcss->wcss_reset);
	}

	wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
	if (IS_ERR(wcss->wcss_q6_reset)) {
		dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
		return PTR_ERR(wcss->wcss_q6_reset);
	}

	return 0;
}

static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
			       struct platform_device *pdev)
{
	struct of_phandle_args args;
	struct resource *res;
	int ret;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
	wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wcss->reg_base))
		return PTR_ERR(wcss->reg_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
	wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wcss->rmb_base))
		return PTR_ERR(wcss->rmb_base);

	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
					       "qcom,halt-regs", 3, 0, &args);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
		return -EINVAL;
	}

	wcss->halt_map = syscon_node_to_regmap(args.np);
	of_node_put(args.np);
	if (IS_ERR(wcss->halt_map))
		return PTR_ERR(wcss->halt_map);

	wcss->halt_q6 = args.args[0];
	wcss->halt_wcss = args.args[1];
	wcss->halt_nc = args.args[2];

	return 0;
}

static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
{
	struct reserved_mem *rmem = NULL;
	struct device_node *node;
	struct device *dev = wcss->dev;

	node = of_parse_phandle(dev->of_node, "memory-region", 0);
	if (node)
		rmem = of_reserved_mem_lookup(node);
	of_node_put(node);

	if (!rmem) {
		dev_err(dev, "unable to acquire memory-region\n");
		return -EINVAL;
	}

	wcss->mem_phys = rmem->base;
	wcss->mem_reloc = rmem->base;
	wcss->mem_size = rmem->size;
	wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size);
	if (!wcss->mem_region) {
		dev_err(dev, "unable to map memory region: %pa+%pa\n",
			&rmem->base, &rmem->size);
		return -EBUSY;
	}

	return 0;
}

static int q6v5_wcss_probe(struct platform_device *pdev)
{
	struct q6v5_wcss *wcss;
	struct rproc *rproc;
	int ret;

	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops,
			    "IPQ8074/q6_fw.mdt", sizeof(*wcss));
	if (!rproc) {
		dev_err(&pdev->dev, "failed to allocate rproc\n");
		return -ENOMEM;
	}

	wcss = rproc->priv;
	wcss->dev = &pdev->dev;

	ret = q6v5_wcss_init_mmio(wcss, pdev);
	if (ret)
		goto free_rproc;

	ret = q6v5_alloc_memory_region(wcss);
	if (ret)
		goto free_rproc;

	ret = q6v5_wcss_init_reset(wcss);
	if (ret)
		goto free_rproc;

	ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
	if (ret)
		goto free_rproc;

	qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
	qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");

	ret = rproc_add(rproc);
	if (ret)
		goto free_rproc;

	platform_set_drvdata(pdev, rproc);

	return 0;

free_rproc:
	rproc_free(rproc);

	return ret;
}

static int q6v5_wcss_remove(struct platform_device *pdev)
{
	struct rproc *rproc = platform_get_drvdata(pdev);

	rproc_del(rproc);
	rproc_free(rproc);

	return 0;
}

static const struct of_device_id q6v5_wcss_of_match[] = {
	{ .compatible = "qcom,ipq8074-wcss-pil" },
	{ },
};
MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);

static struct platform_driver q6v5_wcss_driver = {
	.probe = q6v5_wcss_probe,
	.remove = q6v5_wcss_remove,
	.driver = {
		.name = "qcom-q6v5-wcss-pil",
		.of_match_table = q6v5_wcss_of_match,
	},
};
module_platform_driver(q6v5_wcss_driver);

MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3a3d4163 S	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2016-2018 Linaro Ltd.
	4	* Copyright (C) 2014 Sony Mobile Communications AB
	5	* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
	6	*/
	7	#include <linux/iopoll.h>
	8	#include <linux/kernel.h>
	9	#include <linux/mfd/syscon.h>
	10	#include <linux/module.h>
	11	#include <linux/of_reserved_mem.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/regmap.h>
	14	#include <linux/reset.h>
	15	#include <linux/soc/qcom/mdt_loader.h>
	16	#include "qcom_common.h"
d4c78d21	17	#include "qcom_pil_info.h"
3a3d4163 S	18	#include "qcom_q6v5.h"
	19
	20	#define WCSS_CRASH_REASON 421
	21
	22	/* Q6SS Register Offsets */
	23	#define Q6SS_RESET_REG 0x014
	24	#define Q6SS_GFMUX_CTL_REG 0x020
	25	#define Q6SS_PWR_CTL_REG 0x030
	26	#define Q6SS_MEM_PWR_CTL 0x0B0
	27
	28	/* AXI Halt Register Offsets */
	29	#define AXI_HALTREQ_REG 0x0
	30	#define AXI_HALTACK_REG 0x4
	31	#define AXI_IDLE_REG 0x8
	32
	33	#define HALT_ACK_TIMEOUT_MS 100
	34
	35	/* Q6SS_RESET */
	36	#define Q6SS_STOP_CORE BIT(0)
	37	#define Q6SS_CORE_ARES BIT(1)
	38	#define Q6SS_BUS_ARES_ENABLE BIT(2)
	39
	40	/* Q6SS_GFMUX_CTL */
	41	#define Q6SS_CLK_ENABLE BIT(1)
	42
	43	/* Q6SS_PWR_CTL */
	44	#define Q6SS_L2DATA_STBY_N BIT(18)
	45	#define Q6SS_SLP_RET_N BIT(19)
	46	#define Q6SS_CLAMP_IO BIT(20)
	47	#define QDSS_BHS_ON BIT(21)
	48
	49	/* Q6SS parameters */
	50	#define Q6SS_LDO_BYP BIT(25)
	51	#define Q6SS_BHS_ON BIT(24)
	52	#define Q6SS_CLAMP_WL BIT(21)
	53	#define Q6SS_CLAMP_QMC_MEM BIT(22)
	54	#define HALT_CHECK_MAX_LOOPS 200
	55	#define Q6SS_XO_CBCR GENMASK(5, 3)
	56
	57	/* Q6SS config/status registers */
	58	#define TCSR_GLOBAL_CFG0 0x0
	59	#define TCSR_GLOBAL_CFG1 0x4
	60	#define SSCAON_CONFIG 0x8
	61	#define SSCAON_STATUS 0xc
	62	#define Q6SS_BHS_STATUS 0x78
	63	#define Q6SS_RST_EVB 0x10
	64
	65	#define BHS_EN_REST_ACK BIT(0)
	66	#define SSCAON_ENABLE BIT(13)
	67	#define SSCAON_BUS_EN BIT(15)
	68	#define SSCAON_BUS_MUX_MASK GENMASK(18, 16)
	69
	70	#define MEM_BANKS 19
	71	#define TCSR_WCSS_CLK_MASK 0x1F
	72	#define TCSR_WCSS_CLK_ENABLE 0x14
	73
	74	struct q6v5_wcss {
	75	struct device *dev;
	76
	77	void __iomem *reg_base;
	78	void __iomem *rmb_base;
	79
	80	struct regmap *halt_map;
	81	u32 halt_q6;
82	u32 halt_wcss;
83	u32 halt_nc;
84
85	struct reset_control *wcss_aon_reset;
86	struct reset_control *wcss_reset;
87	struct reset_control *wcss_q6_reset;
88
89	struct qcom_q6v5 q6v5;
90
91	phys_addr_t mem_phys;
92	phys_addr_t mem_reloc;
93	void *mem_region;
94	size_t mem_size;
8a226e2c SM	95
	96	struct qcom_rproc_glink glink_subdev;
	97	struct qcom_rproc_ssr ssr_subdev;
3a3d4163 S	98	};
	99
	100	static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
	101	{
	102	int ret;
	103	u32 val;
	104	int i;
	105
	106	/* Assert resets, stop core */
	107	val = readl(wcss->reg_base + Q6SS_RESET_REG);
	108	val \|= Q6SS_CORE_ARES \| Q6SS_BUS_ARES_ENABLE \| Q6SS_STOP_CORE;
	109	writel(val, wcss->reg_base + Q6SS_RESET_REG);
	110
	111	/* BHS require xo cbcr to be enabled */
	112	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
	113	val \|= 0x1;
	114	writel(val, wcss->reg_base + Q6SS_XO_CBCR);
	115
	116	/* Read CLKOFF bit to go low indicating CLK is enabled */
	117	ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
	118	val, !(val & BIT(31)), 1,
	119	HALT_CHECK_MAX_LOOPS);
	120	if (ret) {
	121	dev_err(wcss->dev,
	122	"xo cbcr enabling timed out (rc:%d)\n", ret);
	123	return ret;
	124	}
	125	/* Enable power block headswitch and wait for it to stabilize */
	126	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	127	val \|= Q6SS_BHS_ON;
	128	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	129	udelay(1);
	130
	131	/* Put LDO in bypass mode */
	132	val \|= Q6SS_LDO_BYP;
	133	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	134
	135	/* Deassert Q6 compiler memory clamp */
	136	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	137	val &= ~Q6SS_CLAMP_QMC_MEM;
	138	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	139
	140	/* Deassert memory peripheral sleep and L2 memory standby */
	141	val \|= Q6SS_L2DATA_STBY_N \| Q6SS_SLP_RET_N;
	142	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	143
	144	/* Turn on L1, L2, ETB and JU memories 1 at a time */
	145	val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
	146	for (i = MEM_BANKS; i >= 0; i--) {
	147	val \|= BIT(i);
	148	writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
	149	/*
	150	* Read back value to ensure the write is done then
	151	* wait for 1us for both memory peripheral and data
	152	* array to turn on.
	153	*/
	154	val \|= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
	155	udelay(1);
	156	}
	157	/* Remove word line clamp */
	158	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
	159	val &= ~Q6SS_CLAMP_WL;
	160	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
	161
162	/* Remove IO clamp */
163	val &= ~Q6SS_CLAMP_IO;
164	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
165
166	/* Bring core out of reset */
167	val = readl(wcss->reg_base + Q6SS_RESET_REG);
168	val &= ~Q6SS_CORE_ARES;
169	writel(val, wcss->reg_base + Q6SS_RESET_REG);
170
171	/* Turn on core clock */
172	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
173	val \|= Q6SS_CLK_ENABLE;
174	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
175
176	/* Start core execution */
177	val = readl(wcss->reg_base + Q6SS_RESET_REG);
178	val &= ~Q6SS_STOP_CORE;
179	writel(val, wcss->reg_base + Q6SS_RESET_REG);
180
181	return 0;
182	}
183
184	static int q6v5_wcss_start(struct rproc *rproc)
185	{
186	struct q6v5_wcss *wcss = rproc->priv;
187	int ret;
188
189	qcom_q6v5_prepare(&wcss->q6v5);
190
191	/* Release Q6 and WCSS reset */
192	ret = reset_control_deassert(wcss->wcss_reset);
193	if (ret) {
194	dev_err(wcss->dev, "wcss_reset failed\n");
195	return ret;
196	}
197
198	ret = reset_control_deassert(wcss->wcss_q6_reset);
199	if (ret) {
200	dev_err(wcss->dev, "wcss_q6_reset failed\n");
201	goto wcss_reset;
202	}
203
204	/* Lithium configuration - clock gating and bus arbitration */
205	ret = regmap_update_bits(wcss->halt_map,
206	wcss->halt_nc + TCSR_GLOBAL_CFG0,
207	TCSR_WCSS_CLK_MASK,
208	TCSR_WCSS_CLK_ENABLE);
209	if (ret)
210	goto wcss_q6_reset;
211
212	ret = regmap_update_bits(wcss->halt_map,
213	wcss->halt_nc + TCSR_GLOBAL_CFG1,
214	1, 0);
215	if (ret)
216	goto wcss_q6_reset;
217
218	/* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
219	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
220
221	ret = q6v5_wcss_reset(wcss);
222	if (ret)
223	goto wcss_q6_reset;
224
225	ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
226	if (ret == -ETIMEDOUT)
227	dev_err(wcss->dev, "start timed out\n");
228
229	return ret;
230
231	wcss_q6_reset:
232	reset_control_assert(wcss->wcss_q6_reset);
233
234	wcss_reset:
235	reset_control_assert(wcss->wcss_reset);
236
237	return ret;
238	}
239
240	static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
241	struct regmap *halt_map,
242	u32 offset)
243	{
244	unsigned long timeout;
245	unsigned int val;
246	int ret;
247
248	/* Check if we're already idle */
249	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
250	if (!ret && val)
251	return;
252
253	/* Assert halt request */
254	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
255
256	/* Wait for halt */
257	timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
258	for (;;) {
259	ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
260	if (ret \|\| val \|\| time_after(jiffies, timeout))
261	break;
262
263	msleep(1);
264	}
265
266	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
267	if (ret \|\| !val)
268	dev_err(wcss->dev, "port failed halt\n");
269
270	/* Clear halt request (port will remain halted until reset) */
271	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
272	}
273
274	static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
275	{
276	int ret;
277	u32 val;
278
279	/* 1 - Assert WCSS/Q6 HALTREQ */
280	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
281
282	/* 2 - Enable WCSSAON_CONFIG */
283	val = readl(wcss->rmb_base + SSCAON_CONFIG);
284	val \|= SSCAON_ENABLE;
285	writel(val, wcss->rmb_base + SSCAON_CONFIG);
286
287	/* 3 - Set SSCAON_CONFIG */
288	val \|= SSCAON_BUS_EN;
289	val &= ~SSCAON_BUS_MUX_MASK;
290	writel(val, wcss->rmb_base + SSCAON_CONFIG);
291
292	/* 4 - SSCAON_CONFIG 1 */
293	val \|= BIT(1);
294	writel(val, wcss->rmb_base + SSCAON_CONFIG);
295
296	/* 5 - wait for SSCAON_STATUS */
297	ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS,
298	val, (val & 0xffff) == 0x400, 1000,
299	HALT_CHECK_MAX_LOOPS);
300	if (ret) {
301	dev_err(wcss->dev,
302	"can't get SSCAON_STATUS rc:%d)\n", ret);
303	return ret;
304	}
305
306	/* 6 - De-assert WCSS_AON reset */
307	reset_control_assert(wcss->wcss_aon_reset);
308
309	/* 7 - Disable WCSSAON_CONFIG 13 */
310	val = readl(wcss->rmb_base + SSCAON_CONFIG);
311	val &= ~SSCAON_ENABLE;
312	writel(val, wcss->rmb_base + SSCAON_CONFIG);
313
314	/* 8 - De-assert WCSS/Q6 HALTREQ */
315	reset_control_assert(wcss->wcss_reset);
316
317	return 0;
318	}
319
320	static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
321	{
322	int ret;
323	u32 val;
324	int i;
325
326	/* 1 - Halt Q6 bus interface */
327	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6);
328
329	/* 2 - Disable Q6 Core clock */
330	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
331	val &= ~Q6SS_CLK_ENABLE;
332	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
333
334	/* 3 - Clamp I/O */
335	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
336	val \|= Q6SS_CLAMP_IO;
337	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
338
339	/* 4 - Clamp WL */
340	val \|= QDSS_BHS_ON;
341	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
342
343	/* 5 - Clear Erase standby */
344	val &= ~Q6SS_L2DATA_STBY_N;
345	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
346
347	/* 6 - Clear Sleep RTN */
348	val &= ~Q6SS_SLP_RET_N;
349	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
350
351	/* 7 - turn off Q6 memory foot/head switch one bank at a time */
352	for (i = 0; i < 20; i++) {
353	val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
354	val &= ~BIT(i);
355	writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
356	mdelay(1);
357	}
358
359	/* 8 - Assert QMC memory RTN */
360	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
361	val \|= Q6SS_CLAMP_QMC_MEM;
362	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
363
364	/* 9 - Turn off BHS */
365	val &= ~Q6SS_BHS_ON;
366	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
367	udelay(1);
368
369	/* 10 - Wait till BHS Reset is done */
370	ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,
371	val, !(val & BHS_EN_REST_ACK), 1000,
372	HALT_CHECK_MAX_LOOPS);
373	if (ret) {
374	dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret);
375	return ret;
376	}
377
378	/* 11 - Assert WCSS reset */
379	reset_control_assert(wcss->wcss_reset);
380
381	/* 12 - Assert Q6 reset */
382	reset_control_assert(wcss->wcss_q6_reset);
383
384	return 0;
385	}
386
387	static int q6v5_wcss_stop(struct rproc *rproc)
388	{
389	struct q6v5_wcss *wcss = rproc->priv;
390	int ret;
391
392	/* WCSS powerdown */
ed5da808	393	ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
3a3d4163 S	394	if (ret == -ETIMEDOUT) {
	395	dev_err(wcss->dev, "timed out on wait\n");
	396	return ret;
	397	}
	398
	399	ret = q6v5_wcss_powerdown(wcss);
	400	if (ret)
	401	return ret;
	402
	403	/* Q6 Power down */
	404	ret = q6v5_q6_powerdown(wcss);
	405	if (ret)
	406	return ret;
	407
	408	qcom_q6v5_unprepare(&wcss->q6v5);
	409
	410	return 0;
	411	}
	412
9ce3bf22	413	static void q6v5_wcss_da_to_va(struct rproc rproc, u64 da, size_t len)
3a3d4163 S	414	{
	415	struct q6v5_wcss *wcss = rproc->priv;
	416	int offset;
	417
	418	offset = da - wcss->mem_reloc;
	419	if (offset < 0 \|\| offset + len > wcss->mem_size)
	420	return NULL;
	421
	422	return wcss->mem_region + offset;
	423	}
	424
	425	static int q6v5_wcss_load(struct rproc rproc, const struct firmware fw)
	426	{
	427	struct q6v5_wcss *wcss = rproc->priv;
d4c78d21 BA	428	int ret;
	429
	430	ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
	431	0, wcss->mem_region, wcss->mem_phys,
	432	wcss->mem_size, &wcss->mem_reloc);
	433	if (ret)
	434	return ret;
	435
	436	qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size);
3a3d4163	437
d4c78d21	438	return ret;
3a3d4163 S	439	}
	440
	441	static const struct rproc_ops q6v5_wcss_ops = {
	442	.start = q6v5_wcss_start,
	443	.stop = q6v5_wcss_stop,
	444	.da_to_va = q6v5_wcss_da_to_va,
	445	.load = q6v5_wcss_load,
	446	.get_boot_addr = rproc_elf_get_boot_addr,
	447	};
	448
	449	static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
	450	{
	451	struct device *dev = wcss->dev;
	452
	453	wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
	454	if (IS_ERR(wcss->wcss_aon_reset)) {
	455	dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n");
	456	return PTR_ERR(wcss->wcss_aon_reset);
	457	}
	458
	459	wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
	460	if (IS_ERR(wcss->wcss_reset)) {
	461	dev_err(wcss->dev, "unable to acquire wcss_reset\n");
	462	return PTR_ERR(wcss->wcss_reset);
	463	}
	464
	465	wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
	466	if (IS_ERR(wcss->wcss_q6_reset)) {
	467	dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
	468	return PTR_ERR(wcss->wcss_q6_reset);
	469	}
	470
	471	return 0;
	472	}
	473
	474	static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
	475	struct platform_device *pdev)
	476	{
	477	struct of_phandle_args args;
	478	struct resource *res;
	479	int ret;
	480
	481	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
	482	wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
	483	if (IS_ERR(wcss->reg_base))
	484	return PTR_ERR(wcss->reg_base);
	485
	486	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
	487	wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
	488	if (IS_ERR(wcss->rmb_base))
	489	return PTR_ERR(wcss->rmb_base);
	490
	491	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
	492	"qcom,halt-regs", 3, 0, &args);
	493	if (ret < 0) {
	494	dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
	495	return -EINVAL;
	496	}
	497
	498	wcss->halt_map = syscon_node_to_regmap(args.np);
	499	of_node_put(args.np);
	500	if (IS_ERR(wcss->halt_map))
	501	return PTR_ERR(wcss->halt_map);
	502
503	wcss->halt_q6 = args.args[0];
504	wcss->halt_wcss = args.args[1];
505	wcss->halt_nc = args.args[2];
506
507	return 0;
508	}
509
510	static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
511	{
512	struct reserved_mem *rmem = NULL;
513	struct device_node *node;
514	struct device *dev = wcss->dev;
515
516	node = of_parse_phandle(dev->of_node, "memory-region", 0);
517	if (node)
518	rmem = of_reserved_mem_lookup(node);
519	of_node_put(node);
520
521	if (!rmem) {
522	dev_err(dev, "unable to acquire memory-region\n");
523	return -EINVAL;
524	}
525
526	wcss->mem_phys = rmem->base;
527	wcss->mem_reloc = rmem->base;
528	wcss->mem_size = rmem->size;
529	wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size);
530	if (!wcss->mem_region) {
531	dev_err(dev, "unable to map memory region: %pa+%pa\n",
532	&rmem->base, &rmem->size);
533	return -EBUSY;
534	}
535
536	return 0;
537	}
538
539	static int q6v5_wcss_probe(struct platform_device *pdev)
540	{
541	struct q6v5_wcss *wcss;
542	struct rproc *rproc;
543	int ret;
544
545	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops,
546	"IPQ8074/q6_fw.mdt", sizeof(*wcss));
547	if (!rproc) {
548	dev_err(&pdev->dev, "failed to allocate rproc\n");
549	return -ENOMEM;
550	}
551
552	wcss = rproc->priv;
553	wcss->dev = &pdev->dev;
554
555	ret = q6v5_wcss_init_mmio(wcss, pdev);
556	if (ret)
557	goto free_rproc;
558
559	ret = q6v5_alloc_memory_region(wcss);
560	if (ret)
561	goto free_rproc;
562
563	ret = q6v5_wcss_init_reset(wcss);
564	if (ret)
565	goto free_rproc;
566
567	ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
568	if (ret)
569	goto free_rproc;
570
25f9f5a2	571	qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
8a226e2c SM	572	qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
8a226e2c SM	573
3a3d4163 S	574	ret = rproc_add(rproc);
	575	if (ret)
	576	goto free_rproc;
	577
	578	platform_set_drvdata(pdev, rproc);
	579
	580	return 0;
	581
	582	free_rproc:
	583	rproc_free(rproc);
	584
	585	return ret;
	586	}
	587
	588	static int q6v5_wcss_remove(struct platform_device *pdev)
	589	{
	590	struct rproc *rproc = platform_get_drvdata(pdev);
	591
	592	rproc_del(rproc);
	593	rproc_free(rproc);
	594
	595	return 0;
	596	}
	597
	598	static const struct of_device_id q6v5_wcss_of_match[] = {
	599	{ .compatible = "qcom,ipq8074-wcss-pil" },
	600	{ },
	601	};
	602	MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);
	603
	604	static struct platform_driver q6v5_wcss_driver = {
	605	.probe = q6v5_wcss_probe,
	606	.remove = q6v5_wcss_remove,
	607	.driver = {
	608	.name = "qcom-q6v5-wcss-pil",
	609	.of_match_table = q6v5_wcss_of_match,
	610	},
	611	};
	612	module_platform_driver(q6v5_wcss_driver);
	613
	614	MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader");
	615	MODULE_LICENSE("GPL v2");