[mirror_ubuntu-jammy-kernel.git] / drivers / remoteproc / qcom_wcnss.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
 *
 * Copyright (C) 2016 Linaro Ltd
 * Copyright (C) 2014 Sony Mobile Communications AB
 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/rpmsg/qcom_smd.h>

#include "qcom_common.h"
#include "remoteproc_internal.h"
#include "qcom_pil_info.h"
#include "qcom_wcnss.h"

#define WCNSS_CRASH_REASON_SMEM		422
#define WCNSS_FIRMWARE_NAME		"wcnss.mdt"
#define WCNSS_PAS_ID			6
#define WCNSS_SSCTL_ID			0x13

#define WCNSS_SPARE_NVBIN_DLND		BIT(25)

#define WCNSS_PMU_IRIS_XO_CFG		BIT(3)
#define WCNSS_PMU_IRIS_XO_EN		BIT(4)
#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP	BIT(5)
#define WCNSS_PMU_IRIS_XO_CFG_STS	BIT(6) /* 1: in progress, 0: done */

#define WCNSS_PMU_IRIS_RESET		BIT(7)
#define WCNSS_PMU_IRIS_RESET_STS	BIT(8) /* 1: in progress, 0: done */
#define WCNSS_PMU_IRIS_XO_READ		BIT(9)
#define WCNSS_PMU_IRIS_XO_READ_STS	BIT(10)

#define WCNSS_PMU_XO_MODE_MASK		GENMASK(2, 1)
#define WCNSS_PMU_XO_MODE_19p2		0
#define WCNSS_PMU_XO_MODE_48		3

#define WCNSS_MAX_PDS			2

struct wcnss_data {
	size_t pmu_offset;
	size_t spare_offset;

	const char *pd_names[WCNSS_MAX_PDS];
	const struct wcnss_vreg_info *vregs;
	size_t num_vregs, num_pd_vregs;
};

struct qcom_wcnss {
	struct device *dev;
	struct rproc *rproc;

	void __iomem *pmu_cfg;
	void __iomem *spare_out;

	bool use_48mhz_xo;

	int wdog_irq;
	int fatal_irq;
	int ready_irq;
	int handover_irq;
	int stop_ack_irq;

	struct qcom_smem_state *state;
	unsigned stop_bit;

	struct mutex iris_lock;
	struct qcom_iris *iris;

	struct device *pds[WCNSS_MAX_PDS];
	size_t num_pds;
	struct regulator_bulk_data *vregs;
	size_t num_vregs;

	struct completion start_done;
	struct completion stop_done;

	phys_addr_t mem_phys;
	phys_addr_t mem_reloc;
	void *mem_region;
	size_t mem_size;

	struct qcom_rproc_subdev smd_subdev;
	struct qcom_sysmon *sysmon;
};

static const struct wcnss_data riva_data = {
	.pmu_offset = 0x28,
	.spare_offset = 0xb4,

	.vregs = (struct wcnss_vreg_info[]) {
		{ "vddmx",  1050000, 1150000, 0 },
		{ "vddcx",  1050000, 1150000, 0 },
		{ "vddpx",  1800000, 1800000, 0 },
	},
	.num_vregs = 3,
};

static const struct wcnss_data pronto_v1_data = {
	.pmu_offset = 0x1004,
	.spare_offset = 0x1088,

	.pd_names = { "mx", "cx" },
	.vregs = (struct wcnss_vreg_info[]) {
		{ "vddmx", 950000, 1150000, 0 },
		{ "vddcx", .super_turbo = true},
		{ "vddpx", 1800000, 1800000, 0 },
	},
	.num_pd_vregs = 2,
	.num_vregs = 1,
};

static const struct wcnss_data pronto_v2_data = {
	.pmu_offset = 0x1004,
	.spare_offset = 0x1088,

	.pd_names = { "mx", "cx" },
	.vregs = (struct wcnss_vreg_info[]) {
		{ "vddmx", 1287500, 1287500, 0 },
		{ "vddcx", .super_turbo = true },
		{ "vddpx", 1800000, 1800000, 0 },
	},
	.num_pd_vregs = 2,
	.num_vregs = 1,
};

void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
			    struct qcom_iris *iris,
			    bool use_48mhz_xo)
{
	mutex_lock(&wcnss->iris_lock);

	wcnss->iris = iris;
	wcnss->use_48mhz_xo = use_48mhz_xo;

	mutex_unlock(&wcnss->iris_lock);
}

static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int ret;

	ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
			    wcnss->mem_region, wcnss->mem_phys,
			    wcnss->mem_size, &wcnss->mem_reloc);
	if (ret)
		return ret;

	qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);

	return 0;
}

static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
{
	u32 val;

	/* Indicate NV download capability */
	val = readl(wcnss->spare_out);
	val |= WCNSS_SPARE_NVBIN_DLND;
	writel(val, wcnss->spare_out);
}

static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
{
	u32 val;

	/* Clear PMU cfg register */
	writel(0, wcnss->pmu_cfg);

	val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
	writel(val, wcnss->pmu_cfg);

	/* Clear XO_MODE */
	val &= ~WCNSS_PMU_XO_MODE_MASK;
	if (wcnss->use_48mhz_xo)
		val |= WCNSS_PMU_XO_MODE_48 << 1;
	else
		val |= WCNSS_PMU_XO_MODE_19p2 << 1;
	writel(val, wcnss->pmu_cfg);

	/* Reset IRIS */
	val |= WCNSS_PMU_IRIS_RESET;
	writel(val, wcnss->pmu_cfg);

	/* Wait for PMU.iris_reg_reset_sts */
	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
		cpu_relax();

	/* Clear IRIS reset */
	val &= ~WCNSS_PMU_IRIS_RESET;
	writel(val, wcnss->pmu_cfg);

	/* Start IRIS XO configuration */
	val |= WCNSS_PMU_IRIS_XO_CFG;
	writel(val, wcnss->pmu_cfg);

	/* Wait for XO configuration to finish */
	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
		cpu_relax();

	/* Stop IRIS XO configuration */
	val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
	val &= ~WCNSS_PMU_IRIS_XO_CFG;
	writel(val, wcnss->pmu_cfg);

	/* Add some delay for XO to settle */
	msleep(20);
}

static int wcnss_start(struct rproc *rproc)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int ret, i;

	mutex_lock(&wcnss->iris_lock);
	if (!wcnss->iris) {
		dev_err(wcnss->dev, "no iris registered\n");
		ret = -EINVAL;
		goto release_iris_lock;
	}

	for (i = 0; i < wcnss->num_pds; i++) {
		dev_pm_genpd_set_performance_state(wcnss->pds[i], INT_MAX);
		ret = pm_runtime_get_sync(wcnss->pds[i]);
		if (ret < 0) {
			pm_runtime_put_noidle(wcnss->pds[i]);
			goto disable_pds;
		}
	}

	ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
	if (ret)
		goto disable_pds;

	ret = qcom_iris_enable(wcnss->iris);
	if (ret)
		goto disable_regulators;

	wcnss_indicate_nv_download(wcnss);
	wcnss_configure_iris(wcnss);

	ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
	if (ret) {
		dev_err(wcnss->dev,
			"failed to authenticate image and release reset\n");
		goto disable_iris;
	}

	ret = wait_for_completion_timeout(&wcnss->start_done,
					  msecs_to_jiffies(5000));
	if (wcnss->ready_irq > 0 && ret == 0) {
		/* We have a ready_irq, but it didn't fire in time. */
		dev_err(wcnss->dev, "start timed out\n");
		qcom_scm_pas_shutdown(WCNSS_PAS_ID);
		ret = -ETIMEDOUT;
		goto disable_iris;
	}

	ret = 0;

disable_iris:
	qcom_iris_disable(wcnss->iris);
disable_regulators:
	regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
disable_pds:
	for (i--; i >= 0; i--) {
		pm_runtime_put(wcnss->pds[i]);
		dev_pm_genpd_set_performance_state(wcnss->pds[i], 0);
	}
release_iris_lock:
	mutex_unlock(&wcnss->iris_lock);

	return ret;
}

static int wcnss_stop(struct rproc *rproc)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int ret;

	if (wcnss->state) {
		qcom_smem_state_update_bits(wcnss->state,
					    BIT(wcnss->stop_bit),
					    BIT(wcnss->stop_bit));

		ret = wait_for_completion_timeout(&wcnss->stop_done,
						  msecs_to_jiffies(5000));
		if (ret == 0)
			dev_err(wcnss->dev, "timed out on wait\n");

		qcom_smem_state_update_bits(wcnss->state,
					    BIT(wcnss->stop_bit),
					    0);
	}

	ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
	if (ret)
		dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);

	return ret;
}

static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int offset;

	offset = da - wcnss->mem_reloc;
	if (offset < 0 || offset + len > wcnss->mem_size)
		return NULL;

	return wcnss->mem_region + offset;
}

static const struct rproc_ops wcnss_ops = {
	.start = wcnss_start,
	.stop = wcnss_stop,
	.da_to_va = wcnss_da_to_va,
	.parse_fw = qcom_register_dump_segments,
	.load = wcnss_load,
};

static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;

	rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;
	size_t len;
	char *msg;

	msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
	if (!IS_ERR(msg) && len > 0 && msg[0])
		dev_err(wcnss->dev, "fatal error received: %s\n", msg);

	rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;

	complete(&wcnss->start_done);

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
{
	/*
	 * XXX: At this point we're supposed to release the resources that we
	 * have been holding on behalf of the WCNSS. Unfortunately this
	 * interrupt comes way before the other side seems to be done.
	 *
	 * So we're currently relying on the ready interrupt firing later then
	 * this and we just disable the resources at the end of wcnss_start().
	 */

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;

	complete(&wcnss->stop_done);

	return IRQ_HANDLED;
}

static int wcnss_init_pds(struct qcom_wcnss *wcnss,
			  const char * const pd_names[WCNSS_MAX_PDS])
{
	int i, ret;

	for (i = 0; i < WCNSS_MAX_PDS; i++) {
		if (!pd_names[i])
			break;

		wcnss->pds[i] = dev_pm_domain_attach_by_name(wcnss->dev, pd_names[i]);
		if (IS_ERR_OR_NULL(wcnss->pds[i])) {
			ret = PTR_ERR(wcnss->pds[i]) ? : -ENODATA;
			for (i--; i >= 0; i--)
				dev_pm_domain_detach(wcnss->pds[i], false);
			return ret;
		}
	}
	wcnss->num_pds = i;

	return 0;
}

static void wcnss_release_pds(struct qcom_wcnss *wcnss)
{
	int i;

	for (i = 0; i < wcnss->num_pds; i++)
		dev_pm_domain_detach(wcnss->pds[i], false);
}

static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
				 const struct wcnss_vreg_info *info,
				 int num_vregs, int num_pd_vregs)
{
	struct regulator_bulk_data *bulk;
	int ret;
	int i;

	/*
	 * If attaching the power domains suceeded we can skip requesting
	 * the regulators for the power domains. For old device trees we need to
	 * reserve extra space to manage them through the regulator interface.
	 */
	if (wcnss->num_pds)
		info += num_pd_vregs;
	else
		num_vregs += num_pd_vregs;

	bulk = devm_kcalloc(wcnss->dev,
			    num_vregs, sizeof(struct regulator_bulk_data),
			    GFP_KERNEL);
	if (!bulk)
		return -ENOMEM;

	for (i = 0; i < num_vregs; i++)
		bulk[i].supply = info[i].name;

	ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
	if (ret)
		return ret;

	for (i = 0; i < num_vregs; i++) {
		if (info[i].max_voltage)
			regulator_set_voltage(bulk[i].consumer,
					      info[i].min_voltage,
					      info[i].max_voltage);

		if (info[i].load_uA)
			regulator_set_load(bulk[i].consumer, info[i].load_uA);
	}

	wcnss->vregs = bulk;
	wcnss->num_vregs = num_vregs;

	return 0;
}

static int wcnss_request_irq(struct qcom_wcnss *wcnss,
			     struct platform_device *pdev,
			     const char *name,
			     bool optional,
			     irq_handler_t thread_fn)
{
	int ret;

	ret = platform_get_irq_byname(pdev, name);
	if (ret < 0 && optional) {
		dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
		return 0;
	} else if (ret < 0) {
		dev_err(&pdev->dev, "no %s IRQ defined\n", name);
		return ret;
	}

	ret = devm_request_threaded_irq(&pdev->dev, ret,
					NULL, thread_fn,
					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
					"wcnss", wcnss);
	if (ret)
		dev_err(&pdev->dev, "request %s IRQ failed\n", name);

	return ret;
}

static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
{
	struct device_node *node;
	struct resource r;
	int ret;

	node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
	if (!node) {
		dev_err(wcnss->dev, "no memory-region specified\n");
		return -EINVAL;
	}

	ret = of_address_to_resource(node, 0, &r);
	if (ret)
		return ret;

	wcnss->mem_phys = wcnss->mem_reloc = r.start;
	wcnss->mem_size = resource_size(&r);
	wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
	if (!wcnss->mem_region) {
		dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
			&r.start, wcnss->mem_size);
		return -EBUSY;
	}

	return 0;
}

static int wcnss_probe(struct platform_device *pdev)
{
	const struct wcnss_data *data;
	struct qcom_wcnss *wcnss;
	struct resource *res;
	struct rproc *rproc;
	void __iomem *mmio;
	int ret;

	data = of_device_get_match_data(&pdev->dev);

	if (!qcom_scm_is_available())
		return -EPROBE_DEFER;

	if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
		dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
		return -ENXIO;
	}

	rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
			    WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
	if (!rproc) {
		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
		return -ENOMEM;
	}
	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);

	wcnss = (struct qcom_wcnss *)rproc->priv;
	wcnss->dev = &pdev->dev;
	wcnss->rproc = rproc;
	platform_set_drvdata(pdev, wcnss);

	init_completion(&wcnss->start_done);
	init_completion(&wcnss->stop_done);

	mutex_init(&wcnss->iris_lock);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
	mmio = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mmio)) {
		ret = PTR_ERR(mmio);
		goto free_rproc;
	}

	ret = wcnss_alloc_memory_region(wcnss);
	if (ret)
		goto free_rproc;

	wcnss->pmu_cfg = mmio + data->pmu_offset;
	wcnss->spare_out = mmio + data->spare_offset;

	/*
	 * We might need to fallback to regulators instead of power domains
	 * for old device trees. Don't report an error in that case.
	 */
	ret = wcnss_init_pds(wcnss, data->pd_names);
	if (ret && (ret != -ENODATA || !data->num_pd_vregs))
		goto free_rproc;

	ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs,
				    data->num_pd_vregs);
	if (ret)
		goto detach_pds;

	ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
	if (ret < 0)
		goto detach_pds;
	wcnss->wdog_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
	if (ret < 0)
		goto detach_pds;
	wcnss->fatal_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
	if (ret < 0)
		goto detach_pds;
	wcnss->ready_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
	if (ret < 0)
		goto detach_pds;
	wcnss->handover_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
	if (ret < 0)
		goto detach_pds;
	wcnss->stop_ack_irq = ret;

	if (wcnss->stop_ack_irq) {
		wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
						   &wcnss->stop_bit);
		if (IS_ERR(wcnss->state)) {
			ret = PTR_ERR(wcnss->state);
			goto detach_pds;
		}
	}

	qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
	wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
	if (IS_ERR(wcnss->sysmon)) {
		ret = PTR_ERR(wcnss->sysmon);
		goto detach_pds;
	}

	ret = rproc_add(rproc);
	if (ret)
		goto detach_pds;

	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

detach_pds:
	wcnss_release_pds(wcnss);
free_rproc:
	rproc_free(rproc);

	return ret;
}

static int wcnss_remove(struct platform_device *pdev)
{
	struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);

	of_platform_depopulate(&pdev->dev);

	qcom_smem_state_put(wcnss->state);
	rproc_del(wcnss->rproc);

	qcom_remove_sysmon_subdev(wcnss->sysmon);
	qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
	wcnss_release_pds(wcnss);
	rproc_free(wcnss->rproc);

	return 0;
}

static const struct of_device_id wcnss_of_match[] = {
	{ .compatible = "qcom,riva-pil", &riva_data },
	{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
	{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
	{ },
};
MODULE_DEVICE_TABLE(of, wcnss_of_match);

static struct platform_driver wcnss_driver = {
	.probe = wcnss_probe,
	.remove = wcnss_remove,
	.driver = {
		.name = "qcom-wcnss-pil",
		.of_match_table = wcnss_of_match,
	},
};

static int __init wcnss_init(void)
{
	int ret;

	ret = platform_driver_register(&wcnss_driver);
	if (ret)
		return ret;

	ret = platform_driver_register(&qcom_iris_driver);
	if (ret)
		platform_driver_unregister(&wcnss_driver);

	return ret;
}
module_init(wcnss_init);

static void __exit wcnss_exit(void)
{
	platform_driver_unregister(&qcom_iris_driver);
	platform_driver_unregister(&wcnss_driver);
}
module_exit(wcnss_exit);

MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
aed361ad BA	2	/*
	3	* Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
	4	*
	5	* Copyright (C) 2016 Linaro Ltd
	6	* Copyright (C) 2014 Sony Mobile Communications AB
	7	* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
aed361ad BA	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/delay.h>
	12	#include <linux/firmware.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/io.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_device.h>
	19	#include <linux/platform_device.h>
858bce9c SG	20	#include <linux/pm_domain.h>
858bce9c SG	21	#include <linux/pm_runtime.h>
aed361ad BA	22	#include <linux/qcom_scm.h>
	23	#include <linux/regulator/consumer.h>
	24	#include <linux/remoteproc.h>
2aad40d9	25	#include <linux/soc/qcom/mdt_loader.h>
aed361ad BA	26	#include <linux/soc/qcom/smem.h>
aed361ad BA	27	#include <linux/soc/qcom/smem_state.h>
5a856bc6	28	#include <linux/rpmsg/qcom_smd.h>
aed361ad	29
bde440ee	30	#include "qcom_common.h"
aed361ad	31	#include "remoteproc_internal.h"
d4c78d21	32	#include "qcom_pil_info.h"
aed361ad BA	33	#include "qcom_wcnss.h"
	34
	35	#define WCNSS_CRASH_REASON_SMEM 422
	36	#define WCNSS_FIRMWARE_NAME "wcnss.mdt"
	37	#define WCNSS_PAS_ID 6
1fb82ee8	38	#define WCNSS_SSCTL_ID 0x13
aed361ad BA	39
	40	#define WCNSS_SPARE_NVBIN_DLND BIT(25)
	41
	42	#define WCNSS_PMU_IRIS_XO_CFG BIT(3)
	43	#define WCNSS_PMU_IRIS_XO_EN BIT(4)
	44	#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
	45	#define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
	46
	47	#define WCNSS_PMU_IRIS_RESET BIT(7)
	48	#define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
	49	#define WCNSS_PMU_IRIS_XO_READ BIT(9)
	50	#define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
	51
	52	#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
	53	#define WCNSS_PMU_XO_MODE_19p2 0
	54	#define WCNSS_PMU_XO_MODE_48 3
	55
858bce9c SG	56	#define WCNSS_MAX_PDS 2
858bce9c SG	57
aed361ad BA	58	struct wcnss_data {
	59	size_t pmu_offset;
	60	size_t spare_offset;
	61
858bce9c	62	const char *pd_names[WCNSS_MAX_PDS];
aed361ad	63	const struct wcnss_vreg_info *vregs;
858bce9c	64	size_t num_vregs, num_pd_vregs;
aed361ad BA	65	};
	66
	67	struct qcom_wcnss {
	68	struct device *dev;
	69	struct rproc *rproc;
	70
	71	void __iomem *pmu_cfg;
	72	void __iomem *spare_out;
	73
	74	bool use_48mhz_xo;
	75
	76	int wdog_irq;
	77	int fatal_irq;
	78	int ready_irq;
	79	int handover_irq;
	80	int stop_ack_irq;
	81
	82	struct qcom_smem_state *state;
	83	unsigned stop_bit;
	84
	85	struct mutex iris_lock;
	86	struct qcom_iris *iris;
	87
858bce9c SG	88	struct device *pds[WCNSS_MAX_PDS];
858bce9c SG	89	size_t num_pds;
aed361ad BA	90	struct regulator_bulk_data *vregs;
	91	size_t num_vregs;
	92
	93	struct completion start_done;
	94	struct completion stop_done;
	95
	96	phys_addr_t mem_phys;
	97	phys_addr_t mem_reloc;
	98	void *mem_region;
	99	size_t mem_size;
5a856bc6	100
b90fcfcb	101	struct qcom_rproc_subdev smd_subdev;
1fb82ee8	102	struct qcom_sysmon *sysmon;
aed361ad BA	103	};
	104
	105	static const struct wcnss_data riva_data = {
	106	.pmu_offset = 0x28,
	107	.spare_offset = 0xb4,
	108
	109	.vregs = (struct wcnss_vreg_info[]) {
	110	{ "vddmx", 1050000, 1150000, 0 },
	111	{ "vddcx", 1050000, 1150000, 0 },
	112	{ "vddpx", 1800000, 1800000, 0 },
	113	},
	114	.num_vregs = 3,
	115	};
	116
	117	static const struct wcnss_data pronto_v1_data = {
	118	.pmu_offset = 0x1004,
	119	.spare_offset = 0x1088,
	120
858bce9c	121	.pd_names = { "mx", "cx" },
aed361ad BA	122	.vregs = (struct wcnss_vreg_info[]) {
	123	{ "vddmx", 950000, 1150000, 0 },
	124	{ "vddcx", .super_turbo = true},
	125	{ "vddpx", 1800000, 1800000, 0 },
	126	},
858bce9c SG	127	.num_pd_vregs = 2,
858bce9c SG	128	.num_vregs = 1,
aed361ad BA	129	};
	130
	131	static const struct wcnss_data pronto_v2_data = {
	132	.pmu_offset = 0x1004,
	133	.spare_offset = 0x1088,
	134
858bce9c	135	.pd_names = { "mx", "cx" },
aed361ad BA	136	.vregs = (struct wcnss_vreg_info[]) {
	137	{ "vddmx", 1287500, 1287500, 0 },
	138	{ "vddcx", .super_turbo = true },
	139	{ "vddpx", 1800000, 1800000, 0 },
	140	},
858bce9c SG	141	.num_pd_vregs = 2,
858bce9c SG	142	.num_vregs = 1,
aed361ad BA	143	};
	144
	145	void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
	146	struct qcom_iris *iris,
	147	bool use_48mhz_xo)
	148	{
	149	mutex_lock(&wcnss->iris_lock);
	150
	151	wcnss->iris = iris;
	152	wcnss->use_48mhz_xo = use_48mhz_xo;
	153
	154	mutex_unlock(&wcnss->iris_lock);
	155	}
aed361ad BA	156
	157	static int wcnss_load(struct rproc rproc, const struct firmware fw)
	158	{
	159	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
d4c78d21	160	int ret;
7f0dd07a	161
d4c78d21 BA	162	ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
	163	wcnss->mem_region, wcnss->mem_phys,
	164	wcnss->mem_size, &wcnss->mem_reloc);
	165	if (ret)
	166	return ret;
	167
	168	qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
	169
	170	return 0;
aed361ad BA	171	}
aed361ad BA	172
aed361ad BA	173	static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
	174	{
	175	u32 val;
	176
	177	/* Indicate NV download capability */
	178	val = readl(wcnss->spare_out);
	179	val \|= WCNSS_SPARE_NVBIN_DLND;
	180	writel(val, wcnss->spare_out);
	181	}
	182
	183	static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
	184	{
	185	u32 val;
	186
	187	/* Clear PMU cfg register */
	188	writel(0, wcnss->pmu_cfg);
	189
	190	val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP \| WCNSS_PMU_IRIS_XO_EN;
	191	writel(val, wcnss->pmu_cfg);
	192
	193	/* Clear XO_MODE */
	194	val &= ~WCNSS_PMU_XO_MODE_MASK;
	195	if (wcnss->use_48mhz_xo)
	196	val \|= WCNSS_PMU_XO_MODE_48 << 1;
	197	else
	198	val \|= WCNSS_PMU_XO_MODE_19p2 << 1;
	199	writel(val, wcnss->pmu_cfg);
	200
	201	/* Reset IRIS */
	202	val \|= WCNSS_PMU_IRIS_RESET;
	203	writel(val, wcnss->pmu_cfg);
	204
	205	/* Wait for PMU.iris_reg_reset_sts */
	206	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
	207	cpu_relax();
	208
	209	/* Clear IRIS reset */
	210	val &= ~WCNSS_PMU_IRIS_RESET;
	211	writel(val, wcnss->pmu_cfg);
	212
	213	/* Start IRIS XO configuration */
	214	val \|= WCNSS_PMU_IRIS_XO_CFG;
	215	writel(val, wcnss->pmu_cfg);
	216
	217	/* Wait for XO configuration to finish */
	218	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
	219	cpu_relax();
	220
	221	/* Stop IRIS XO configuration */
	222	val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
	223	val &= ~WCNSS_PMU_IRIS_XO_CFG;
	224	writel(val, wcnss->pmu_cfg);
	225
	226	/* Add some delay for XO to settle */
	227	msleep(20);
	228	}
	229
	230	static int wcnss_start(struct rproc *rproc)
	231	{
	232	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
858bce9c	233	int ret, i;
aed361ad BA	234
	235	mutex_lock(&wcnss->iris_lock);
	236	if (!wcnss->iris) {
	237	dev_err(wcnss->dev, "no iris registered\n");
	238	ret = -EINVAL;
	239	goto release_iris_lock;
	240	}
	241
858bce9c SG	242	for (i = 0; i < wcnss->num_pds; i++) {
	243	dev_pm_genpd_set_performance_state(wcnss->pds[i], INT_MAX);
	244	ret = pm_runtime_get_sync(wcnss->pds[i]);
	245	if (ret < 0) {
	246	pm_runtime_put_noidle(wcnss->pds[i]);
	247	goto disable_pds;
	248	}
	249	}
	250
aed361ad BA	251	ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
aed361ad BA	252	if (ret)
858bce9c	253	goto disable_pds;
aed361ad BA	254
	255	ret = qcom_iris_enable(wcnss->iris);
	256	if (ret)
	257	goto disable_regulators;
	258
	259	wcnss_indicate_nv_download(wcnss);
	260	wcnss_configure_iris(wcnss);
	261
	262	ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
	263	if (ret) {
	264	dev_err(wcnss->dev,
	265	"failed to authenticate image and release reset\n");
	266	goto disable_iris;
	267	}
	268
	269	ret = wait_for_completion_timeout(&wcnss->start_done,
	270	msecs_to_jiffies(5000));
	271	if (wcnss->ready_irq > 0 && ret == 0) {
	272	/* We have a ready_irq, but it didn't fire in time. */
	273	dev_err(wcnss->dev, "start timed out\n");
	274	qcom_scm_pas_shutdown(WCNSS_PAS_ID);
	275	ret = -ETIMEDOUT;
	276	goto disable_iris;
	277	}
	278
	279	ret = 0;
	280
	281	disable_iris:
	282	qcom_iris_disable(wcnss->iris);
	283	disable_regulators:
	284	regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
858bce9c SG	285	disable_pds:
	286	for (i--; i >= 0; i--) {
	287	pm_runtime_put(wcnss->pds[i]);
	288	dev_pm_genpd_set_performance_state(wcnss->pds[i], 0);
	289	}
aed361ad BA	290	release_iris_lock:
	291	mutex_unlock(&wcnss->iris_lock);
	292
	293	return ret;
	294	}
	295
	296	static int wcnss_stop(struct rproc *rproc)
	297	{
	298	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
	299	int ret;
	300
	301	if (wcnss->state) {
	302	qcom_smem_state_update_bits(wcnss->state,
	303	BIT(wcnss->stop_bit),
	304	BIT(wcnss->stop_bit));
	305
	306	ret = wait_for_completion_timeout(&wcnss->stop_done,
	307	msecs_to_jiffies(5000));
	308	if (ret == 0)
	309	dev_err(wcnss->dev, "timed out on wait\n");
	310
	311	qcom_smem_state_update_bits(wcnss->state,
	312	BIT(wcnss->stop_bit),
	313	0);
	314	}
	315
	316	ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
	317	if (ret)
	318	dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
	319
	320	return ret;
	321	}
	322
9ce3bf22	323	static void wcnss_da_to_va(struct rproc rproc, u64 da, size_t len)
aed361ad BA	324	{
	325	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
	326	int offset;
	327
	328	offset = da - wcnss->mem_reloc;
	329	if (offset < 0 \|\| offset + len > wcnss->mem_size)
	330	return NULL;
	331
	332	return wcnss->mem_region + offset;
	333	}
	334
	335	static const struct rproc_ops wcnss_ops = {
	336	.start = wcnss_start,
	337	.stop = wcnss_stop,
	338	.da_to_va = wcnss_da_to_va,
dcb57ed4	339	.parse_fw = qcom_register_dump_segments,
0f21f9cc	340	.load = wcnss_load,
aed361ad BA	341	};
	342
	343	static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
	344	{
	345	struct qcom_wcnss *wcnss = dev;
	346
	347	rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
	348
	349	return IRQ_HANDLED;
	350	}
	351
	352	static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
	353	{
	354	struct qcom_wcnss *wcnss = dev;
	355	size_t len;
	356	char *msg;
	357
	358	msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
	359	if (!IS_ERR(msg) && len > 0 && msg[0])
	360	dev_err(wcnss->dev, "fatal error received: %s\n", msg);
	361
	362	rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
	363
aed361ad BA	364	return IRQ_HANDLED;
	365	}
	366
	367	static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
	368	{
	369	struct qcom_wcnss *wcnss = dev;
	370
	371	complete(&wcnss->start_done);
	372
	373	return IRQ_HANDLED;
	374	}
	375
	376	static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
	377	{
	378	/*
	379	* XXX: At this point we're supposed to release the resources that we
	380	* have been holding on behalf of the WCNSS. Unfortunately this
	381	* interrupt comes way before the other side seems to be done.
	382	*
	383	* So we're currently relying on the ready interrupt firing later then
	384	* this and we just disable the resources at the end of wcnss_start().
	385	*/
	386
	387	return IRQ_HANDLED;
	388	}
	389
	390	static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
	391	{
	392	struct qcom_wcnss *wcnss = dev;
	393
	394	complete(&wcnss->stop_done);
	395
	396	return IRQ_HANDLED;
	397	}
	398
858bce9c SG	399	static int wcnss_init_pds(struct qcom_wcnss *wcnss,
	400	const char * const pd_names[WCNSS_MAX_PDS])
	401	{
	402	int i, ret;
	403
	404	for (i = 0; i < WCNSS_MAX_PDS; i++) {
	405	if (!pd_names[i])
	406	break;
	407
	408	wcnss->pds[i] = dev_pm_domain_attach_by_name(wcnss->dev, pd_names[i]);
	409	if (IS_ERR_OR_NULL(wcnss->pds[i])) {
	410	ret = PTR_ERR(wcnss->pds[i]) ? : -ENODATA;
	411	for (i--; i >= 0; i--)
	412	dev_pm_domain_detach(wcnss->pds[i], false);
	413	return ret;
	414	}
	415	}
	416	wcnss->num_pds = i;
	417
	418	return 0;
	419	}
	420
	421	static void wcnss_release_pds(struct qcom_wcnss *wcnss)
	422	{
	423	int i;
	424
	425	for (i = 0; i < wcnss->num_pds; i++)
	426	dev_pm_domain_detach(wcnss->pds[i], false);
	427	}
	428
aed361ad BA	429	static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
aed361ad BA	430	const struct wcnss_vreg_info *info,
858bce9c	431	int num_vregs, int num_pd_vregs)
aed361ad BA	432	{
	433	struct regulator_bulk_data *bulk;
	434	int ret;
	435	int i;
	436
858bce9c SG	437	/*
	438	* If attaching the power domains suceeded we can skip requesting
	439	* the regulators for the power domains. For old device trees we need to
	440	* reserve extra space to manage them through the regulator interface.
	441	*/
	442	if (wcnss->num_pds)
	443	info += num_pd_vregs;
	444	else
	445	num_vregs += num_pd_vregs;
	446
aed361ad BA	447	bulk = devm_kcalloc(wcnss->dev,
	448	num_vregs, sizeof(struct regulator_bulk_data),
	449	GFP_KERNEL);
	450	if (!bulk)
	451	return -ENOMEM;
	452
	453	for (i = 0; i < num_vregs; i++)
	454	bulk[i].supply = info[i].name;
	455
	456	ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
	457	if (ret)
	458	return ret;
	459
	460	for (i = 0; i < num_vregs; i++) {
	461	if (info[i].max_voltage)
	462	regulator_set_voltage(bulk[i].consumer,
	463	info[i].min_voltage,
	464	info[i].max_voltage);
	465
	466	if (info[i].load_uA)
	467	regulator_set_load(bulk[i].consumer, info[i].load_uA);
	468	}
	469
	470	wcnss->vregs = bulk;
	471	wcnss->num_vregs = num_vregs;
	472
	473	return 0;
	474	}
	475
	476	static int wcnss_request_irq(struct qcom_wcnss *wcnss,
	477	struct platform_device *pdev,
	478	const char *name,
	479	bool optional,
	480	irq_handler_t thread_fn)
	481	{
	482	int ret;
	483
	484	ret = platform_get_irq_byname(pdev, name);
	485	if (ret < 0 && optional) {
	486	dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
	487	return 0;
	488	} else if (ret < 0) {
	489	dev_err(&pdev->dev, "no %s IRQ defined\n", name);
	490	return ret;
	491	}
	492
	493	ret = devm_request_threaded_irq(&pdev->dev, ret,
	494	NULL, thread_fn,
	495	IRQF_TRIGGER_RISING \| IRQF_ONESHOT,
	496	"wcnss", wcnss);
	497	if (ret)
	498	dev_err(&pdev->dev, "request %s IRQ failed\n", name);
	499
	500	return ret;
	501	}
	502
	503	static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
	504	{
	505	struct device_node *node;
	506	struct resource r;
	507	int ret;
	508
	509	node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
	510	if (!node) {
511	dev_err(wcnss->dev, "no memory-region specified\n");
512	return -EINVAL;
513	}
514
515	ret = of_address_to_resource(node, 0, &r);
516	if (ret)
517	return ret;
518
519	wcnss->mem_phys = wcnss->mem_reloc = r.start;
520	wcnss->mem_size = resource_size(&r);
521	wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
522	if (!wcnss->mem_region) {
523	dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
524	&r.start, wcnss->mem_size);
525	return -EBUSY;
526	}
527
528	return 0;
529	}
530
531	static int wcnss_probe(struct platform_device *pdev)
532	{
533	const struct wcnss_data *data;
534	struct qcom_wcnss *wcnss;
535	struct resource *res;
536	struct rproc *rproc;
537	void __iomem *mmio;
538	int ret;
539
540	data = of_device_get_match_data(&pdev->dev);
541
542	if (!qcom_scm_is_available())
543	return -EPROBE_DEFER;
544
545	if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
546	dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
547	return -ENXIO;
548	}
549
550	rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
551	WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
552	if (!rproc) {
553	dev_err(&pdev->dev, "unable to allocate remoteproc\n");
554	return -ENOMEM;
555	}
3898fc99	556	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
aed361ad	557
aed361ad BA	558	wcnss = (struct qcom_wcnss *)rproc->priv;
	559	wcnss->dev = &pdev->dev;
	560	wcnss->rproc = rproc;
	561	platform_set_drvdata(pdev, wcnss);
	562
	563	init_completion(&wcnss->start_done);
	564	init_completion(&wcnss->stop_done);
	565
	566	mutex_init(&wcnss->iris_lock);
	567
	568	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
	569	mmio = devm_ioremap_resource(&pdev->dev, res);
f4e1f9bb WY	570	if (IS_ERR(mmio)) {
f4e1f9bb WY	571	ret = PTR_ERR(mmio);
aed361ad	572	goto free_rproc;
9a1d2714	573	}
aed361ad BA	574
	575	ret = wcnss_alloc_memory_region(wcnss);
	576	if (ret)
	577	goto free_rproc;
	578
	579	wcnss->pmu_cfg = mmio + data->pmu_offset;
	580	wcnss->spare_out = mmio + data->spare_offset;
	581
858bce9c SG	582	/*
	583	* We might need to fallback to regulators instead of power domains
	584	* for old device trees. Don't report an error in that case.
	585	*/
	586	ret = wcnss_init_pds(wcnss, data->pd_names);
	587	if (ret && (ret != -ENODATA \|\| !data->num_pd_vregs))
aed361ad BA	588	goto free_rproc;
aed361ad BA	589
858bce9c SG	590	ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs,
	591	data->num_pd_vregs);
	592	if (ret)
	593	goto detach_pds;
	594
aed361ad BA	595	ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
aed361ad BA	596	if (ret < 0)
858bce9c	597	goto detach_pds;
aed361ad BA	598	wcnss->wdog_irq = ret;
	599
	600	ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
	601	if (ret < 0)
858bce9c	602	goto detach_pds;
aed361ad BA	603	wcnss->fatal_irq = ret;
	604
	605	ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
	606	if (ret < 0)
858bce9c	607	goto detach_pds;
aed361ad BA	608	wcnss->ready_irq = ret;
	609
	610	ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
	611	if (ret < 0)
858bce9c	612	goto detach_pds;
aed361ad BA	613	wcnss->handover_irq = ret;
	614
	615	ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
	616	if (ret < 0)
858bce9c	617	goto detach_pds;
aed361ad BA	618	wcnss->stop_ack_irq = ret;
	619
	620	if (wcnss->stop_ack_irq) {
	621	wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
	622	&wcnss->stop_bit);
	623	if (IS_ERR(wcnss->state)) {
	624	ret = PTR_ERR(wcnss->state);
858bce9c	625	goto detach_pds;
aed361ad BA	626	}
	627	}
	628
b90fcfcb	629	qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
1fb82ee8	630	wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
027045a6 SS	631	if (IS_ERR(wcnss->sysmon)) {
027045a6 SS	632	ret = PTR_ERR(wcnss->sysmon);
858bce9c	633	goto detach_pds;
027045a6	634	}
5a856bc6	635
aed361ad BA	636	ret = rproc_add(rproc);
aed361ad BA	637	if (ret)
858bce9c	638	goto detach_pds;
aed361ad BA	639
	640	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	641
858bce9c SG	642	detach_pds:
858bce9c SG	643	wcnss_release_pds(wcnss);
aed361ad	644	free_rproc:
433c0e04	645	rproc_free(rproc);
aed361ad BA	646
	647	return ret;
	648	}
	649
	650	static int wcnss_remove(struct platform_device *pdev)
	651	{
	652	struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
	653
	654	of_platform_depopulate(&pdev->dev);
	655
	656	qcom_smem_state_put(wcnss->state);
	657	rproc_del(wcnss->rproc);
b90fcfcb	658
1fb82ee8	659	qcom_remove_sysmon_subdev(wcnss->sysmon);
b90fcfcb	660	qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
858bce9c	661	wcnss_release_pds(wcnss);
433c0e04	662	rproc_free(wcnss->rproc);
aed361ad BA	663
	664	return 0;
	665	}
	666
	667	static const struct of_device_id wcnss_of_match[] = {
	668	{ .compatible = "qcom,riva-pil", &riva_data },
	669	{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
	670	{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
	671	{ },
	672	};
4958aabb	673	MODULE_DEVICE_TABLE(of, wcnss_of_match);
aed361ad BA	674
	675	static struct platform_driver wcnss_driver = {
	676	.probe = wcnss_probe,
	677	.remove = wcnss_remove,
	678	.driver = {
	679	.name = "qcom-wcnss-pil",
	680	.of_match_table = wcnss_of_match,
	681	},
	682	};
	683
6de1a507 BA	684	static int __init wcnss_init(void)
	685	{
	686	int ret;
	687
	688	ret = platform_driver_register(&wcnss_driver);
	689	if (ret)
	690	return ret;
	691
	692	ret = platform_driver_register(&qcom_iris_driver);
	693	if (ret)
	694	platform_driver_unregister(&wcnss_driver);
	695
	696	return ret;
	697	}
	698	module_init(wcnss_init);
	699
	700	static void __exit wcnss_exit(void)
	701	{
	702	platform_driver_unregister(&qcom_iris_driver);
	703	platform_driver_unregister(&wcnss_driver);
	704	}
	705	module_exit(wcnss_exit);
	706
fff7fca5	707	MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
aed361ad	708	MODULE_LICENSE("GPL v2");