[mirror_ubuntu-hirsute-kernel.git] / drivers / reset / reset-meson.c

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * Amlogic Meson Reset Controller driver
 *
 * Copyright (c) 2016 BayLibre, SAS.
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/of_device.h>

#define BITS_PER_REG	32

struct meson_reset_param {
	int reg_count;
	int level_offset;
};

struct meson_reset {
	void __iomem *reg_base;
	const struct meson_reset_param *param;
	struct reset_controller_dev rcdev;
	spinlock_t lock;
};

static int meson_reset_reset(struct reset_controller_dev *rcdev,
			      unsigned long id)
{
	struct meson_reset *data =
		container_of(rcdev, struct meson_reset, rcdev);
	unsigned int bank = id / BITS_PER_REG;
	unsigned int offset = id % BITS_PER_REG;
	void __iomem *reg_addr = data->reg_base + (bank << 2);

	writel(BIT(offset), reg_addr);

	return 0;
}

static int meson_reset_level(struct reset_controller_dev *rcdev,
			    unsigned long id, bool assert)
{
	struct meson_reset *data =
		container_of(rcdev, struct meson_reset, rcdev);
	unsigned int bank = id / BITS_PER_REG;
	unsigned int offset = id % BITS_PER_REG;
	void __iomem *reg_addr;
	unsigned long flags;
	u32 reg;

	reg_addr = data->reg_base + data->param->level_offset + (bank << 2);

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(reg_addr);
	if (assert)
		writel(reg & ~BIT(offset), reg_addr);
	else
		writel(reg | BIT(offset), reg_addr);

	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int meson_reset_assert(struct reset_controller_dev *rcdev,
			      unsigned long id)
{
	return meson_reset_level(rcdev, id, true);
}

static int meson_reset_deassert(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	return meson_reset_level(rcdev, id, false);
}

static const struct reset_control_ops meson_reset_ops = {
	.reset		= meson_reset_reset,
	.assert		= meson_reset_assert,
	.deassert	= meson_reset_deassert,
};

static const struct meson_reset_param meson8b_param = {
	.reg_count	= 8,
	.level_offset	= 0x7c,
};

static const struct meson_reset_param meson_a1_param = {
	.reg_count	= 3,
	.level_offset	= 0x40,
};

static const struct of_device_id meson_reset_dt_ids[] = {
	 { .compatible = "amlogic,meson8b-reset",    .data = &meson8b_param},
	 { .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
	 { .compatible = "amlogic,meson-axg-reset",  .data = &meson8b_param},
	 { .compatible = "amlogic,meson-a1-reset",   .data = &meson_a1_param},
	 { /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);

static int meson_reset_probe(struct platform_device *pdev)
{
	struct meson_reset *data;
	struct resource *res;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->reg_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(data->reg_base))
		return PTR_ERR(data->reg_base);

	data->param = of_device_get_match_data(&pdev->dev);
	if (!data->param)
		return -ENODEV;

	platform_set_drvdata(pdev, data);

	spin_lock_init(&data->lock);

	data->rcdev.owner = THIS_MODULE;
	data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
	data->rcdev.ops = &meson_reset_ops;
	data->rcdev.of_node = pdev->dev.of_node;

	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}

static struct platform_driver meson_reset_driver = {
	.probe	= meson_reset_probe,
	.driver = {
		.name		= "meson_reset",
		.of_match_table	= meson_reset_dt_ids,
	},
};
module_platform_driver(meson_reset_driver);

MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
7c61ccf6	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
c7224dc3	2	/*
8290924e PG	3	* Amlogic Meson Reset Controller driver
8290924e PG	4	*
c7224dc3 NA	5	* Copyright (c) 2016 BayLibre, SAS.
c7224dc3 NA	6	* Author: Neil Armstrong <narmstrong@baylibre.com>
c7224dc3 NA	7	*/
c7224dc3 NA	8	#include <linux/err.h>
8290924e	9	#include <linux/init.h>
c7224dc3 NA	10	#include <linux/io.h>
c7224dc3 NA	11	#include <linux/of.h>
3bfe8933	12	#include <linux/module.h>
c7224dc3 NA	13	#include <linux/platform_device.h>
	14	#include <linux/reset-controller.h>
	15	#include <linux/slab.h>
	16	#include <linux/types.h>
a5a10afe	17	#include <linux/of_device.h>
c7224dc3	18
c7224dc3	19	#define BITS_PER_REG 32
bdb369e1 XC	20
	21	struct meson_reset_param {
	22	int reg_count;
	23	int level_offset;
	24	};
c7224dc3 NA	25
	26	struct meson_reset {
	27	void __iomem *reg_base;
bdb369e1	28	const struct meson_reset_param *param;
c7224dc3	29	struct reset_controller_dev rcdev;
a5a10afe	30	spinlock_t lock;
c7224dc3 NA	31	};
	32
	33	static int meson_reset_reset(struct reset_controller_dev *rcdev,
	34	unsigned long id)
	35	{
	36	struct meson_reset *data =
	37	container_of(rcdev, struct meson_reset, rcdev);
	38	unsigned int bank = id / BITS_PER_REG;
	39	unsigned int offset = id % BITS_PER_REG;
	40	void __iomem *reg_addr = data->reg_base + (bank << 2);
	41
c7224dc3 NA	42	writel(BIT(offset), reg_addr);
	43
	44	return 0;
	45	}
	46
a5a10afe NA	47	static int meson_reset_level(struct reset_controller_dev *rcdev,
	48	unsigned long id, bool assert)
	49	{
	50	struct meson_reset *data =
	51	container_of(rcdev, struct meson_reset, rcdev);
	52	unsigned int bank = id / BITS_PER_REG;
	53	unsigned int offset = id % BITS_PER_REG;
bdb369e1	54	void __iomem *reg_addr;
a5a10afe NA	55	unsigned long flags;
	56	u32 reg;
	57
bdb369e1 XC	58	reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
bdb369e1 XC	59
a5a10afe NA	60	spin_lock_irqsave(&data->lock, flags);
	61
	62	reg = readl(reg_addr);
	63	if (assert)
	64	writel(reg & ~BIT(offset), reg_addr);
	65	else
	66	writel(reg \| BIT(offset), reg_addr);
	67
	68	spin_unlock_irqrestore(&data->lock, flags);
	69
	70	return 0;
	71	}
	72
	73	static int meson_reset_assert(struct reset_controller_dev *rcdev,
	74	unsigned long id)
	75	{
	76	return meson_reset_level(rcdev, id, true);
	77	}
	78
	79	static int meson_reset_deassert(struct reset_controller_dev *rcdev,
	80	unsigned long id)
	81	{
	82	return meson_reset_level(rcdev, id, false);
	83	}
	84
320da785	85	static const struct reset_control_ops meson_reset_ops = {
a5a10afe NA	86	.reset = meson_reset_reset,
	87	.assert = meson_reset_assert,
	88	.deassert = meson_reset_deassert,
	89	};
	90
bdb369e1 XC	91	static const struct meson_reset_param meson8b_param = {
	92	.reg_count = 8,
	93	.level_offset = 0x7c,
	94	};
	95
	96	static const struct meson_reset_param meson_a1_param = {
	97	.reg_count = 3,
	98	.level_offset = 0x40,
	99	};
	100
c7224dc3	101	static const struct of_device_id meson_reset_dt_ids[] = {
bdb369e1 XC	102	{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
	103	{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
	104	{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
	105	{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
c7224dc3 NA	106	{ /* sentinel */ },
c7224dc3 NA	107	};
3bfe8933	108	MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
c7224dc3 NA	109
	110	static int meson_reset_probe(struct platform_device *pdev)
	111	{
	112	struct meson_reset *data;
	113	struct resource *res;
	114
	115	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	116	if (!data)
	117	return -ENOMEM;
	118
	119	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	120	data->reg_base = devm_ioremap_resource(&pdev->dev, res);
	121	if (IS_ERR(data->reg_base))
	122	return PTR_ERR(data->reg_base);
	123
bdb369e1 XC	124	data->param = of_device_get_match_data(&pdev->dev);
	125	if (!data->param)
	126	return -ENODEV;
	127
c7224dc3 NA	128	platform_set_drvdata(pdev, data);
c7224dc3 NA	129
a5a10afe NA	130	spin_lock_init(&data->lock);
a5a10afe NA	131
c7224dc3	132	data->rcdev.owner = THIS_MODULE;
bdb369e1	133	data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
320da785	134	data->rcdev.ops = &meson_reset_ops;
c7224dc3 NA	135	data->rcdev.of_node = pdev->dev.of_node;
	136
	137	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
	138	}
	139
	140	static struct platform_driver meson_reset_driver = {
	141	.probe = meson_reset_probe,
	142	.driver = {
	143	.name = "meson_reset",
	144	.of_match_table = meson_reset_dt_ids,
	145	},
	146	};
3bfe8933 NA	147	module_platform_driver(meson_reset_driver);
	148
	149	MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
	150	MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
	151	MODULE_LICENSE("Dual BSD/GPL");