[mirror_ubuntu-bionic-kernel.git] / drivers / reset / reset-socfpga.c

/*
 * Socfpga Reset Controller Driver
 *
 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
 *
 * based on
 * Allwinner SoCs Reset Controller driver
 *
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define BANK_INCREMENT		4
#define NR_BANKS		8

struct socfpga_reset_data {
	spinlock_t			lock;
	void __iomem			*membase;
	struct reset_controller_dev	rcdev;
};

static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						     struct socfpga_reset_data,
						     rcdev);
	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(data->membase + (bank * BANK_INCREMENT));
	writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
				  unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						     struct socfpga_reset_data,
						     rcdev);

	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(data->membase + (bank * BANK_INCREMENT));
	writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));

	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int socfpga_reset_status(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						struct socfpga_reset_data, rcdev);
	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	u32 reg;

	reg = readl(data->membase + (bank * BANK_INCREMENT));

	return !(reg & BIT(offset));
}

static const struct reset_control_ops socfpga_reset_ops = {
	.assert		= socfpga_reset_assert,
	.deassert	= socfpga_reset_deassert,
	.status		= socfpga_reset_status,
};

static int socfpga_reset_probe(struct platform_device *pdev)
{
	struct socfpga_reset_data *data;
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	u32 modrst_offset;

	/*
	 * The binding was mainlined without the required property.
	 * Do not continue, when we encounter an old DT.
	 */
	if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
		dev_err(&pdev->dev, "%s missing #reset-cells property\n",
			pdev->dev.of_node->full_name);
		return -EINVAL;
	}

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->membase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(data->membase))
		return PTR_ERR(data->membase);

	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
		dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
		modrst_offset = 0x10;
	}
	data->membase += modrst_offset;

	spin_lock_init(&data->lock);

	data->rcdev.owner = THIS_MODULE;
	data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
	data->rcdev.ops = &socfpga_reset_ops;
	data->rcdev.of_node = pdev->dev.of_node;

	return devm_reset_controller_register(dev, &data->rcdev);
}

static const struct of_device_id socfpga_reset_dt_ids[] = {
	{ .compatible = "altr,rst-mgr", },
	{ /* sentinel */ },
};

static struct platform_driver socfpga_reset_driver = {
	.probe	= socfpga_reset_probe,
	.driver = {
		.name		= "socfpga-reset",
		.of_match_table	= socfpga_reset_dt_ids,
	},
};
builtin_platform_driver(socfpga_reset_driver);
Commit	Line	Data
a39a4939	1	/*
02163199 PG	2	* Socfpga Reset Controller Driver
02163199 PG	3	*
a39a4939 ST	4	* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
	5	*
	6	* based on
	7	* Allwinner SoCs Reset Controller driver
	8	*
	9	* Copyright 2013 Maxime Ripard
	10	*
	11	* Maxime Ripard <maxime.ripard@free-electrons.com>
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License, or
	16	* (at your option) any later version.
	17	*/
	18
	19	#include <linux/err.h>
	20	#include <linux/io.h>
02163199	21	#include <linux/init.h>
a39a4939 ST	22	#include <linux/of.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/reset-controller.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
	27
d518d9ca RI	28	#define BANK_INCREMENT 4
d518d9ca RI	29	#define NR_BANKS 8
a39a4939 ST	30
	31	struct socfpga_reset_data {
	32	spinlock_t lock;
	33	void __iomem *membase;
	34	struct reset_controller_dev rcdev;
	35	};
	36
	37	static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
	38	unsigned long id)
	39	{
	40	struct socfpga_reset_data *data = container_of(rcdev,
	41	struct socfpga_reset_data,
	42	rcdev);
	43	int bank = id / BITS_PER_LONG;
	44	int offset = id % BITS_PER_LONG;
	45	unsigned long flags;
	46	u32 reg;
	47
	48	spin_lock_irqsave(&data->lock, flags);
	49
d518d9ca RI	50	reg = readl(data->membase + (bank * BANK_INCREMENT));
d518d9ca RI	51	writel(reg \| BIT(offset), data->membase + (bank * BANK_INCREMENT));
a39a4939 ST	52	spin_unlock_irqrestore(&data->lock, flags);
	53
	54	return 0;
	55	}
	56
	57	static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
	58	unsigned long id)
	59	{
	60	struct socfpga_reset_data *data = container_of(rcdev,
	61	struct socfpga_reset_data,
	62	rcdev);
	63
	64	int bank = id / BITS_PER_LONG;
	65	int offset = id % BITS_PER_LONG;
	66	unsigned long flags;
	67	u32 reg;
	68
	69	spin_lock_irqsave(&data->lock, flags);
	70
d518d9ca RI	71	reg = readl(data->membase + (bank * BANK_INCREMENT));
d518d9ca RI	72	writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
a39a4939 ST	73
	74	spin_unlock_irqrestore(&data->lock, flags);
	75
	76	return 0;
	77	}
	78
f200890f DN	79	static int socfpga_reset_status(struct reset_controller_dev *rcdev,
	80	unsigned long id)
	81	{
	82	struct socfpga_reset_data *data = container_of(rcdev,
	83	struct socfpga_reset_data, rcdev);
	84	int bank = id / BITS_PER_LONG;
	85	int offset = id % BITS_PER_LONG;
	86	u32 reg;
	87
d518d9ca	88	reg = readl(data->membase + (bank * BANK_INCREMENT));
f200890f DN	89
	90	return !(reg & BIT(offset));
	91	}
	92
387eb3f3	93	static const struct reset_control_ops socfpga_reset_ops = {
a39a4939 ST	94	.assert = socfpga_reset_assert,
a39a4939 ST	95	.deassert = socfpga_reset_deassert,
f200890f	96	.status = socfpga_reset_status,
a39a4939 ST	97	};
	98
	99	static int socfpga_reset_probe(struct platform_device *pdev)
	100	{
	101	struct socfpga_reset_data *data;
	102	struct resource *res;
27e44646 DN	103	struct device *dev = &pdev->dev;
27e44646 DN	104	struct device_node *np = dev->of_node;
6b37d3e9	105	u32 modrst_offset;
a39a4939 ST	106
	107	/*
	108	* The binding was mainlined without the required property.
	109	* Do not continue, when we encounter an old DT.
	110	*/
	111	if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
	112	dev_err(&pdev->dev, "%s missing #reset-cells property\n",
	113	pdev->dev.of_node->full_name);
	114	return -EINVAL;
	115	}
	116
	117	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	118	if (!data)
	119	return -ENOMEM;
	120
	121	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	122	data->membase = devm_ioremap_resource(&pdev->dev, res);
	123	if (IS_ERR(data->membase))
	124	return PTR_ERR(data->membase);
	125
6b37d3e9	126	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
27e44646	127	dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
6b37d3e9	128	modrst_offset = 0x10;
27e44646	129	}
6b37d3e9	130	data->membase += modrst_offset;
27e44646	131
a39a4939 ST	132	spin_lock_init(&data->lock);
	133
	134	data->rcdev.owner = THIS_MODULE;
	135	data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
	136	data->rcdev.ops = &socfpga_reset_ops;
	137	data->rcdev.of_node = pdev->dev.of_node;
a39a4939	138
dc22e08e	139	return devm_reset_controller_register(dev, &data->rcdev);
a39a4939 ST	140	}
	141
	142	static const struct of_device_id socfpga_reset_dt_ids[] = {
	143	{ .compatible = "altr,rst-mgr", },
	144	{ /* sentinel */ },
	145	};
	146
	147	static struct platform_driver socfpga_reset_driver = {
	148	.probe = socfpga_reset_probe,
a39a4939 ST	149	.driver = {
a39a4939 ST	150	.name = "socfpga-reset",
a39a4939 ST	151	.of_match_table = socfpga_reset_dt_ids,
	152	},
	153	};
02163199	154	builtin_platform_driver(socfpga_reset_driver);