[mirror_ubuntu-zesty-kernel.git] / drivers / reset / reset-socfpga.c

/*
 * Socfpga Reset Controller Driver
 *
 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
 *
 * based on
 * Allwinner SoCs Reset Controller driver
 *
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define NR_BANKS		4

struct socfpga_reset_data {
	spinlock_t			lock;
	void __iomem			*membase;
	struct reset_controller_dev	rcdev;
};

static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						     struct socfpga_reset_data,
						     rcdev);
	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(data->membase + (bank * NR_BANKS));
	writel(reg | BIT(offset), data->membase + (bank * NR_BANKS));
	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
				  unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						     struct socfpga_reset_data,
						     rcdev);

	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(data->membase + (bank * NR_BANKS));
	writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS));

	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int socfpga_reset_status(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						struct socfpga_reset_data, rcdev);
	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	u32 reg;

	reg = readl(data->membase + (bank * NR_BANKS));

	return !(reg & BIT(offset));
}

static const struct reset_control_ops socfpga_reset_ops = {
	.assert		= socfpga_reset_assert,
	.deassert	= socfpga_reset_deassert,
	.status		= socfpga_reset_status,
};

static int socfpga_reset_probe(struct platform_device *pdev)
{
	struct socfpga_reset_data *data;
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	u32 modrst_offset;

	/*
	 * The binding was mainlined without the required property.
	 * Do not continue, when we encounter an old DT.
	 */
	if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
		dev_err(&pdev->dev, "%s missing #reset-cells property\n",
			pdev->dev.of_node->full_name);
		return -EINVAL;
	}

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->membase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(data->membase))
		return PTR_ERR(data->membase);

	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
		dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
		modrst_offset = 0x10;
	}
	data->membase += modrst_offset;

	spin_lock_init(&data->lock);

	data->rcdev.owner = THIS_MODULE;
	data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
	data->rcdev.ops = &socfpga_reset_ops;
	data->rcdev.of_node = pdev->dev.of_node;

	return devm_reset_controller_register(dev, &data->rcdev);
}

static const struct of_device_id socfpga_reset_dt_ids[] = {
	{ .compatible = "altr,rst-mgr", },
	{ /* sentinel */ },
};

static struct platform_driver socfpga_reset_driver = {
	.probe	= socfpga_reset_probe,
	.driver = {
		.name		= "socfpga-reset",
		.of_match_table	= socfpga_reset_dt_ids,
	},
};
builtin_platform_driver(socfpga_reset_driver);
Commit	Line	Data
a39a4939	1	/*
02163199 PG	2	* Socfpga Reset Controller Driver
02163199 PG	3	*
a39a4939 ST	4	* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
	5	*
	6	* based on
	7	* Allwinner SoCs Reset Controller driver
	8	*
	9	* Copyright 2013 Maxime Ripard
	10	*
	11	* Maxime Ripard <maxime.ripard@free-electrons.com>
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License, or
	16	* (at your option) any later version.
	17	*/
	18
	19	#include <linux/err.h>
	20	#include <linux/io.h>
02163199	21	#include <linux/init.h>
a39a4939 ST	22	#include <linux/of.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/reset-controller.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
	27
	28	#define NR_BANKS 4
a39a4939 ST	29
	30	struct socfpga_reset_data {
	31	spinlock_t lock;
	32	void __iomem *membase;
	33	struct reset_controller_dev rcdev;
	34	};
	35
	36	static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
	37	unsigned long id)
	38	{
	39	struct socfpga_reset_data *data = container_of(rcdev,
	40	struct socfpga_reset_data,
	41	rcdev);
	42	int bank = id / BITS_PER_LONG;
	43	int offset = id % BITS_PER_LONG;
	44	unsigned long flags;
	45	u32 reg;
	46
	47	spin_lock_irqsave(&data->lock, flags);
	48
6b37d3e9 PZ	49	reg = readl(data->membase + (bank * NR_BANKS));
6b37d3e9 PZ	50	writel(reg \| BIT(offset), data->membase + (bank * NR_BANKS));
a39a4939 ST	51	spin_unlock_irqrestore(&data->lock, flags);
	52
	53	return 0;
	54	}
	55
	56	static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
	57	unsigned long id)
	58	{
	59	struct socfpga_reset_data *data = container_of(rcdev,
	60	struct socfpga_reset_data,
	61	rcdev);
	62
	63	int bank = id / BITS_PER_LONG;
	64	int offset = id % BITS_PER_LONG;
	65	unsigned long flags;
	66	u32 reg;
	67
	68	spin_lock_irqsave(&data->lock, flags);
	69
6b37d3e9 PZ	70	reg = readl(data->membase + (bank * NR_BANKS));
6b37d3e9 PZ	71	writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS));
a39a4939 ST	72
	73	spin_unlock_irqrestore(&data->lock, flags);
	74
	75	return 0;
	76	}
	77
f200890f DN	78	static int socfpga_reset_status(struct reset_controller_dev *rcdev,
	79	unsigned long id)
	80	{
	81	struct socfpga_reset_data *data = container_of(rcdev,
	82	struct socfpga_reset_data, rcdev);
	83	int bank = id / BITS_PER_LONG;
	84	int offset = id % BITS_PER_LONG;
	85	u32 reg;
	86
6b37d3e9	87	reg = readl(data->membase + (bank * NR_BANKS));
f200890f DN	88
	89	return !(reg & BIT(offset));
	90	}
	91
387eb3f3	92	static const struct reset_control_ops socfpga_reset_ops = {
a39a4939 ST	93	.assert = socfpga_reset_assert,
a39a4939 ST	94	.deassert = socfpga_reset_deassert,
f200890f	95	.status = socfpga_reset_status,
a39a4939 ST	96	};
	97
	98	static int socfpga_reset_probe(struct platform_device *pdev)
	99	{
	100	struct socfpga_reset_data *data;
	101	struct resource *res;
27e44646 DN	102	struct device *dev = &pdev->dev;
27e44646 DN	103	struct device_node *np = dev->of_node;
6b37d3e9	104	u32 modrst_offset;
a39a4939 ST	105
	106	/*
	107	* The binding was mainlined without the required property.
	108	* Do not continue, when we encounter an old DT.
	109	*/
	110	if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
	111	dev_err(&pdev->dev, "%s missing #reset-cells property\n",
	112	pdev->dev.of_node->full_name);
	113	return -EINVAL;
	114	}
	115
	116	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	117	if (!data)
	118	return -ENOMEM;
	119
	120	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	121	data->membase = devm_ioremap_resource(&pdev->dev, res);
	122	if (IS_ERR(data->membase))
	123	return PTR_ERR(data->membase);
	124
6b37d3e9	125	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
27e44646	126	dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
6b37d3e9	127	modrst_offset = 0x10;
27e44646	128	}
6b37d3e9	129	data->membase += modrst_offset;
27e44646	130
a39a4939 ST	131	spin_lock_init(&data->lock);
	132
	133	data->rcdev.owner = THIS_MODULE;
	134	data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
	135	data->rcdev.ops = &socfpga_reset_ops;
	136	data->rcdev.of_node = pdev->dev.of_node;
a39a4939	137
dc22e08e	138	return devm_reset_controller_register(dev, &data->rcdev);
a39a4939 ST	139	}
	140
	141	static const struct of_device_id socfpga_reset_dt_ids[] = {
	142	{ .compatible = "altr,rst-mgr", },
	143	{ /* sentinel */ },
	144	};
	145
	146	static struct platform_driver socfpga_reset_driver = {
	147	.probe = socfpga_reset_probe,
a39a4939 ST	148	.driver = {
a39a4939 ST	149	.name = "socfpga-reset",
a39a4939 ST	150	.of_match_table = socfpga_reset_dt_ids,
	151	},
	152	};
02163199	153	builtin_platform_driver(socfpga_reset_driver);