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54e991b5 MY |
1 | /* |
2 | * Copyright (C) 2016 Socionext Inc. | |
3 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_device.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/reset-controller.h> | |
23 | ||
24 | struct uniphier_reset_data { | |
25 | unsigned int id; | |
26 | unsigned int reg; | |
27 | unsigned int bit; | |
28 | unsigned int flags; | |
29 | #define UNIPHIER_RESET_ACTIVE_LOW BIT(0) | |
30 | }; | |
31 | ||
32 | #define UNIPHIER_RESET_ID_END (unsigned int)(-1) | |
33 | ||
34 | #define UNIPHIER_RESET_END \ | |
35 | { .id = UNIPHIER_RESET_ID_END } | |
36 | ||
37 | #define UNIPHIER_RESET(_id, _reg, _bit) \ | |
38 | { \ | |
39 | .id = (_id), \ | |
40 | .reg = (_reg), \ | |
41 | .bit = (_bit), \ | |
42 | } | |
43 | ||
44 | #define UNIPHIER_RESETX(_id, _reg, _bit) \ | |
45 | { \ | |
46 | .id = (_id), \ | |
47 | .reg = (_reg), \ | |
48 | .bit = (_bit), \ | |
49 | .flags = UNIPHIER_RESET_ACTIVE_LOW, \ | |
50 | } | |
51 | ||
52 | /* System reset data */ | |
5281036a MY |
53 | static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = { |
54 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ | |
55 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */ | |
54e991b5 MY |
56 | UNIPHIER_RESET_END, |
57 | }; | |
58 | ||
716adfe3 | 59 | static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { |
5281036a | 60 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
4c05c4a5 | 61 | UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */ |
5281036a | 62 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */ |
dec173cc MY |
63 | UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */ |
64 | UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ | |
65 | UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ | |
54e991b5 MY |
66 | UNIPHIER_RESET_END, |
67 | }; | |
68 | ||
716adfe3 | 69 | static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { |
5281036a MY |
70 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
71 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC) */ | |
dec173cc MY |
72 | UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */ |
73 | UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ | |
74 | UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ | |
54e991b5 MY |
75 | UNIPHIER_RESET_END, |
76 | }; | |
77 | ||
716adfe3 | 78 | static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { |
5281036a | 79 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
4c05c4a5 | 80 | UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */ |
5281036a | 81 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, RLE) */ |
dec173cc MY |
82 | UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ |
83 | UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ | |
54e991b5 MY |
84 | UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */ |
85 | UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */ | |
86 | UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */ | |
87 | UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ | |
88 | UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */ | |
89 | UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */ | |
90 | UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */ | |
91 | UNIPHIER_RESET_END, | |
92 | }; | |
93 | ||
716adfe3 | 94 | static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { |
dec173cc MY |
95 | UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ |
96 | UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ | |
4c05c4a5 | 97 | UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */ |
dec173cc | 98 | UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */ |
94e10c22 KS |
99 | UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */ |
100 | UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */ | |
0f195435 | 101 | UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */ |
54e991b5 MY |
102 | UNIPHIER_RESET_END, |
103 | }; | |
104 | ||
716adfe3 | 105 | static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { |
dec173cc MY |
106 | UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ |
107 | UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ | |
4c05c4a5 | 108 | UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */ |
dec173cc | 109 | UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */ |
33918750 | 110 | UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */ |
54e991b5 MY |
111 | UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ |
112 | UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ | |
113 | UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ | |
114 | UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */ | |
94e10c22 KS |
115 | UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */ |
116 | UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */ | |
0f195435 | 117 | UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */ |
54e991b5 MY |
118 | UNIPHIER_RESET_END, |
119 | }; | |
120 | ||
2a158f88 MY |
121 | static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { |
122 | UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ | |
123 | UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ | |
124 | UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ | |
33918750 MY |
125 | UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */ |
126 | UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */ | |
2a158f88 MY |
127 | UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */ |
128 | UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */ | |
129 | UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ | |
130 | UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ | |
131 | UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ | |
132 | UNIPHIER_RESET_END, | |
133 | }; | |
134 | ||
54e991b5 MY |
135 | /* Media I/O reset data */ |
136 | #define UNIPHIER_MIO_RESET_SD(id, ch) \ | |
137 | UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) | |
138 | ||
139 | #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ | |
140 | UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26) | |
141 | ||
142 | #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ | |
143 | UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0) | |
144 | ||
145 | #define UNIPHIER_MIO_RESET_USB2(id, ch) \ | |
146 | UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0) | |
147 | ||
148 | #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ | |
149 | UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24) | |
150 | ||
151 | #define UNIPHIER_MIO_RESET_DMAC(id) \ | |
152 | UNIPHIER_RESETX((id), 0x110, 17) | |
153 | ||
5281036a | 154 | static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = { |
54e991b5 MY |
155 | UNIPHIER_MIO_RESET_SD(0, 0), |
156 | UNIPHIER_MIO_RESET_SD(1, 1), | |
157 | UNIPHIER_MIO_RESET_SD(2, 2), | |
158 | UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0), | |
159 | UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1), | |
160 | UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2), | |
161 | UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), | |
162 | UNIPHIER_MIO_RESET_DMAC(7), | |
163 | UNIPHIER_MIO_RESET_USB2(8, 0), | |
164 | UNIPHIER_MIO_RESET_USB2(9, 1), | |
165 | UNIPHIER_MIO_RESET_USB2(10, 2), | |
54e991b5 MY |
166 | UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0), |
167 | UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1), | |
168 | UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2), | |
54e991b5 MY |
169 | UNIPHIER_RESET_END, |
170 | }; | |
171 | ||
716adfe3 | 172 | static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { |
54e991b5 MY |
173 | UNIPHIER_MIO_RESET_SD(0, 0), |
174 | UNIPHIER_MIO_RESET_SD(1, 1), | |
175 | UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), | |
176 | UNIPHIER_RESET_END, | |
177 | }; | |
178 | ||
179 | /* Peripheral reset data */ | |
180 | #define UNIPHIER_PERI_RESET_UART(id, ch) \ | |
181 | UNIPHIER_RESETX((id), 0x114, 19 + (ch)) | |
182 | ||
183 | #define UNIPHIER_PERI_RESET_I2C(id, ch) \ | |
184 | UNIPHIER_RESETX((id), 0x114, 5 + (ch)) | |
185 | ||
186 | #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ | |
187 | UNIPHIER_RESETX((id), 0x114, 24 + (ch)) | |
188 | ||
716adfe3 | 189 | static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { |
54e991b5 MY |
190 | UNIPHIER_PERI_RESET_UART(0, 0), |
191 | UNIPHIER_PERI_RESET_UART(1, 1), | |
192 | UNIPHIER_PERI_RESET_UART(2, 2), | |
193 | UNIPHIER_PERI_RESET_UART(3, 3), | |
194 | UNIPHIER_PERI_RESET_I2C(4, 0), | |
195 | UNIPHIER_PERI_RESET_I2C(5, 1), | |
196 | UNIPHIER_PERI_RESET_I2C(6, 2), | |
197 | UNIPHIER_PERI_RESET_I2C(7, 3), | |
198 | UNIPHIER_PERI_RESET_I2C(8, 4), | |
199 | UNIPHIER_RESET_END, | |
200 | }; | |
201 | ||
716adfe3 | 202 | static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { |
54e991b5 MY |
203 | UNIPHIER_PERI_RESET_UART(0, 0), |
204 | UNIPHIER_PERI_RESET_UART(1, 1), | |
205 | UNIPHIER_PERI_RESET_UART(2, 2), | |
206 | UNIPHIER_PERI_RESET_UART(3, 3), | |
207 | UNIPHIER_PERI_RESET_FI2C(4, 0), | |
208 | UNIPHIER_PERI_RESET_FI2C(5, 1), | |
209 | UNIPHIER_PERI_RESET_FI2C(6, 2), | |
210 | UNIPHIER_PERI_RESET_FI2C(7, 3), | |
211 | UNIPHIER_PERI_RESET_FI2C(8, 4), | |
212 | UNIPHIER_PERI_RESET_FI2C(9, 5), | |
213 | UNIPHIER_PERI_RESET_FI2C(10, 6), | |
214 | UNIPHIER_RESET_END, | |
215 | }; | |
216 | ||
ac0c735a KS |
217 | /* Analog signal amplifiers reset data */ |
218 | static const struct uniphier_reset_data uniphier_ld11_adamv_reset_data[] = { | |
219 | UNIPHIER_RESETX(0, 0x10, 6), /* EVEA */ | |
220 | UNIPHIER_RESET_END, | |
221 | }; | |
222 | ||
54e991b5 MY |
223 | /* core implementaton */ |
224 | struct uniphier_reset_priv { | |
225 | struct reset_controller_dev rcdev; | |
226 | struct device *dev; | |
227 | struct regmap *regmap; | |
228 | const struct uniphier_reset_data *data; | |
229 | }; | |
230 | ||
231 | #define to_uniphier_reset_priv(_rcdev) \ | |
232 | container_of(_rcdev, struct uniphier_reset_priv, rcdev) | |
233 | ||
234 | static int uniphier_reset_update(struct reset_controller_dev *rcdev, | |
235 | unsigned long id, int assert) | |
236 | { | |
237 | struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev); | |
238 | const struct uniphier_reset_data *p; | |
239 | ||
240 | for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { | |
241 | unsigned int mask, val; | |
242 | ||
243 | if (p->id != id) | |
244 | continue; | |
245 | ||
246 | mask = BIT(p->bit); | |
247 | ||
248 | if (assert) | |
249 | val = mask; | |
250 | else | |
251 | val = ~mask; | |
252 | ||
253 | if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) | |
254 | val = ~val; | |
255 | ||
256 | return regmap_write_bits(priv->regmap, p->reg, mask, val); | |
257 | } | |
258 | ||
259 | dev_err(priv->dev, "reset_id=%lu was not handled\n", id); | |
260 | return -EINVAL; | |
261 | } | |
262 | ||
263 | static int uniphier_reset_assert(struct reset_controller_dev *rcdev, | |
264 | unsigned long id) | |
265 | { | |
266 | return uniphier_reset_update(rcdev, id, 1); | |
267 | } | |
268 | ||
269 | static int uniphier_reset_deassert(struct reset_controller_dev *rcdev, | |
270 | unsigned long id) | |
271 | { | |
272 | return uniphier_reset_update(rcdev, id, 0); | |
273 | } | |
274 | ||
275 | static int uniphier_reset_status(struct reset_controller_dev *rcdev, | |
276 | unsigned long id) | |
277 | { | |
278 | struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev); | |
279 | const struct uniphier_reset_data *p; | |
280 | ||
281 | for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { | |
282 | unsigned int val; | |
283 | int ret, asserted; | |
284 | ||
285 | if (p->id != id) | |
286 | continue; | |
287 | ||
288 | ret = regmap_read(priv->regmap, p->reg, &val); | |
289 | if (ret) | |
290 | return ret; | |
291 | ||
292 | asserted = !!(val & BIT(p->bit)); | |
293 | ||
294 | if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) | |
295 | asserted = !asserted; | |
296 | ||
297 | return asserted; | |
298 | } | |
299 | ||
300 | dev_err(priv->dev, "reset_id=%lu was not found\n", id); | |
301 | return -EINVAL; | |
302 | } | |
303 | ||
304 | static const struct reset_control_ops uniphier_reset_ops = { | |
305 | .assert = uniphier_reset_assert, | |
306 | .deassert = uniphier_reset_deassert, | |
307 | .status = uniphier_reset_status, | |
308 | }; | |
309 | ||
310 | static int uniphier_reset_probe(struct platform_device *pdev) | |
311 | { | |
312 | struct device *dev = &pdev->dev; | |
313 | struct uniphier_reset_priv *priv; | |
314 | const struct uniphier_reset_data *p, *data; | |
315 | struct regmap *regmap; | |
316 | struct device_node *parent; | |
317 | unsigned int nr_resets = 0; | |
318 | ||
319 | data = of_device_get_match_data(dev); | |
320 | if (WARN_ON(!data)) | |
321 | return -EINVAL; | |
322 | ||
323 | parent = of_get_parent(dev->of_node); /* parent should be syscon node */ | |
324 | regmap = syscon_node_to_regmap(parent); | |
325 | of_node_put(parent); | |
326 | if (IS_ERR(regmap)) { | |
327 | dev_err(dev, "failed to get regmap (error %ld)\n", | |
328 | PTR_ERR(regmap)); | |
329 | return PTR_ERR(regmap); | |
330 | } | |
331 | ||
332 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
333 | if (!priv) | |
334 | return -ENOMEM; | |
335 | ||
336 | for (p = data; p->id != UNIPHIER_RESET_ID_END; p++) | |
337 | nr_resets = max(nr_resets, p->id + 1); | |
338 | ||
339 | priv->rcdev.ops = &uniphier_reset_ops; | |
340 | priv->rcdev.owner = dev->driver->owner; | |
341 | priv->rcdev.of_node = dev->of_node; | |
342 | priv->rcdev.nr_resets = nr_resets; | |
343 | priv->dev = dev; | |
344 | priv->regmap = regmap; | |
345 | priv->data = data; | |
346 | ||
347 | return devm_reset_controller_register(&pdev->dev, &priv->rcdev); | |
348 | } | |
349 | ||
350 | static const struct of_device_id uniphier_reset_match[] = { | |
351 | /* System reset */ | |
54e991b5 MY |
352 | { |
353 | .compatible = "socionext,uniphier-ld4-reset", | |
5281036a | 354 | .data = uniphier_ld4_sys_reset_data, |
54e991b5 MY |
355 | }, |
356 | { | |
357 | .compatible = "socionext,uniphier-pro4-reset", | |
358 | .data = uniphier_pro4_sys_reset_data, | |
359 | }, | |
360 | { | |
361 | .compatible = "socionext,uniphier-sld8-reset", | |
5281036a | 362 | .data = uniphier_ld4_sys_reset_data, |
54e991b5 MY |
363 | }, |
364 | { | |
365 | .compatible = "socionext,uniphier-pro5-reset", | |
366 | .data = uniphier_pro5_sys_reset_data, | |
367 | }, | |
368 | { | |
369 | .compatible = "socionext,uniphier-pxs2-reset", | |
370 | .data = uniphier_pxs2_sys_reset_data, | |
371 | }, | |
372 | { | |
373 | .compatible = "socionext,uniphier-ld11-reset", | |
374 | .data = uniphier_ld11_sys_reset_data, | |
375 | }, | |
376 | { | |
377 | .compatible = "socionext,uniphier-ld20-reset", | |
378 | .data = uniphier_ld20_sys_reset_data, | |
379 | }, | |
2a158f88 MY |
380 | { |
381 | .compatible = "socionext,uniphier-pxs3-reset", | |
382 | .data = uniphier_pxs3_sys_reset_data, | |
383 | }, | |
19eb4a47 | 384 | /* Media I/O reset, SD reset */ |
54e991b5 MY |
385 | { |
386 | .compatible = "socionext,uniphier-ld4-mio-reset", | |
5281036a | 387 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 MY |
388 | }, |
389 | { | |
390 | .compatible = "socionext,uniphier-pro4-mio-reset", | |
5281036a | 391 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 MY |
392 | }, |
393 | { | |
394 | .compatible = "socionext,uniphier-sld8-mio-reset", | |
5281036a | 395 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 MY |
396 | }, |
397 | { | |
19eb4a47 MY |
398 | .compatible = "socionext,uniphier-pro5-sd-reset", |
399 | .data = uniphier_pro5_sd_reset_data, | |
54e991b5 MY |
400 | }, |
401 | { | |
19eb4a47 MY |
402 | .compatible = "socionext,uniphier-pxs2-sd-reset", |
403 | .data = uniphier_pro5_sd_reset_data, | |
54e991b5 MY |
404 | }, |
405 | { | |
406 | .compatible = "socionext,uniphier-ld11-mio-reset", | |
5281036a | 407 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 | 408 | }, |
88a7f523 MY |
409 | { |
410 | .compatible = "socionext,uniphier-ld11-sd-reset", | |
411 | .data = uniphier_pro5_sd_reset_data, | |
412 | }, | |
54e991b5 | 413 | { |
19eb4a47 MY |
414 | .compatible = "socionext,uniphier-ld20-sd-reset", |
415 | .data = uniphier_pro5_sd_reset_data, | |
54e991b5 | 416 | }, |
2a158f88 MY |
417 | { |
418 | .compatible = "socionext,uniphier-pxs3-sd-reset", | |
419 | .data = uniphier_pro5_sd_reset_data, | |
420 | }, | |
54e991b5 MY |
421 | /* Peripheral reset */ |
422 | { | |
423 | .compatible = "socionext,uniphier-ld4-peri-reset", | |
424 | .data = uniphier_ld4_peri_reset_data, | |
425 | }, | |
426 | { | |
427 | .compatible = "socionext,uniphier-pro4-peri-reset", | |
428 | .data = uniphier_pro4_peri_reset_data, | |
429 | }, | |
430 | { | |
431 | .compatible = "socionext,uniphier-sld8-peri-reset", | |
432 | .data = uniphier_ld4_peri_reset_data, | |
433 | }, | |
434 | { | |
435 | .compatible = "socionext,uniphier-pro5-peri-reset", | |
436 | .data = uniphier_pro4_peri_reset_data, | |
437 | }, | |
438 | { | |
439 | .compatible = "socionext,uniphier-pxs2-peri-reset", | |
440 | .data = uniphier_pro4_peri_reset_data, | |
441 | }, | |
442 | { | |
443 | .compatible = "socionext,uniphier-ld11-peri-reset", | |
444 | .data = uniphier_pro4_peri_reset_data, | |
445 | }, | |
446 | { | |
447 | .compatible = "socionext,uniphier-ld20-peri-reset", | |
448 | .data = uniphier_pro4_peri_reset_data, | |
449 | }, | |
2a158f88 MY |
450 | { |
451 | .compatible = "socionext,uniphier-pxs3-peri-reset", | |
452 | .data = uniphier_pro4_peri_reset_data, | |
453 | }, | |
ac0c735a KS |
454 | /* Analog signal amplifiers reset */ |
455 | { | |
456 | .compatible = "socionext,uniphier-ld11-adamv-reset", | |
457 | .data = uniphier_ld11_adamv_reset_data, | |
458 | }, | |
459 | { | |
460 | .compatible = "socionext,uniphier-ld20-adamv-reset", | |
461 | .data = uniphier_ld11_adamv_reset_data, | |
462 | }, | |
54e991b5 MY |
463 | { /* sentinel */ } |
464 | }; | |
465 | MODULE_DEVICE_TABLE(of, uniphier_reset_match); | |
466 | ||
467 | static struct platform_driver uniphier_reset_driver = { | |
468 | .probe = uniphier_reset_probe, | |
469 | .driver = { | |
470 | .name = "uniphier-reset", | |
471 | .of_match_table = uniphier_reset_match, | |
472 | }, | |
473 | }; | |
474 | module_platform_driver(uniphier_reset_driver); | |
475 | ||
476 | MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); | |
477 | MODULE_DESCRIPTION("UniPhier Reset Controller Driver"); | |
478 | MODULE_LICENSE("GPL"); |