[mirror_ubuntu-artful-kernel.git] / drivers / reset / reset-uniphier.c

/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>

struct uniphier_reset_data {
	unsigned int id;
	unsigned int reg;
	unsigned int bit;
	unsigned int flags;
#define UNIPHIER_RESET_ACTIVE_LOW		BIT(0)
};

#define UNIPHIER_RESET_ID_END		(unsigned int)(-1)

#define UNIPHIER_RESET_END				\
	{ .id = UNIPHIER_RESET_ID_END }

#define UNIPHIER_RESET(_id, _reg, _bit)			\
	{						\
		.id = (_id),				\
		.reg = (_reg),				\
		.bit = (_bit),				\
	}

#define UNIPHIER_RESETX(_id, _reg, _bit)		\
	{						\
		.id = (_id),				\
		.reg = (_reg),				\
		.bit = (_bit),				\
		.flags = UNIPHIER_RESET_ACTIVE_LOW,	\
	}

/* System reset data */
#define UNIPHIER_SLD3_SYS_RESET_NAND(id)		\
	UNIPHIER_RESETX((id), 0x2004, 2)

#define UNIPHIER_LD11_SYS_RESET_NAND(id)		\
	UNIPHIER_RESETX((id), 0x200c, 0)

#define UNIPHIER_LD11_SYS_RESET_EMMC(id)		\
	UNIPHIER_RESETX((id), 0x200c, 2)

#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id)		\
	UNIPHIER_RESETX((id), 0x2000, 10)

#define UNIPHIER_LD11_SYS_RESET_STDMAC(id)		\
	UNIPHIER_RESETX((id), 0x200c, 8)

#define UNIPHIER_PRO4_SYS_RESET_GIO(id)			\
	UNIPHIER_RESETX((id), 0x2000, 6)

#define UNIPHIER_LD20_SYS_RESET_GIO(id)			\
	UNIPHIER_RESETX((id), 0x200c, 5)

#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch)		\
	UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)

static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
	UNIPHIER_SLD3_SYS_RESET_NAND(2),
	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* Ether, HSC, MIO */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
	UNIPHIER_SLD3_SYS_RESET_NAND(2),
	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* HSC, MIO, RLE */
	UNIPHIER_PRO4_SYS_RESET_GIO(12),	/* Ether, SATA, USB3 */
	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
	UNIPHIER_SLD3_SYS_RESET_NAND(2),
	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* HSC */
	UNIPHIER_PRO4_SYS_RESET_GIO(12),	/* PCIe, USB3 */
	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
	UNIPHIER_SLD3_SYS_RESET_NAND(2),
	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* HSC, RLE */
	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
	UNIPHIER_RESETX(16, 0x2014, 4),		/* USB30-PHY0 */
	UNIPHIER_RESETX(17, 0x2014, 0),		/* USB30-PHY1 */
	UNIPHIER_RESETX(18, 0x2014, 2),		/* USB30-PHY2 */
	UNIPHIER_RESETX(20, 0x2014, 5),		/* USB31-PHY0 */
	UNIPHIER_RESETX(21, 0x2014, 1),		/* USB31-PHY1 */
	UNIPHIER_RESETX(28, 0x2014, 12),	/* SATA */
	UNIPHIER_RESET(29, 0x2014, 8),		/* SATA-PHY (active high) */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
	UNIPHIER_LD11_SYS_RESET_NAND(2),
	UNIPHIER_LD11_SYS_RESET_EMMC(4),
	UNIPHIER_LD11_SYS_RESET_STDMAC(8),	/* HSC, MIO */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
	UNIPHIER_LD11_SYS_RESET_NAND(2),
	UNIPHIER_LD11_SYS_RESET_EMMC(4),
	UNIPHIER_LD11_SYS_RESET_STDMAC(8),	/* HSC */
	UNIPHIER_LD20_SYS_RESET_GIO(12),	/* PCIe, USB3 */
	UNIPHIER_RESETX(16, 0x200c, 12),	/* USB30-PHY0 */
	UNIPHIER_RESETX(17, 0x200c, 13),	/* USB30-PHY1 */
	UNIPHIER_RESETX(18, 0x200c, 14),	/* USB30-PHY2 */
	UNIPHIER_RESETX(19, 0x200c, 15),	/* USB30-PHY3 */
	UNIPHIER_RESET_END,
};

/* Media I/O reset data */
#define UNIPHIER_MIO_RESET_SD(id, ch)			\
	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)

#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch)		\
	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)

#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch)	\
	UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)

#define UNIPHIER_MIO_RESET_USB2(id, ch)			\
	UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)

#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch)		\
	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)

#define UNIPHIER_MIO_RESET_DMAC(id)			\
	UNIPHIER_RESETX((id), 0x110, 17)

static const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
	UNIPHIER_MIO_RESET_SD(0, 0),
	UNIPHIER_MIO_RESET_SD(1, 1),
	UNIPHIER_MIO_RESET_SD(2, 2),
	UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
	UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
	UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	UNIPHIER_MIO_RESET_DMAC(7),
	UNIPHIER_MIO_RESET_USB2(8, 0),
	UNIPHIER_MIO_RESET_USB2(9, 1),
	UNIPHIER_MIO_RESET_USB2(10, 2),
	UNIPHIER_MIO_RESET_USB2(11, 3),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
	UNIPHIER_MIO_RESET_SD(0, 0),
	UNIPHIER_MIO_RESET_SD(1, 1),
	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	UNIPHIER_RESET_END,
};

/* Peripheral reset data */
#define UNIPHIER_PERI_RESET_UART(id, ch)		\
	UNIPHIER_RESETX((id), 0x114, 19 + (ch))

#define UNIPHIER_PERI_RESET_I2C(id, ch)			\
	UNIPHIER_RESETX((id), 0x114, 5 + (ch))

#define UNIPHIER_PERI_RESET_FI2C(id, ch)		\
	UNIPHIER_RESETX((id), 0x114, 24 + (ch))

static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
	UNIPHIER_PERI_RESET_UART(0, 0),
	UNIPHIER_PERI_RESET_UART(1, 1),
	UNIPHIER_PERI_RESET_UART(2, 2),
	UNIPHIER_PERI_RESET_UART(3, 3),
	UNIPHIER_PERI_RESET_I2C(4, 0),
	UNIPHIER_PERI_RESET_I2C(5, 1),
	UNIPHIER_PERI_RESET_I2C(6, 2),
	UNIPHIER_PERI_RESET_I2C(7, 3),
	UNIPHIER_PERI_RESET_I2C(8, 4),
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
	UNIPHIER_PERI_RESET_UART(0, 0),
	UNIPHIER_PERI_RESET_UART(1, 1),
	UNIPHIER_PERI_RESET_UART(2, 2),
	UNIPHIER_PERI_RESET_UART(3, 3),
	UNIPHIER_PERI_RESET_FI2C(4, 0),
	UNIPHIER_PERI_RESET_FI2C(5, 1),
	UNIPHIER_PERI_RESET_FI2C(6, 2),
	UNIPHIER_PERI_RESET_FI2C(7, 3),
	UNIPHIER_PERI_RESET_FI2C(8, 4),
	UNIPHIER_PERI_RESET_FI2C(9, 5),
	UNIPHIER_PERI_RESET_FI2C(10, 6),
	UNIPHIER_RESET_END,
};

/* core implementaton */
struct uniphier_reset_priv {
	struct reset_controller_dev rcdev;
	struct device *dev;
	struct regmap *regmap;
	const struct uniphier_reset_data *data;
};

#define to_uniphier_reset_priv(_rcdev) \
			container_of(_rcdev, struct uniphier_reset_priv, rcdev)

static int uniphier_reset_update(struct reset_controller_dev *rcdev,
				 unsigned long id, int assert)
{
	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
	const struct uniphier_reset_data *p;

	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
		unsigned int mask, val;

		if (p->id != id)
			continue;

		mask = BIT(p->bit);

		if (assert)
			val = mask;
		else
			val = ~mask;

		if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
			val = ~val;

		return regmap_write_bits(priv->regmap, p->reg, mask, val);
	}

	dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
	return -EINVAL;
}

static int uniphier_reset_assert(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	return uniphier_reset_update(rcdev, id, 1);
}

static int uniphier_reset_deassert(struct reset_controller_dev *rcdev,
				   unsigned long id)
{
	return uniphier_reset_update(rcdev, id, 0);
}

static int uniphier_reset_status(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
	const struct uniphier_reset_data *p;

	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
		unsigned int val;
		int ret, asserted;

		if (p->id != id)
			continue;

		ret = regmap_read(priv->regmap, p->reg, &val);
		if (ret)
			return ret;

		asserted = !!(val & BIT(p->bit));

		if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
			asserted = !asserted;

		return asserted;
	}

	dev_err(priv->dev, "reset_id=%lu was not found\n", id);
	return -EINVAL;
}

static const struct reset_control_ops uniphier_reset_ops = {
	.assert = uniphier_reset_assert,
	.deassert = uniphier_reset_deassert,
	.status = uniphier_reset_status,
};

static int uniphier_reset_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct uniphier_reset_priv *priv;
	const struct uniphier_reset_data *p, *data;
	struct regmap *regmap;
	struct device_node *parent;
	unsigned int nr_resets = 0;

	data = of_device_get_match_data(dev);
	if (WARN_ON(!data))
		return -EINVAL;

	parent = of_get_parent(dev->of_node); /* parent should be syscon node */
	regmap = syscon_node_to_regmap(parent);
	of_node_put(parent);
	if (IS_ERR(regmap)) {
		dev_err(dev, "failed to get regmap (error %ld)\n",
			PTR_ERR(regmap));
		return PTR_ERR(regmap);
	}

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	for (p = data; p->id != UNIPHIER_RESET_ID_END; p++)
		nr_resets = max(nr_resets, p->id + 1);

	priv->rcdev.ops = &uniphier_reset_ops;
	priv->rcdev.owner = dev->driver->owner;
	priv->rcdev.of_node = dev->of_node;
	priv->rcdev.nr_resets = nr_resets;
	priv->dev = dev;
	priv->regmap = regmap;
	priv->data = data;

	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
}

static const struct of_device_id uniphier_reset_match[] = {
	/* System reset */
	{
		.compatible = "socionext,uniphier-sld3-reset",
		.data = uniphier_sld3_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld4-reset",
		.data = uniphier_sld3_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-reset",
		.data = uniphier_pro4_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-reset",
		.data = uniphier_sld3_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-reset",
		.data = uniphier_pro5_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-reset",
		.data = uniphier_pxs2_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-reset",
		.data = uniphier_ld11_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-reset",
		.data = uniphier_ld20_sys_reset_data,
	},
	/* Media I/O reset, SD reset */
	{
		.compatible = "socionext,uniphier-sld3-mio-reset",
		.data = uniphier_sld3_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld4-mio-reset",
		.data = uniphier_sld3_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-mio-reset",
		.data = uniphier_sld3_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-mio-reset",
		.data = uniphier_sld3_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-mio-reset",
		.data = uniphier_sld3_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	/* Peripheral reset */
	{
		.compatible = "socionext,uniphier-ld4-peri-reset",
		.data = uniphier_ld4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-peri-reset",
		.data = uniphier_ld4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_reset_match);

static struct platform_driver uniphier_reset_driver = {
	.probe = uniphier_reset_probe,
	.driver = {
		.name = "uniphier-reset",
		.of_match_table = uniphier_reset_match,
	},
};
module_platform_driver(uniphier_reset_driver);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier Reset Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
54e991b5 MY	1	/*
	2	* Copyright (C) 2016 Socionext Inc.
	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/mfd/syscon.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_device.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22	#include <linux/reset-controller.h>
	23
	24	struct uniphier_reset_data {
	25	unsigned int id;
	26	unsigned int reg;
	27	unsigned int bit;
	28	unsigned int flags;
	29	#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
	30	};
	31
	32	#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
	33
	34	#define UNIPHIER_RESET_END \
	35	{ .id = UNIPHIER_RESET_ID_END }
	36
	37	#define UNIPHIER_RESET(_id, _reg, _bit) \
	38	{ \
	39	.id = (_id), \
	40	.reg = (_reg), \
	41	.bit = (_bit), \
	42	}
	43
	44	#define UNIPHIER_RESETX(_id, _reg, _bit) \
	45	{ \
	46	.id = (_id), \
	47	.reg = (_reg), \
	48	.bit = (_bit), \
	49	.flags = UNIPHIER_RESET_ACTIVE_LOW, \
	50	}
	51
	52	/* System reset data */
23ade398 MY	53	#define UNIPHIER_SLD3_SYS_RESET_NAND(id) \
	54	UNIPHIER_RESETX((id), 0x2004, 2)
	55
	56	#define UNIPHIER_LD11_SYS_RESET_NAND(id) \
	57	UNIPHIER_RESETX((id), 0x200c, 0)
	58
	59	#define UNIPHIER_LD11_SYS_RESET_EMMC(id) \
	60	UNIPHIER_RESETX((id), 0x200c, 2)
	61
54e991b5 MY	62	#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \
	63	UNIPHIER_RESETX((id), 0x2000, 10)
	64
	65	#define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \
	66	UNIPHIER_RESETX((id), 0x200c, 8)
	67
	68	#define UNIPHIER_PRO4_SYS_RESET_GIO(id) \
	69	UNIPHIER_RESETX((id), 0x2000, 6)
	70
	71	#define UNIPHIER_LD20_SYS_RESET_GIO(id) \
	72	UNIPHIER_RESETX((id), 0x200c, 5)
	73
	74	#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
	75	UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
	76
716adfe3	77	static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
23ade398	78	UNIPHIER_SLD3_SYS_RESET_NAND(2),
54e991b5 MY	79	UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
	80	UNIPHIER_RESET_END,
	81	};
	82
716adfe3	83	static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
23ade398	84	UNIPHIER_SLD3_SYS_RESET_NAND(2),
54e991b5 MY	85	UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
	86	UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
	87	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
	88	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
	89	UNIPHIER_RESET_END,
	90	};
	91
716adfe3	92	static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
23ade398	93	UNIPHIER_SLD3_SYS_RESET_NAND(2),
54e991b5 MY	94	UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
	95	UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
	96	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
	97	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
	98	UNIPHIER_RESET_END,
	99	};
	100
716adfe3	101	static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
23ade398	102	UNIPHIER_SLD3_SYS_RESET_NAND(2),
54e991b5 MY	103	UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
	104	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
	105	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
	106	UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
	107	UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
	108	UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
	109	UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
	110	UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
	111	UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
	112	UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
	113	UNIPHIER_RESET_END,
	114	};
	115
716adfe3	116	static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
23ade398 MY	117	UNIPHIER_LD11_SYS_RESET_NAND(2),
23ade398 MY	118	UNIPHIER_LD11_SYS_RESET_EMMC(4),
54e991b5 MY	119	UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
	120	UNIPHIER_RESET_END,
	121	};
	122
716adfe3	123	static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
23ade398 MY	124	UNIPHIER_LD11_SYS_RESET_NAND(2),
23ade398 MY	125	UNIPHIER_LD11_SYS_RESET_EMMC(4),
54e991b5 MY	126	UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
	127	UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
	128	UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
	129	UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
	130	UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
	131	UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
	132	UNIPHIER_RESET_END,
	133	};
	134
	135	/* Media I/O reset data */
	136	#define UNIPHIER_MIO_RESET_SD(id, ch) \
	137	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
	138
	139	#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
	140	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
	141
	142	#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
	143	UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
	144
	145	#define UNIPHIER_MIO_RESET_USB2(id, ch) \
	146	UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
	147
	148	#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
	149	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
	150
	151	#define UNIPHIER_MIO_RESET_DMAC(id) \
	152	UNIPHIER_RESETX((id), 0x110, 17)
	153
716adfe3	154	static const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
54e991b5 MY	155	UNIPHIER_MIO_RESET_SD(0, 0),
	156	UNIPHIER_MIO_RESET_SD(1, 1),
	157	UNIPHIER_MIO_RESET_SD(2, 2),
	158	UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
	159	UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
	160	UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
	161	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	162	UNIPHIER_MIO_RESET_DMAC(7),
	163	UNIPHIER_MIO_RESET_USB2(8, 0),
	164	UNIPHIER_MIO_RESET_USB2(9, 1),
	165	UNIPHIER_MIO_RESET_USB2(10, 2),
	166	UNIPHIER_MIO_RESET_USB2(11, 3),
	167	UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
	168	UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
	169	UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
	170	UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
	171	UNIPHIER_RESET_END,
	172	};
	173
716adfe3	174	static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
54e991b5 MY	175	UNIPHIER_MIO_RESET_SD(0, 0),
	176	UNIPHIER_MIO_RESET_SD(1, 1),
	177	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	178	UNIPHIER_RESET_END,
	179	};
	180
	181	/* Peripheral reset data */
	182	#define UNIPHIER_PERI_RESET_UART(id, ch) \
	183	UNIPHIER_RESETX((id), 0x114, 19 + (ch))
	184
	185	#define UNIPHIER_PERI_RESET_I2C(id, ch) \
	186	UNIPHIER_RESETX((id), 0x114, 5 + (ch))
	187
	188	#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
	189	UNIPHIER_RESETX((id), 0x114, 24 + (ch))
	190
716adfe3	191	static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
54e991b5 MY	192	UNIPHIER_PERI_RESET_UART(0, 0),
	193	UNIPHIER_PERI_RESET_UART(1, 1),
	194	UNIPHIER_PERI_RESET_UART(2, 2),
	195	UNIPHIER_PERI_RESET_UART(3, 3),
	196	UNIPHIER_PERI_RESET_I2C(4, 0),
	197	UNIPHIER_PERI_RESET_I2C(5, 1),
	198	UNIPHIER_PERI_RESET_I2C(6, 2),
	199	UNIPHIER_PERI_RESET_I2C(7, 3),
	200	UNIPHIER_PERI_RESET_I2C(8, 4),
	201	UNIPHIER_RESET_END,
	202	};
	203
716adfe3	204	static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
54e991b5 MY	205	UNIPHIER_PERI_RESET_UART(0, 0),
	206	UNIPHIER_PERI_RESET_UART(1, 1),
	207	UNIPHIER_PERI_RESET_UART(2, 2),
	208	UNIPHIER_PERI_RESET_UART(3, 3),
	209	UNIPHIER_PERI_RESET_FI2C(4, 0),
	210	UNIPHIER_PERI_RESET_FI2C(5, 1),
	211	UNIPHIER_PERI_RESET_FI2C(6, 2),
	212	UNIPHIER_PERI_RESET_FI2C(7, 3),
	213	UNIPHIER_PERI_RESET_FI2C(8, 4),
	214	UNIPHIER_PERI_RESET_FI2C(9, 5),
	215	UNIPHIER_PERI_RESET_FI2C(10, 6),
	216	UNIPHIER_RESET_END,
	217	};
	218
	219	/* core implementaton */
	220	struct uniphier_reset_priv {
	221	struct reset_controller_dev rcdev;
	222	struct device *dev;
	223	struct regmap *regmap;
	224	const struct uniphier_reset_data *data;
	225	};
	226
	227	#define to_uniphier_reset_priv(_rcdev) \
	228	container_of(_rcdev, struct uniphier_reset_priv, rcdev)
	229
	230	static int uniphier_reset_update(struct reset_controller_dev *rcdev,
	231	unsigned long id, int assert)
	232	{
	233	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
	234	const struct uniphier_reset_data *p;
	235
	236	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
	237	unsigned int mask, val;
	238
	239	if (p->id != id)
	240	continue;
	241
	242	mask = BIT(p->bit);
	243
	244	if (assert)
	245	val = mask;
	246	else
	247	val = ~mask;
	248
	249	if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
	250	val = ~val;
	251
	252	return regmap_write_bits(priv->regmap, p->reg, mask, val);
	253	}
	254
	255	dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
	256	return -EINVAL;
	257	}
	258
	259	static int uniphier_reset_assert(struct reset_controller_dev *rcdev,
	260	unsigned long id)
	261	{
	262	return uniphier_reset_update(rcdev, id, 1);
	263	}
	264
	265	static int uniphier_reset_deassert(struct reset_controller_dev *rcdev,
	266	unsigned long id)
	267	{
	268	return uniphier_reset_update(rcdev, id, 0);
269	}
270
271	static int uniphier_reset_status(struct reset_controller_dev *rcdev,
272	unsigned long id)
273	{
274	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
275	const struct uniphier_reset_data *p;
276
277	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
278	unsigned int val;
279	int ret, asserted;
280
281	if (p->id != id)
282	continue;
283
284	ret = regmap_read(priv->regmap, p->reg, &val);
285	if (ret)
286	return ret;
287
288	asserted = !!(val & BIT(p->bit));
289
290	if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
291	asserted = !asserted;
292
293	return asserted;
294	}
295
296	dev_err(priv->dev, "reset_id=%lu was not found\n", id);
297	return -EINVAL;
298	}
299
300	static const struct reset_control_ops uniphier_reset_ops = {
301	.assert = uniphier_reset_assert,
302	.deassert = uniphier_reset_deassert,
303	.status = uniphier_reset_status,
304	};
305
306	static int uniphier_reset_probe(struct platform_device *pdev)
307	{
308	struct device *dev = &pdev->dev;
309	struct uniphier_reset_priv *priv;
310	const struct uniphier_reset_data p, data;
311	struct regmap *regmap;
312	struct device_node *parent;
313	unsigned int nr_resets = 0;
314
315	data = of_device_get_match_data(dev);
316	if (WARN_ON(!data))
317	return -EINVAL;
318
319	parent = of_get_parent(dev->of_node); /* parent should be syscon node */
320	regmap = syscon_node_to_regmap(parent);
321	of_node_put(parent);
322	if (IS_ERR(regmap)) {
323	dev_err(dev, "failed to get regmap (error %ld)\n",
324	PTR_ERR(regmap));
325	return PTR_ERR(regmap);
326	}
327
328	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
329	if (!priv)
330	return -ENOMEM;
331
332	for (p = data; p->id != UNIPHIER_RESET_ID_END; p++)
333	nr_resets = max(nr_resets, p->id + 1);
334
335	priv->rcdev.ops = &uniphier_reset_ops;
336	priv->rcdev.owner = dev->driver->owner;
337	priv->rcdev.of_node = dev->of_node;
338	priv->rcdev.nr_resets = nr_resets;
339	priv->dev = dev;
340	priv->regmap = regmap;
341	priv->data = data;
342
343	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
344	}
345
346	static const struct of_device_id uniphier_reset_match[] = {
347	/* System reset */
348	{
349	.compatible = "socionext,uniphier-sld3-reset",
350	.data = uniphier_sld3_sys_reset_data,
351	},
352	{
353	.compatible = "socionext,uniphier-ld4-reset",
354	.data = uniphier_sld3_sys_reset_data,
355	},
356	{
357	.compatible = "socionext,uniphier-pro4-reset",
358	.data = uniphier_pro4_sys_reset_data,
359	},
360	{
361	.compatible = "socionext,uniphier-sld8-reset",
362	.data = uniphier_sld3_sys_reset_data,
363	},
364	{
365	.compatible = "socionext,uniphier-pro5-reset",
366	.data = uniphier_pro5_sys_reset_data,
367	},
368	{
369	.compatible = "socionext,uniphier-pxs2-reset",
370	.data = uniphier_pxs2_sys_reset_data,
371	},
372	{
373	.compatible = "socionext,uniphier-ld11-reset",
374	.data = uniphier_ld11_sys_reset_data,
375	},
376	{
377	.compatible = "socionext,uniphier-ld20-reset",
378	.data = uniphier_ld20_sys_reset_data,
379	},
19eb4a47	380	/* Media I/O reset, SD reset */
54e991b5 MY	381	{
	382	.compatible = "socionext,uniphier-sld3-mio-reset",
	383	.data = uniphier_sld3_mio_reset_data,
	384	},
	385	{
	386	.compatible = "socionext,uniphier-ld4-mio-reset",
	387	.data = uniphier_sld3_mio_reset_data,
	388	},
	389	{
	390	.compatible = "socionext,uniphier-pro4-mio-reset",
	391	.data = uniphier_sld3_mio_reset_data,
	392	},
	393	{
	394	.compatible = "socionext,uniphier-sld8-mio-reset",
	395	.data = uniphier_sld3_mio_reset_data,
	396	},
	397	{
19eb4a47 MY	398	.compatible = "socionext,uniphier-pro5-sd-reset",
19eb4a47 MY	399	.data = uniphier_pro5_sd_reset_data,
54e991b5 MY	400	},
54e991b5 MY	401	{
19eb4a47 MY	402	.compatible = "socionext,uniphier-pxs2-sd-reset",
19eb4a47 MY	403	.data = uniphier_pro5_sd_reset_data,
54e991b5 MY	404	},
	405	{
	406	.compatible = "socionext,uniphier-ld11-mio-reset",
	407	.data = uniphier_sld3_mio_reset_data,
	408	},
88a7f523 MY	409	{
	410	.compatible = "socionext,uniphier-ld11-sd-reset",
	411	.data = uniphier_pro5_sd_reset_data,
	412	},
54e991b5	413	{
19eb4a47 MY	414	.compatible = "socionext,uniphier-ld20-sd-reset",
19eb4a47 MY	415	.data = uniphier_pro5_sd_reset_data,
54e991b5 MY	416	},
	417	/* Peripheral reset */
	418	{
	419	.compatible = "socionext,uniphier-ld4-peri-reset",
	420	.data = uniphier_ld4_peri_reset_data,
	421	},
	422	{
	423	.compatible = "socionext,uniphier-pro4-peri-reset",
	424	.data = uniphier_pro4_peri_reset_data,
	425	},
	426	{
	427	.compatible = "socionext,uniphier-sld8-peri-reset",
	428	.data = uniphier_ld4_peri_reset_data,
	429	},
	430	{
	431	.compatible = "socionext,uniphier-pro5-peri-reset",
	432	.data = uniphier_pro4_peri_reset_data,
	433	},
	434	{
	435	.compatible = "socionext,uniphier-pxs2-peri-reset",
	436	.data = uniphier_pro4_peri_reset_data,
	437	},
	438	{
	439	.compatible = "socionext,uniphier-ld11-peri-reset",
	440	.data = uniphier_pro4_peri_reset_data,
	441	},
	442	{
	443	.compatible = "socionext,uniphier-ld20-peri-reset",
	444	.data = uniphier_pro4_peri_reset_data,
	445	},
	446	{ /* sentinel */ }
	447	};
	448	MODULE_DEVICE_TABLE(of, uniphier_reset_match);
	449
	450	static struct platform_driver uniphier_reset_driver = {
	451	.probe = uniphier_reset_probe,
	452	.driver = {
	453	.name = "uniphier-reset",
	454	.of_match_table = uniphier_reset_match,
	455	},
	456	};
	457	module_platform_driver(uniphier_reset_driver);
	458
	459	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
	460	MODULE_DESCRIPTION("UniPhier Reset Controller Driver");
	461	MODULE_LICENSE("GPL");