[mirror_ubuntu-jammy-kernel.git] / drivers / reset / reset-zynq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015, National Instruments Corp.
 *
 * Xilinx Zynq Reset controller driver
 *
 * Author: Moritz Fischer <moritz.fischer@ettus.com>
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/regmap.h>
#include <linux/types.h>

struct zynq_reset_data {
	struct regmap *slcr;
	struct reset_controller_dev rcdev;
	u32 offset;
};

#define to_zynq_reset_data(p)		\
	container_of((p), struct zynq_reset_data, rcdev)

static int zynq_reset_assert(struct reset_controller_dev *rcdev,
			     unsigned long id)
{
	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);

	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;

	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
		 bank, offset);

	return regmap_update_bits(priv->slcr,
				  priv->offset + (bank * 4),
				  BIT(offset),
				  BIT(offset));
}

static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
			       unsigned long id)
{
	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);

	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;

	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
		 bank, offset);

	return regmap_update_bits(priv->slcr,
				  priv->offset + (bank * 4),
				  BIT(offset),
				  ~BIT(offset));
}

static int zynq_reset_status(struct reset_controller_dev *rcdev,
			     unsigned long id)
{
	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);

	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	int ret;
	u32 reg;

	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
		 bank, offset);

	ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);
	if (ret)
		return ret;

	return !!(reg & BIT(offset));
}

static const struct reset_control_ops zynq_reset_ops = {
	.assert		= zynq_reset_assert,
	.deassert	= zynq_reset_deassert,
	.status		= zynq_reset_status,
};

static int zynq_reset_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct zynq_reset_data *priv;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	platform_set_drvdata(pdev, priv);

	priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
						     "syscon");
	if (IS_ERR(priv->slcr)) {
		dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
		return PTR_ERR(priv->slcr);
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "missing IO resource\n");
		return -ENODEV;
	}

	priv->offset = res->start;

	priv->rcdev.owner = THIS_MODULE;
	priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
	priv->rcdev.ops = &zynq_reset_ops;
	priv->rcdev.of_node = pdev->dev.of_node;

	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
}

static const struct of_device_id zynq_reset_dt_ids[] = {
	{ .compatible = "xlnx,zynq-reset", },
	{ /* sentinel */ },
};

static struct platform_driver zynq_reset_driver = {
	.probe	= zynq_reset_probe,
	.driver = {
		.name		= KBUILD_MODNAME,
		.of_match_table	= zynq_reset_dt_ids,
	},
};
builtin_platform_driver(zynq_reset_driver);
Commit	Line	Data
8e8e69d6	1	// SPDX-License-Identifier: GPL-2.0-only
fedf42b5 MF	2	/*
	3	* Copyright (c) 2015, National Instruments Corp.
	4	*
	5	* Xilinx Zynq Reset controller driver
	6	*
fadb03cd	7	* Author: Moritz Fischer <moritz.fischer@ettus.com>
fedf42b5 MF	8	*/
	9
	10	#include <linux/err.h>
	11	#include <linux/io.h>
fadb03cd	12	#include <linux/init.h>
fedf42b5 MF	13	#include <linux/mfd/syscon.h>
	14	#include <linux/of.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/reset-controller.h>
	17	#include <linux/regmap.h>
	18	#include <linux/types.h>
	19
	20	struct zynq_reset_data {
	21	struct regmap *slcr;
	22	struct reset_controller_dev rcdev;
	23	u32 offset;
	24	};
	25
	26	#define to_zynq_reset_data(p) \
	27	container_of((p), struct zynq_reset_data, rcdev)
	28
	29	static int zynq_reset_assert(struct reset_controller_dev *rcdev,
	30	unsigned long id)
	31	{
	32	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
	33
	34	int bank = id / BITS_PER_LONG;
	35	int offset = id % BITS_PER_LONG;
	36
	37	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
	38	bank, offset);
	39
	40	return regmap_update_bits(priv->slcr,
	41	priv->offset + (bank * 4),
	42	BIT(offset),
	43	BIT(offset));
	44	}
	45
	46	static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
	47	unsigned long id)
	48	{
	49	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
	50
	51	int bank = id / BITS_PER_LONG;
	52	int offset = id % BITS_PER_LONG;
	53
	54	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
	55	bank, offset);
	56
	57	return regmap_update_bits(priv->slcr,
	58	priv->offset + (bank * 4),
	59	BIT(offset),
	60	~BIT(offset));
	61	}
	62
	63	static int zynq_reset_status(struct reset_controller_dev *rcdev,
	64	unsigned long id)
	65	{
	66	struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
	67
	68	int bank = id / BITS_PER_LONG;
	69	int offset = id % BITS_PER_LONG;
	70	int ret;
	71	u32 reg;
	72
	73	pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
	74	bank, offset);
	75
	76	ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);
77	if (ret)
78	return ret;
79
80	return !!(reg & BIT(offset));
81	}
82
356d108f	83	static const struct reset_control_ops zynq_reset_ops = {
fedf42b5 MF	84	.assert = zynq_reset_assert,
	85	.deassert = zynq_reset_deassert,
	86	.status = zynq_reset_status,
	87	};
	88
	89	static int zynq_reset_probe(struct platform_device *pdev)
	90	{
	91	struct resource *res;
	92	struct zynq_reset_data *priv;
	93
	94	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	95	if (!priv)
	96	return -ENOMEM;
	97	platform_set_drvdata(pdev, priv);
	98
	99	priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	100	"syscon");
	101	if (IS_ERR(priv->slcr)) {
	102	dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
	103	return PTR_ERR(priv->slcr);
	104	}
	105
	106	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	107	if (!res) {
	108	dev_err(&pdev->dev, "missing IO resource\n");
	109	return -ENODEV;
	110	}
	111
	112	priv->offset = res->start;
	113
	114	priv->rcdev.owner = THIS_MODULE;
	115	priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
	116	priv->rcdev.ops = &zynq_reset_ops;
	117	priv->rcdev.of_node = pdev->dev.of_node;
fedf42b5	118
da1fda2a	119	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
fedf42b5 MF	120	}
	121
	122	static const struct of_device_id zynq_reset_dt_ids[] = {
	123	{ .compatible = "xlnx,zynq-reset", },
	124	{ /* sentinel */ },
	125	};
	126
	127	static struct platform_driver zynq_reset_driver = {
	128	.probe = zynq_reset_probe,
fedf42b5 MF	129	.driver = {
	130	.name = KBUILD_MODNAME,
	131	.of_match_table = zynq_reset_dt_ids,
	132	},
	133	};
fadb03cd	134	builtin_platform_driver(zynq_reset_driver);