]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/rtc/rtc-armada38x.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
perf tools: Remove needless evlist.h include directives
[mirror_ubuntu-focal-kernel.git] / drivers / rtc / rtc-armada38x.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
a3a42806
GC		 2/*
3 * RTC driver for the Armada 38x Marvell SoCs
4 *
5 * Copyright (C) 2015 Marvell
6 *
7 * Gregory Clement <gregory.clement@free-electrons.com>
a3a42806
GC		 8 */
9
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
75faea91 14#include <linux/of_device.h>
a3a42806
GC		 15#include <linux/platform_device.h>
16#include <linux/rtc.h>
17
18#define RTC_STATUS 0x0
19#define RTC_STATUS_ALARM1 BIT(0)
20#define RTC_STATUS_ALARM2 BIT(1)
21#define RTC_IRQ1_CONF 0x4
34f54f57 22#define RTC_IRQ2_CONF 0x8
75faea91
GC		 23#define RTC_IRQ_AL_EN BIT(0)
24#define RTC_IRQ_FREQ_EN BIT(1)
25#define RTC_IRQ_FREQ_1HZ BIT(2)
f94ffbc2
RK		 26#define RTC_CCR 0x18
27#define RTC_CCR_MODE BIT(15)
1a990fef
BS		 28#define RTC_CONF_TEST 0x1C
29#define RTC_NOMINAL_TIMING BIT(13)
75faea91 30
a3a42806
GC		 31#define RTC_TIME 0xC
32#define RTC_ALARM1 0x10
34f54f57
GC		 33#define RTC_ALARM2 0x14
34
35/* Armada38x SoC registers */
75faea91
GC		 36#define RTC_38X_BRIDGE_TIMING_CTL 0x0
37#define RTC_38X_PERIOD_OFFS 0
38#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS)
39#define RTC_38X_READ_DELAY_OFFS 26
40#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS)
41
34f54f57
GC		 42/* Armada 7K/8K registers */
43#define RTC_8K_BRIDGE_TIMING_CTL0 0x0
44#define RTC_8K_WRCLK_PERIOD_OFFS 0
45#define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
46#define RTC_8K_WRCLK_SETUP_OFFS 16
47#define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
48#define RTC_8K_BRIDGE_TIMING_CTL1 0x4
49#define RTC_8K_READ_DELAY_OFFS 0
50#define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS)
51
52#define RTC_8K_ISR 0x10
53#define RTC_8K_IMR 0x14
54#define RTC_8K_ALARM2 BIT(0)
55
75faea91
GC		 56#define SOC_RTC_INTERRUPT 0x8
57#define SOC_RTC_ALARM1 BIT(0)
58#define SOC_RTC_ALARM2 BIT(1)
59#define SOC_RTC_ALARM1_MASK BIT(2)
60#define SOC_RTC_ALARM2_MASK BIT(3)
a3a42806 61
844a3073
GC		 62#define SAMPLE_NR 100
63
64struct value_to_freq {
65 u32 value;
66 u8 freq;
67};
68
a3a42806
GC		 69struct armada38x_rtc {
70 struct rtc_device *rtc_dev;
71 void __iomem *regs;
72 void __iomem *regs_soc;
73 spinlock_t lock;
74 int irq;
1a990fef 75 bool initialized;
844a3073 76 struct value_to_freq *val_to_freq;
75faea91
GC		 77 struct armada38x_rtc_data *data;
78};
79
80#define ALARM1 0
34f54f57
GC		 81#define ALARM2 1
82
75faea91
GC		 83#define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32))
84
85struct armada38x_rtc_data {
86 /* Initialize the RTC-MBUS bridge timing */
87 void (*update_mbus_timing)(struct armada38x_rtc *rtc);
88 u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
89 void (*clear_isr)(struct armada38x_rtc *rtc);
90 void (*unmask_interrupt)(struct armada38x_rtc *rtc);
91 u32 alarm;
a3a42806
GC		 92};
93
94/*
95 * According to the datasheet, the OS should wait 5us after every
96 * register write to the RTC hard macro so that the required update
97 * can occur without holding off the system bus
844a3073
GC		 98 * According to errata RES-3124064, Write to any RTC register
99 * may fail. As a workaround, before writing to RTC
100 * register, issue a dummy write of 0x0 twice to RTC Status
101 * register.
a3a42806 102 */
844a3073 103
a3a42806
GC		 104static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
105{
844a3073
GC		 106 writel(0, rtc->regs + RTC_STATUS);
107 writel(0, rtc->regs + RTC_STATUS);
a3a42806
GC		 108 writel(val, rtc->regs + offset);
109 udelay(5);
110}
111
844a3073 112/* Update RTC-MBUS bridge timing parameters */
75faea91 113static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
844a3073
GC		 114{
115 u32 reg;
116
75faea91
GC		 117 reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
118 reg &= ~RTC_38X_PERIOD_MASK;
119 reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
120 reg &= ~RTC_38X_READ_DELAY_MASK;
121 reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
122 writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
844a3073
GC		 123}
124
34f54f57
GC		 125static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
126{
127 u32 reg;
128
129 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
130 reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
131 reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
132 reg &= ~RTC_8K_WRCLK_SETUP_MASK;
133 reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
134 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
135
136 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
137 reg &= ~RTC_8K_READ_DELAY_MASK;
138 reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
139 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
140}
141
142static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
143{
144 return readl(rtc->regs + rtc_reg);
145}
146
75faea91 147static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
844a3073
GC		 148{
149 int i, index_max = 0, max = 0;
150
151 for (i = 0; i < SAMPLE_NR; i++) {
152 rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
153 rtc->val_to_freq[i].freq = 0;
154 }
155
156 for (i = 0; i < SAMPLE_NR; i++) {
157 int j = 0;
158 u32 value = rtc->val_to_freq[i].value;
159
160 while (rtc->val_to_freq[j].freq) {
161 if (rtc->val_to_freq[j].value == value) {
162 rtc->val_to_freq[j].freq++;
163 break;
164 }
165 j++;
166 }
167
168 if (!rtc->val_to_freq[j].freq) {
169 rtc->val_to_freq[j].value = value;
170 rtc->val_to_freq[j].freq = 1;
171 }
172
173 if (rtc->val_to_freq[j].freq > max) {
174 index_max = j;
175 max = rtc->val_to_freq[j].freq;
176 }
177
178 /*
179 * If a value already has half of the sample this is the most
180 * frequent one and we can stop the research right now
181 */
182 if (max > SAMPLE_NR / 2)
183 break;
184 }
185
186 return rtc->val_to_freq[index_max].value;
187}
188
75faea91
GC		 189static void armada38x_clear_isr(struct armada38x_rtc *rtc)
190{
191 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
192
193 writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
194}
195
196static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
197{
198 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
199
200 writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
201}
34f54f57
GC		 202
203static void armada8k_clear_isr(struct armada38x_rtc *rtc)
204{
205 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
206}
207
208static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
209{
210 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
211}
212
a3a42806
GC		 213static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
214{
215 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
844a3073 216 unsigned long time, flags;
a3a42806 217
0c6e7183 218 spin_lock_irqsave(&rtc->lock, flags);
75faea91 219 time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
0c6e7183 220 spin_unlock_irqrestore(&rtc->lock, flags);
a3a42806 221
f6e3d773 222 rtc_time64_to_tm(time, tm);
a3a42806
GC		 223
224 return 0;
225}
226
1a990fef
BS		 227static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
228{
229 u32 reg;
230
231 reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
232 /* If bits [7:0] are non-zero, assume RTC was uninitialized */
233 if (reg & 0xff) {
234 rtc_delayed_write(0, rtc, RTC_CONF_TEST);
235 msleep(500); /* Oscillator startup time */
236 rtc_delayed_write(0, rtc, RTC_TIME);
237 rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
238 RTC_STATUS);
239 rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
240 }
241 rtc->initialized = true;
242}
243
a3a42806
GC		 244static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
245{
246 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0c6e7183 247 unsigned long time, flags;
a3a42806 248
f6e3d773 249 time = rtc_tm_to_time64(tm);
844a3073 250
1a990fef
BS		 251 if (!rtc->initialized)
252 armada38x_rtc_reset(rtc);
253
0c6e7183 254 spin_lock_irqsave(&rtc->lock, flags);
a3a42806 255 rtc_delayed_write(time, rtc, RTC_TIME);
0c6e7183 256 spin_unlock_irqrestore(&rtc->lock, flags);
a3a42806 257
f6e3d773 258 return 0;
a3a42806
GC		 259}
260
261static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
262{
263 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
264 unsigned long time, flags;
75faea91
GC		 265 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
266 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806
GC		 267 u32 val;
268
269 spin_lock_irqsave(&rtc->lock, flags);
270
75faea91
GC		 271 time = rtc->data->read_rtc_reg(rtc, reg);
272 val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
a3a42806
GC		 273
274 spin_unlock_irqrestore(&rtc->lock, flags);
275
276 alrm->enabled = val ? 1 : 0;
f6e3d773 277 rtc_time64_to_tm(time, &alrm->time);
a3a42806
GC		 278
279 return 0;
280}
281
282static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
283{
284 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
75faea91
GC		 285 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
286 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 287 unsigned long time, flags;
a3a42806 288
f6e3d773 289 time = rtc_tm_to_time64(&alrm->time);
a3a42806
GC		 290
291 spin_lock_irqsave(&rtc->lock, flags);
292
75faea91 293 rtc_delayed_write(time, rtc, reg);
a3a42806
GC		 294
295 if (alrm->enabled) {
75faea91
GC		 296 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
297 rtc->data->unmask_interrupt(rtc);
a3a42806
GC		 298 }
299
300 spin_unlock_irqrestore(&rtc->lock, flags);
301
f6e3d773 302 return 0;
a3a42806
GC		 303}
304
305static int armada38x_rtc_alarm_irq_enable(struct device *dev,
306 unsigned int enabled)
307{
308 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
75faea91 309 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806
GC		 310 unsigned long flags;
311
312 spin_lock_irqsave(&rtc->lock, flags);
313
314 if (enabled)
75faea91 315 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
a3a42806 316 else
75faea91 317 rtc_delayed_write(0, rtc, reg_irq);
a3a42806
GC		 318
319 spin_unlock_irqrestore(&rtc->lock, flags);
320
321 return 0;
322}
323
324static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
325{
326 struct armada38x_rtc *rtc = data;
327 u32 val;
328 int event = RTC_IRQF | RTC_AF;
75faea91 329 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806
GC		 330
331 dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
332
333 spin_lock(&rtc->lock);
334
75faea91
GC		 335 rtc->data->clear_isr(rtc);
336 val = rtc->data->read_rtc_reg(rtc, reg_irq);
337 /* disable all the interrupts for alarm*/
338 rtc_delayed_write(0, rtc, reg_irq);
a3a42806 339 /* Ack the event */
75faea91 340 rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
a3a42806
GC		 341
342 spin_unlock(&rtc->lock);
343
75faea91
GC		 344 if (val & RTC_IRQ_FREQ_EN) {
345 if (val & RTC_IRQ_FREQ_1HZ)
a3a42806
GC		 346 event |= RTC_UF;
347 else
348 event |= RTC_PF;
349 }
350
351 rtc_update_irq(rtc->rtc_dev, 1, event);
352
353 return IRQ_HANDLED;
354}
355
f94ffbc2
RK		 356/*
357 * The information given in the Armada 388 functional spec is complex.
358 * They give two different formulas for calculating the offset value,
359 * but when considering "Offset" as an 8-bit signed integer, they both
360 * reduce down to (we shall rename "Offset" as "val" here):
361 *
362 * val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768
363 *
364 * Converting to time, f = 1/t:
365 * val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768
366 *
367 * => t_measured / t_ideal = val * resolution + 1
368 *
369 * "offset" in the RTC interface is defined as:
370 * t = t0 * (1 + offset * 1e-9)
371 * where t is the desired period, t0 is the measured period with a zero
372 * offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
373 * offset = (t_ideal / t_measured - 1) / 1e-9
374 *
375 * => t_ideal / t_measured = offset * 1e-9 + 1
376 *
377 * so:
378 *
379 * offset * 1e-9 + 1 = 1 / (val * resolution + 1)
380 *
381 * We want "resolution" to be an integer, so resolution = R * 1e-9, giving
382 * offset = 1e18 / (val * R + 1e9) - 1e9
383 * val = (1e18 / (offset + 1e9) - 1e9) / R
384 * with a common transformation:
385 * f(x) = 1e18 / (x + 1e9) - 1e9
386 * offset = f(val * R)
387 * val = f(offset) / R
388 *
389 * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
390 */
391static long armada38x_ppb_convert(long ppb)
392{
393 long div = ppb + 1000000000L;
394
395 return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
396}
397
398static int armada38x_rtc_read_offset(struct device *dev, long *offset)
399{
400 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
401 unsigned long ccr, flags;
402 long ppb_cor;
403
404 spin_lock_irqsave(&rtc->lock, flags);
405 ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
406 spin_unlock_irqrestore(&rtc->lock, flags);
407
408 ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
409 /* ppb_cor + 1000000000L can never be zero */
410 *offset = armada38x_ppb_convert(ppb_cor);
411
412 return 0;
413}
414
415static int armada38x_rtc_set_offset(struct device *dev, long offset)
416{
417 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
418 unsigned long ccr = 0;
419 long ppb_cor, off;
420
421 /*
422 * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
423 * need to clamp the input. This equates to -484270 .. 488558.
424 * Not only is this to stop out of range "off" but also to
425 * avoid the division by zero in armada38x_ppb_convert().
426 */
427 offset = clamp(offset, -484270L, 488558L);
428
429 ppb_cor = armada38x_ppb_convert(offset);
430
431 /*
432 * Use low update mode where possible, which gives a better
433 * resolution of correction.
434 */
435 off = DIV_ROUND_CLOSEST(ppb_cor, 954);
436 if (off > 127 || off < -128) {
437 ccr = RTC_CCR_MODE;
438 off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
439 }
440
441 /*
442 * Armada 388 requires a bit pattern in bits 14..8 depending on
443 * the sign bit: { 0, ~S, S, S, S, S, S }
444 */
445 ccr |= (off & 0x3fff) ^ 0x2000;
446 rtc_delayed_write(ccr, rtc, RTC_CCR);
447
448 return 0;
449}
450
d748c981 451static const struct rtc_class_ops armada38x_rtc_ops = {
a3a42806
GC		 452 .read_time = armada38x_rtc_read_time,
453 .set_time = armada38x_rtc_set_time,
454 .read_alarm = armada38x_rtc_read_alarm,
455 .set_alarm = armada38x_rtc_set_alarm,
456 .alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
f94ffbc2
RK		 457 .read_offset = armada38x_rtc_read_offset,
458 .set_offset = armada38x_rtc_set_offset,
a3a42806
GC		 459};
460
d748c981
RK		 461static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
462 .read_time = armada38x_rtc_read_time,
463 .set_time = armada38x_rtc_set_time,
464 .read_alarm = armada38x_rtc_read_alarm,
f94ffbc2
RK		 465 .read_offset = armada38x_rtc_read_offset,
466 .set_offset = armada38x_rtc_set_offset,
d748c981
RK		 467};
468
75faea91
GC		 469static const struct armada38x_rtc_data armada38x_data = {
470 .update_mbus_timing = rtc_update_38x_mbus_timing_params,
471 .read_rtc_reg = read_rtc_register_38x_wa,
472 .clear_isr = armada38x_clear_isr,
473 .unmask_interrupt = armada38x_unmask_interrupt,
474 .alarm = ALARM1,
475};
476
34f54f57
GC		 477static const struct armada38x_rtc_data armada8k_data = {
478 .update_mbus_timing = rtc_update_8k_mbus_timing_params,
479 .read_rtc_reg = read_rtc_register,
480 .clear_isr = armada8k_clear_isr,
481 .unmask_interrupt = armada8k_unmask_interrupt,
482 .alarm = ALARM2,
483};
484
75faea91
GC		 485#ifdef CONFIG_OF
486static const struct of_device_id armada38x_rtc_of_match_table[] = {
487 {
488 .compatible = "marvell,armada-380-rtc",
489 .data = &armada38x_data,
490 },
34f54f57
GC		 491 {
492 .compatible = "marvell,armada-8k-rtc",
493 .data = &armada8k_data,
494 },
75faea91
GC		 495 {}
496};
497MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
498#endif
499
a3a42806
GC		 500static __init int armada38x_rtc_probe(struct platform_device *pdev)
501{
502 struct resource *res;
503 struct armada38x_rtc *rtc;
75faea91 504 const struct of_device_id *match;
a3a42806
GC		 505 int ret;
506
75faea91
GC		 507 match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev);
508 if (!match)
509 return -ENODEV;
510
a3a42806
GC		 511 rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
512 GFP_KERNEL);
513 if (!rtc)
514 return -ENOMEM;
515
844a3073
GC		 516 rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
517 sizeof(struct value_to_freq), GFP_KERNEL);
518 if (!rtc->val_to_freq)
519 return -ENOMEM;
520
a3a42806
GC		 521 spin_lock_init(&rtc->lock);
522
523 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
524 rtc->regs = devm_ioremap_resource(&pdev->dev, res);
525 if (IS_ERR(rtc->regs))
526 return PTR_ERR(rtc->regs);
527 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
528 rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
529 if (IS_ERR(rtc->regs_soc))
530 return PTR_ERR(rtc->regs_soc);
531
532 rtc->irq = platform_get_irq(pdev, 0);
533
534 if (rtc->irq < 0) {
535 dev_err(&pdev->dev, "no irq\n");
536 return rtc->irq;
537 }
7d61cbb9
AB		 538
539 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
540 if (IS_ERR(rtc->rtc_dev))
541 return PTR_ERR(rtc->rtc_dev);
542
a3a42806
GC		 543 if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
544 0, pdev->name, rtc) < 0) {
545 dev_warn(&pdev->dev, "Interrupt not available.\n");
546 rtc->irq = -1;
d748c981
RK		 547 }
548 platform_set_drvdata(pdev, rtc);
549
550 if (rtc->irq != -1) {
551 device_init_wakeup(&pdev->dev, 1);
7d61cbb9 552 rtc->rtc_dev->ops = &armada38x_rtc_ops;
d748c981 553 } else {
a3a42806
GC		 554 /*
555 * If there is no interrupt available then we can't
556 * use the alarm
557 */
7d61cbb9 558 rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq;
a3a42806 559 }
75faea91
GC		 560 rtc->data = (struct armada38x_rtc_data *)match->data;
561
844a3073 562 /* Update RTC-MBUS bridge timing parameters */
75faea91 563 rtc->data->update_mbus_timing(rtc);
844a3073 564
ef2a7176
AB		 565 rtc->rtc_dev->range_max = U32_MAX;
566
7d61cbb9
AB		 567 ret = rtc_register_device(rtc->rtc_dev);
568 if (ret)
a3a42806 569 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
7d61cbb9
AB		 570
571 return ret;
a3a42806
GC		 572}
573
574#ifdef CONFIG_PM_SLEEP
575static int armada38x_rtc_suspend(struct device *dev)
576{
577 if (device_may_wakeup(dev)) {
578 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
579
580 return enable_irq_wake(rtc->irq);
581 }
582
583 return 0;
584}
585
586static int armada38x_rtc_resume(struct device *dev)
587{
588 if (device_may_wakeup(dev)) {
589 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
590
844a3073 591 /* Update RTC-MBUS bridge timing parameters */
75faea91 592 rtc->data->update_mbus_timing(rtc);
844a3073 593
a3a42806
GC		 594 return disable_irq_wake(rtc->irq);
595 }
596
597 return 0;
598}
599#endif
600
601static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
602 armada38x_rtc_suspend, armada38x_rtc_resume);
603
a3a42806
GC		 604static struct platform_driver armada38x_rtc_driver = {
605 .driver = {
606 .name = "armada38x-rtc",
607 .pm = &armada38x_rtc_pm_ops,
608 .of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
609 },
610};
611
612module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
613
614MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
615MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
616MODULE_LICENSE("GPL");
Ubuntu Focal Linux kernel mirror