[mirror_ubuntu-bionic-kernel.git] / drivers / rtc / rtc-armada38x.c

/*
 * RTC driver for the Armada 38x Marvell SoCs
 *
 * Copyright (C) 2015 Marvell
 *
 * Gregory Clement <gregory.clement@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of the
 * License, or (at your option) any later version.
 *
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>

#define RTC_STATUS	    0x0
#define RTC_STATUS_ALARM1	    BIT(0)
#define RTC_STATUS_ALARM2	    BIT(1)
#define RTC_IRQ1_CONF	    0x4
#define RTC_IRQ2_CONF	    0x8
#define RTC_IRQ_AL_EN		    BIT(0)
#define RTC_IRQ_FREQ_EN		    BIT(1)
#define RTC_IRQ_FREQ_1HZ	    BIT(2)
#define RTC_CCR		    0x18
#define RTC_CCR_MODE		    BIT(15)

#define RTC_TIME	    0xC
#define RTC_ALARM1	    0x10
#define RTC_ALARM2	    0x14

/* Armada38x SoC registers  */
#define RTC_38X_BRIDGE_TIMING_CTL   0x0
#define RTC_38X_PERIOD_OFFS		0
#define RTC_38X_PERIOD_MASK		(0x3FF << RTC_38X_PERIOD_OFFS)
#define RTC_38X_READ_DELAY_OFFS		26
#define RTC_38X_READ_DELAY_MASK		(0x1F << RTC_38X_READ_DELAY_OFFS)

/* Armada 7K/8K registers  */
#define RTC_8K_BRIDGE_TIMING_CTL0    0x0
#define RTC_8K_WRCLK_PERIOD_OFFS	0
#define RTC_8K_WRCLK_PERIOD_MASK	(0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
#define RTC_8K_WRCLK_SETUP_OFFS		16
#define RTC_8K_WRCLK_SETUP_MASK		(0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
#define RTC_8K_BRIDGE_TIMING_CTL1   0x4
#define RTC_8K_READ_DELAY_OFFS		0
#define RTC_8K_READ_DELAY_MASK		(0xFFFF << RTC_8K_READ_DELAY_OFFS)

#define RTC_8K_ISR		    0x10
#define RTC_8K_IMR		    0x14
#define RTC_8K_ALARM2			BIT(0)

#define SOC_RTC_INTERRUPT	    0x8
#define SOC_RTC_ALARM1			BIT(0)
#define SOC_RTC_ALARM2			BIT(1)
#define SOC_RTC_ALARM1_MASK		BIT(2)
#define SOC_RTC_ALARM2_MASK		BIT(3)

#define SAMPLE_NR 100

struct value_to_freq {
	u32 value;
	u8 freq;
};

struct armada38x_rtc {
	struct rtc_device   *rtc_dev;
	void __iomem	    *regs;
	void __iomem	    *regs_soc;
	spinlock_t	    lock;
	int		    irq;
	struct value_to_freq *val_to_freq;
	struct armada38x_rtc_data *data;
};

#define ALARM1	0
#define ALARM2	1

#define ALARM_REG(base, alarm)	 ((base) + (alarm) * sizeof(u32))

struct armada38x_rtc_data {
	/* Initialize the RTC-MBUS bridge timing */
	void (*update_mbus_timing)(struct armada38x_rtc *rtc);
	u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
	void (*clear_isr)(struct armada38x_rtc *rtc);
	void (*unmask_interrupt)(struct armada38x_rtc *rtc);
	u32 alarm;
};

/*
 * According to the datasheet, the OS should wait 5us after every
 * register write to the RTC hard macro so that the required update
 * can occur without holding off the system bus
 * According to errata RES-3124064, Write to any RTC register
 * may fail. As a workaround, before writing to RTC
 * register, issue a dummy write of 0x0 twice to RTC Status
 * register.
 */

static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
{
	writel(0, rtc->regs + RTC_STATUS);
	writel(0, rtc->regs + RTC_STATUS);
	writel(val, rtc->regs + offset);
	udelay(5);
}

/* Update RTC-MBUS bridge timing parameters */
static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
{
	u32 reg;

	reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
	reg &= ~RTC_38X_PERIOD_MASK;
	reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
	reg &= ~RTC_38X_READ_DELAY_MASK;
	reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
	writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
}

static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
{
	u32 reg;

	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
	reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
	reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
	reg &= ~RTC_8K_WRCLK_SETUP_MASK;
	reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);

	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
	reg &= ~RTC_8K_READ_DELAY_MASK;
	reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
}

static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
{
	return readl(rtc->regs + rtc_reg);
}

static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
{
	int i, index_max = 0, max = 0;

	for (i = 0; i < SAMPLE_NR; i++) {
		rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
		rtc->val_to_freq[i].freq = 0;
	}

	for (i = 0; i < SAMPLE_NR; i++) {
		int j = 0;
		u32 value = rtc->val_to_freq[i].value;

		while (rtc->val_to_freq[j].freq) {
			if (rtc->val_to_freq[j].value == value) {
				rtc->val_to_freq[j].freq++;
				break;
			}
			j++;
		}

		if (!rtc->val_to_freq[j].freq) {
			rtc->val_to_freq[j].value = value;
			rtc->val_to_freq[j].freq = 1;
		}

		if (rtc->val_to_freq[j].freq > max) {
			index_max = j;
			max = rtc->val_to_freq[j].freq;
		}

		/*
		 * If a value already has half of the sample this is the most
		 * frequent one and we can stop the research right now
		 */
		if (max > SAMPLE_NR / 2)
			break;
	}

	return rtc->val_to_freq[index_max].value;
}

static void armada38x_clear_isr(struct armada38x_rtc *rtc)
{
	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);

	writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
}

static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
{
	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);

	writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
}

static void armada8k_clear_isr(struct armada38x_rtc *rtc)
{
	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
}

static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
{
	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
}

static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long time, flags;

	spin_lock_irqsave(&rtc->lock, flags);
	time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
	spin_unlock_irqrestore(&rtc->lock, flags);

	rtc_time_to_tm(time, tm);

	return 0;
}

static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	int ret = 0;
	unsigned long time, flags;

	ret = rtc_tm_to_time(tm, &time);

	if (ret)
		goto out;

	spin_lock_irqsave(&rtc->lock, flags);
	rtc_delayed_write(time, rtc, RTC_TIME);
	spin_unlock_irqrestore(&rtc->lock, flags);

out:
	return ret;
}

static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long time, flags;
	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
	u32 val;

	spin_lock_irqsave(&rtc->lock, flags);

	time = rtc->data->read_rtc_reg(rtc, reg);
	val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;

	spin_unlock_irqrestore(&rtc->lock, flags);

	alrm->enabled = val ? 1 : 0;
	rtc_time_to_tm(time,  &alrm->time);

	return 0;
}

static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
	unsigned long time, flags;
	int ret = 0;

	ret = rtc_tm_to_time(&alrm->time, &time);

	if (ret)
		goto out;

	spin_lock_irqsave(&rtc->lock, flags);

	rtc_delayed_write(time, rtc, reg);

	if (alrm->enabled) {
		rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
		rtc->data->unmask_interrupt(rtc);
	}

	spin_unlock_irqrestore(&rtc->lock, flags);

out:
	return ret;
}

static int armada38x_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
	unsigned long flags;

	spin_lock_irqsave(&rtc->lock, flags);

	if (enabled)
		rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
	else
		rtc_delayed_write(0, rtc, reg_irq);

	spin_unlock_irqrestore(&rtc->lock, flags);

	return 0;
}

static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
{
	struct armada38x_rtc *rtc = data;
	u32 val;
	int event = RTC_IRQF | RTC_AF;
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);

	dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);

	spin_lock(&rtc->lock);

	rtc->data->clear_isr(rtc);
	val = rtc->data->read_rtc_reg(rtc, reg_irq);
	/* disable all the interrupts for alarm*/
	rtc_delayed_write(0, rtc, reg_irq);
	/* Ack the event */
	rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);

	spin_unlock(&rtc->lock);

	if (val & RTC_IRQ_FREQ_EN) {
		if (val & RTC_IRQ_FREQ_1HZ)
			event |= RTC_UF;
		else
			event |= RTC_PF;
	}

	rtc_update_irq(rtc->rtc_dev, 1, event);

	return IRQ_HANDLED;
}

/*
 * The information given in the Armada 388 functional spec is complex.
 * They give two different formulas for calculating the offset value,
 * but when considering "Offset" as an 8-bit signed integer, they both
 * reduce down to (we shall rename "Offset" as "val" here):
 *
 *   val = (f_ideal / f_measured - 1) / resolution   where f_ideal = 32768
 *
 * Converting to time, f = 1/t:
 *   val = (t_measured / t_ideal - 1) / resolution   where t_ideal = 1/32768
 *
 *   =>  t_measured / t_ideal = val * resolution + 1
 *
 * "offset" in the RTC interface is defined as:
 *   t = t0 * (1 + offset * 1e-9)
 * where t is the desired period, t0 is the measured period with a zero
 * offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
 *   offset = (t_ideal / t_measured - 1) / 1e-9
 *
 *   => t_ideal / t_measured = offset * 1e-9 + 1
 *
 * so:
 *
 *   offset * 1e-9 + 1 = 1 / (val * resolution + 1)
 *
 * We want "resolution" to be an integer, so resolution = R * 1e-9, giving
 *   offset = 1e18 / (val * R + 1e9) - 1e9
 *   val = (1e18 / (offset + 1e9) - 1e9) / R
 * with a common transformation:
 *   f(x) = 1e18 / (x + 1e9) - 1e9
 *   offset = f(val * R)
 *   val = f(offset) / R
 *
 * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
 */
static long armada38x_ppb_convert(long ppb)
{
	long div = ppb + 1000000000L;

	return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
}

static int armada38x_rtc_read_offset(struct device *dev, long *offset)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long ccr, flags;
	long ppb_cor;

	spin_lock_irqsave(&rtc->lock, flags);
	ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
	spin_unlock_irqrestore(&rtc->lock, flags);

	ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
	/* ppb_cor + 1000000000L can never be zero */
	*offset = armada38x_ppb_convert(ppb_cor);

	return 0;
}

static int armada38x_rtc_set_offset(struct device *dev, long offset)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long ccr = 0;
	long ppb_cor, off;

	/*
	 * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
	 * need to clamp the input.  This equates to -484270 .. 488558.
	 * Not only is this to stop out of range "off" but also to
	 * avoid the division by zero in armada38x_ppb_convert().
	 */
	offset = clamp(offset, -484270L, 488558L);

	ppb_cor = armada38x_ppb_convert(offset);

	/*
	 * Use low update mode where possible, which gives a better
	 * resolution of correction.
	 */
	off = DIV_ROUND_CLOSEST(ppb_cor, 954);
	if (off > 127 || off < -128) {
		ccr = RTC_CCR_MODE;
		off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
	}

	/*
	 * Armada 388 requires a bit pattern in bits 14..8 depending on
	 * the sign bit: { 0, ~S, S, S, S, S, S }
	 */
	ccr |= (off & 0x3fff) ^ 0x2000;
	rtc_delayed_write(ccr, rtc, RTC_CCR);

	return 0;
}

static const struct rtc_class_ops armada38x_rtc_ops = {
	.read_time = armada38x_rtc_read_time,
	.set_time = armada38x_rtc_set_time,
	.read_alarm = armada38x_rtc_read_alarm,
	.set_alarm = armada38x_rtc_set_alarm,
	.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
	.read_offset = armada38x_rtc_read_offset,
	.set_offset = armada38x_rtc_set_offset,
};

static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
	.read_time = armada38x_rtc_read_time,
	.set_time = armada38x_rtc_set_time,
	.read_alarm = armada38x_rtc_read_alarm,
	.read_offset = armada38x_rtc_read_offset,
	.set_offset = armada38x_rtc_set_offset,
};

static const struct armada38x_rtc_data armada38x_data = {
	.update_mbus_timing = rtc_update_38x_mbus_timing_params,
	.read_rtc_reg = read_rtc_register_38x_wa,
	.clear_isr = armada38x_clear_isr,
	.unmask_interrupt = armada38x_unmask_interrupt,
	.alarm = ALARM1,
};

static const struct armada38x_rtc_data armada8k_data = {
	.update_mbus_timing = rtc_update_8k_mbus_timing_params,
	.read_rtc_reg = read_rtc_register,
	.clear_isr = armada8k_clear_isr,
	.unmask_interrupt = armada8k_unmask_interrupt,
	.alarm = ALARM2,
};

#ifdef CONFIG_OF
static const struct of_device_id armada38x_rtc_of_match_table[] = {
	{
		.compatible = "marvell,armada-380-rtc",
		.data = &armada38x_data,
	},
	{
		.compatible = "marvell,armada-8k-rtc",
		.data = &armada8k_data,
	},
	{}
};
MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
#endif

static __init int armada38x_rtc_probe(struct platform_device *pdev)
{
	const struct rtc_class_ops *ops;
	struct resource *res;
	struct armada38x_rtc *rtc;
	const struct of_device_id *match;
	int ret;

	match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev);
	if (!match)
		return -ENODEV;

	rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
			    GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
				sizeof(struct value_to_freq), GFP_KERNEL);
	if (!rtc->val_to_freq)
		return -ENOMEM;

	spin_lock_init(&rtc->lock);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
	rtc->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rtc->regs))
		return PTR_ERR(rtc->regs);
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
	rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rtc->regs_soc))
		return PTR_ERR(rtc->regs_soc);

	rtc->irq = platform_get_irq(pdev, 0);

	if (rtc->irq < 0) {
		dev_err(&pdev->dev, "no irq\n");
		return rtc->irq;
	}
	if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
				0, pdev->name, rtc) < 0) {
		dev_warn(&pdev->dev, "Interrupt not available.\n");
		rtc->irq = -1;
	}
	platform_set_drvdata(pdev, rtc);

	if (rtc->irq != -1) {
		device_init_wakeup(&pdev->dev, 1);
		ops = &armada38x_rtc_ops;
	} else {
		/*
		 * If there is no interrupt available then we can't
		 * use the alarm
		 */
		ops = &armada38x_rtc_ops_noirq;
	}
	rtc->data = (struct armada38x_rtc_data *)match->data;


	/* Update RTC-MBUS bridge timing parameters */
	rtc->data->update_mbus_timing(rtc);

	rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
						ops, THIS_MODULE);
	if (IS_ERR(rtc->rtc_dev)) {
		ret = PTR_ERR(rtc->rtc_dev);
		dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
		return ret;
	}
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int armada38x_rtc_suspend(struct device *dev)
{
	if (device_may_wakeup(dev)) {
		struct armada38x_rtc *rtc = dev_get_drvdata(dev);

		return enable_irq_wake(rtc->irq);
	}

	return 0;
}

static int armada38x_rtc_resume(struct device *dev)
{
	if (device_may_wakeup(dev)) {
		struct armada38x_rtc *rtc = dev_get_drvdata(dev);

		/* Update RTC-MBUS bridge timing parameters */
		rtc->data->update_mbus_timing(rtc);

		return disable_irq_wake(rtc->irq);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
			 armada38x_rtc_suspend, armada38x_rtc_resume);

static struct platform_driver armada38x_rtc_driver = {
	.driver		= {
		.name	= "armada38x-rtc",
		.pm	= &armada38x_rtc_pm_ops,
		.of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
	},
};

module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);

MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a42806 GC	1	/*
	2	* RTC driver for the Armada 38x Marvell SoCs
	3	*
	4	* Copyright (C) 2015 Marvell
	5	*
	6	* Gregory Clement <gregory.clement@free-electrons.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of the
	11	* License, or (at your option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
75faea91	19	#include <linux/of_device.h>
a3a42806 GC	20	#include <linux/platform_device.h>
	21	#include <linux/rtc.h>
	22
	23	#define RTC_STATUS 0x0
	24	#define RTC_STATUS_ALARM1 BIT(0)
	25	#define RTC_STATUS_ALARM2 BIT(1)
	26	#define RTC_IRQ1_CONF 0x4
34f54f57	27	#define RTC_IRQ2_CONF 0x8
75faea91 GC	28	#define RTC_IRQ_AL_EN BIT(0)
	29	#define RTC_IRQ_FREQ_EN BIT(1)
	30	#define RTC_IRQ_FREQ_1HZ BIT(2)
f94ffbc2 RK	31	#define RTC_CCR 0x18
f94ffbc2 RK	32	#define RTC_CCR_MODE BIT(15)
75faea91	33
a3a42806 GC	34	#define RTC_TIME 0xC
a3a42806 GC	35	#define RTC_ALARM1 0x10
34f54f57 GC	36	#define RTC_ALARM2 0x14
	37
	38	/* Armada38x SoC registers */
75faea91 GC	39	#define RTC_38X_BRIDGE_TIMING_CTL 0x0
	40	#define RTC_38X_PERIOD_OFFS 0
	41	#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS)
	42	#define RTC_38X_READ_DELAY_OFFS 26
	43	#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS)
	44
34f54f57 GC	45	/* Armada 7K/8K registers */
	46	#define RTC_8K_BRIDGE_TIMING_CTL0 0x0
	47	#define RTC_8K_WRCLK_PERIOD_OFFS 0
	48	#define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
	49	#define RTC_8K_WRCLK_SETUP_OFFS 16
	50	#define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
	51	#define RTC_8K_BRIDGE_TIMING_CTL1 0x4
	52	#define RTC_8K_READ_DELAY_OFFS 0
	53	#define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS)
	54
	55	#define RTC_8K_ISR 0x10
	56	#define RTC_8K_IMR 0x14
	57	#define RTC_8K_ALARM2 BIT(0)
	58
75faea91 GC	59	#define SOC_RTC_INTERRUPT 0x8
	60	#define SOC_RTC_ALARM1 BIT(0)
	61	#define SOC_RTC_ALARM2 BIT(1)
	62	#define SOC_RTC_ALARM1_MASK BIT(2)
	63	#define SOC_RTC_ALARM2_MASK BIT(3)
a3a42806	64
844a3073 GC	65	#define SAMPLE_NR 100
	66
	67	struct value_to_freq {
	68	u32 value;
	69	u8 freq;
	70	};
	71
a3a42806 GC	72	struct armada38x_rtc {
	73	struct rtc_device *rtc_dev;
	74	void __iomem *regs;
	75	void __iomem *regs_soc;
	76	spinlock_t lock;
	77	int irq;
844a3073	78	struct value_to_freq *val_to_freq;
75faea91 GC	79	struct armada38x_rtc_data *data;
	80	};
	81
	82	#define ALARM1 0
34f54f57 GC	83	#define ALARM2 1
34f54f57 GC	84
75faea91 GC	85	#define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32))
	86
	87	struct armada38x_rtc_data {
	88	/* Initialize the RTC-MBUS bridge timing */
	89	void (update_mbus_timing)(struct armada38x_rtc rtc);
	90	u32 (read_rtc_reg)(struct armada38x_rtc rtc, u8 rtc_reg);
	91	void (clear_isr)(struct armada38x_rtc rtc);
	92	void (unmask_interrupt)(struct armada38x_rtc rtc);
	93	u32 alarm;
a3a42806 GC	94	};
	95
	96	/*
	97	* According to the datasheet, the OS should wait 5us after every
	98	* register write to the RTC hard macro so that the required update
	99	* can occur without holding off the system bus
844a3073 GC	100	* According to errata RES-3124064, Write to any RTC register
	101	* may fail. As a workaround, before writing to RTC
	102	* register, issue a dummy write of 0x0 twice to RTC Status
	103	* register.
a3a42806	104	*/
844a3073	105
a3a42806 GC	106	static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
a3a42806 GC	107	{
844a3073 GC	108	writel(0, rtc->regs + RTC_STATUS);
844a3073 GC	109	writel(0, rtc->regs + RTC_STATUS);
a3a42806 GC	110	writel(val, rtc->regs + offset);
	111	udelay(5);
	112	}
	113
844a3073	114	/* Update RTC-MBUS bridge timing parameters */
75faea91	115	static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
844a3073 GC	116	{
	117	u32 reg;
	118
75faea91 GC	119	reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
	120	reg &= ~RTC_38X_PERIOD_MASK;
	121	reg \|= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
	122	reg &= ~RTC_38X_READ_DELAY_MASK;
	123	reg \|= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
	124	writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
844a3073 GC	125	}
844a3073 GC	126
34f54f57 GC	127	static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
	128	{
	129	u32 reg;
	130
	131	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
	132	reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
	133	reg \|= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
	134	reg &= ~RTC_8K_WRCLK_SETUP_MASK;
	135	reg \|= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
	136	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
	137
	138	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
	139	reg &= ~RTC_8K_READ_DELAY_MASK;
	140	reg \|= 0x3F << RTC_8K_READ_DELAY_OFFS;
	141	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
	142	}
	143
	144	static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
	145	{
	146	return readl(rtc->regs + rtc_reg);
	147	}
	148
75faea91	149	static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
844a3073 GC	150	{
	151	int i, index_max = 0, max = 0;
	152
	153	for (i = 0; i < SAMPLE_NR; i++) {
	154	rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
	155	rtc->val_to_freq[i].freq = 0;
	156	}
	157
	158	for (i = 0; i < SAMPLE_NR; i++) {
	159	int j = 0;
	160	u32 value = rtc->val_to_freq[i].value;
	161
	162	while (rtc->val_to_freq[j].freq) {
	163	if (rtc->val_to_freq[j].value == value) {
	164	rtc->val_to_freq[j].freq++;
	165	break;
	166	}
	167	j++;
	168	}
	169
	170	if (!rtc->val_to_freq[j].freq) {
	171	rtc->val_to_freq[j].value = value;
	172	rtc->val_to_freq[j].freq = 1;
	173	}
	174
	175	if (rtc->val_to_freq[j].freq > max) {
	176	index_max = j;
	177	max = rtc->val_to_freq[j].freq;
	178	}
	179
	180	/*
	181	* If a value already has half of the sample this is the most
	182	* frequent one and we can stop the research right now
	183	*/
	184	if (max > SAMPLE_NR / 2)
	185	break;
	186	}
	187
	188	return rtc->val_to_freq[index_max].value;
	189	}
	190
75faea91 GC	191	static void armada38x_clear_isr(struct armada38x_rtc *rtc)
	192	{
	193	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
	194
	195	writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
	196	}
	197
	198	static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
	199	{
	200	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
	201
	202	writel(val \| SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
	203	}
34f54f57 GC	204
	205	static void armada8k_clear_isr(struct armada38x_rtc *rtc)
	206	{
	207	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
	208	}
	209
	210	static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
	211	{
	212	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
	213	}
	214
a3a42806 GC	215	static int armada38x_rtc_read_time(struct device dev, struct rtc_time tm)
	216	{
	217	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
844a3073	218	unsigned long time, flags;
a3a42806	219
0c6e7183	220	spin_lock_irqsave(&rtc->lock, flags);
75faea91	221	time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
0c6e7183	222	spin_unlock_irqrestore(&rtc->lock, flags);
a3a42806	223
844a3073	224	rtc_time_to_tm(time, tm);
a3a42806 GC	225
	226	return 0;
	227	}
	228
	229	static int armada38x_rtc_set_time(struct device dev, struct rtc_time tm)
	230	{
	231	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	232	int ret = 0;
0c6e7183	233	unsigned long time, flags;
a3a42806 GC	234
	235	ret = rtc_tm_to_time(tm, &time);
	236
	237	if (ret)
	238	goto out;
844a3073	239
0c6e7183	240	spin_lock_irqsave(&rtc->lock, flags);
a3a42806	241	rtc_delayed_write(time, rtc, RTC_TIME);
0c6e7183	242	spin_unlock_irqrestore(&rtc->lock, flags);
a3a42806	243
a3a42806 GC	244	out:
	245	return ret;
	246	}
	247
	248	static int armada38x_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	249	{
	250	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	251	unsigned long time, flags;
75faea91 GC	252	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
75faea91 GC	253	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	254	u32 val;
	255
	256	spin_lock_irqsave(&rtc->lock, flags);
	257
75faea91 GC	258	time = rtc->data->read_rtc_reg(rtc, reg);
75faea91 GC	259	val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
a3a42806 GC	260
	261	spin_unlock_irqrestore(&rtc->lock, flags);
	262
	263	alrm->enabled = val ? 1 : 0;
	264	rtc_time_to_tm(time, &alrm->time);
	265
	266	return 0;
	267	}
	268
	269	static int armada38x_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	270	{
	271	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
75faea91 GC	272	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
75faea91 GC	273	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	274	unsigned long time, flags;
a3a42806 GC	275	int ret = 0;
a3a42806 GC	276
	277	ret = rtc_tm_to_time(&alrm->time, &time);
	278
	279	if (ret)
	280	goto out;
	281
	282	spin_lock_irqsave(&rtc->lock, flags);
	283
75faea91	284	rtc_delayed_write(time, rtc, reg);
a3a42806 GC	285
a3a42806 GC	286	if (alrm->enabled) {
75faea91 GC	287	rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
75faea91 GC	288	rtc->data->unmask_interrupt(rtc);
a3a42806 GC	289	}
	290
	291	spin_unlock_irqrestore(&rtc->lock, flags);
	292
	293	out:
	294	return ret;
	295	}
	296
	297	static int armada38x_rtc_alarm_irq_enable(struct device *dev,
	298	unsigned int enabled)
	299	{
	300	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
75faea91	301	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	302	unsigned long flags;
	303
	304	spin_lock_irqsave(&rtc->lock, flags);
	305
	306	if (enabled)
75faea91	307	rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
a3a42806	308	else
75faea91	309	rtc_delayed_write(0, rtc, reg_irq);
a3a42806 GC	310
	311	spin_unlock_irqrestore(&rtc->lock, flags);
	312
	313	return 0;
	314	}
	315
	316	static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
	317	{
	318	struct armada38x_rtc *rtc = data;
	319	u32 val;
	320	int event = RTC_IRQF \| RTC_AF;
75faea91	321	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	322
	323	dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
	324
	325	spin_lock(&rtc->lock);
	326
75faea91 GC	327	rtc->data->clear_isr(rtc);
	328	val = rtc->data->read_rtc_reg(rtc, reg_irq);
	329	/* disable all the interrupts for alarm*/
	330	rtc_delayed_write(0, rtc, reg_irq);
a3a42806	331	/* Ack the event */
75faea91	332	rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
a3a42806 GC	333
	334	spin_unlock(&rtc->lock);
	335
75faea91 GC	336	if (val & RTC_IRQ_FREQ_EN) {
75faea91 GC	337	if (val & RTC_IRQ_FREQ_1HZ)
a3a42806 GC	338	event \|= RTC_UF;
	339	else
	340	event \|= RTC_PF;
	341	}
	342
	343	rtc_update_irq(rtc->rtc_dev, 1, event);
	344
	345	return IRQ_HANDLED;
	346	}
	347
f94ffbc2 RK	348	/*
	349	* The information given in the Armada 388 functional spec is complex.
	350	* They give two different formulas for calculating the offset value,
	351	* but when considering "Offset" as an 8-bit signed integer, they both
	352	* reduce down to (we shall rename "Offset" as "val" here):
	353	*
	354	* val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768
	355	*
	356	* Converting to time, f = 1/t:
	357	* val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768
	358	*
	359	* => t_measured / t_ideal = val * resolution + 1
	360	*
	361	* "offset" in the RTC interface is defined as:
	362	* t = t0 * (1 + offset * 1e-9)
	363	* where t is the desired period, t0 is the measured period with a zero
	364	* offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
	365	* offset = (t_ideal / t_measured - 1) / 1e-9
	366	*
	367	* => t_ideal / t_measured = offset * 1e-9 + 1
	368	*
	369	* so:
	370	*
	371	* offset * 1e-9 + 1 = 1 / (val * resolution + 1)
	372	*
	373	* We want "resolution" to be an integer, so resolution = R * 1e-9, giving
	374	* offset = 1e18 / (val * R + 1e9) - 1e9
	375	* val = (1e18 / (offset + 1e9) - 1e9) / R
	376	* with a common transformation:
	377	* f(x) = 1e18 / (x + 1e9) - 1e9
	378	* offset = f(val * R)
	379	* val = f(offset) / R
	380	*
	381	* Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
	382	*/
	383	static long armada38x_ppb_convert(long ppb)
	384	{
	385	long div = ppb + 1000000000L;
	386
	387	return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
	388	}
	389
	390	static int armada38x_rtc_read_offset(struct device dev, long offset)
	391	{
	392	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	393	unsigned long ccr, flags;
	394	long ppb_cor;
	395
	396	spin_lock_irqsave(&rtc->lock, flags);
	397	ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
	398	spin_unlock_irqrestore(&rtc->lock, flags);
	399
	400	ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
	401	/* ppb_cor + 1000000000L can never be zero */
	402	*offset = armada38x_ppb_convert(ppb_cor);
	403
	404	return 0;
	405	}
	406
	407	static int armada38x_rtc_set_offset(struct device *dev, long offset)
	408	{
	409	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	410	unsigned long ccr = 0;
	411	long ppb_cor, off;
412
413	/*
414	* The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
415	* need to clamp the input. This equates to -484270 .. 488558.
416	* Not only is this to stop out of range "off" but also to
417	* avoid the division by zero in armada38x_ppb_convert().
418	*/
419	offset = clamp(offset, -484270L, 488558L);
420
421	ppb_cor = armada38x_ppb_convert(offset);
422
423	/*
424	* Use low update mode where possible, which gives a better
425	* resolution of correction.
426	*/
427	off = DIV_ROUND_CLOSEST(ppb_cor, 954);
428	if (off > 127 \|\| off < -128) {
429	ccr = RTC_CCR_MODE;
430	off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
431	}
432
433	/*
434	* Armada 388 requires a bit pattern in bits 14..8 depending on
435	* the sign bit: { 0, ~S, S, S, S, S, S }
436	*/
437	ccr \|= (off & 0x3fff) ^ 0x2000;
438	rtc_delayed_write(ccr, rtc, RTC_CCR);
439
440	return 0;
441	}
442
d748c981	443	static const struct rtc_class_ops armada38x_rtc_ops = {
a3a42806 GC	444	.read_time = armada38x_rtc_read_time,
	445	.set_time = armada38x_rtc_set_time,
	446	.read_alarm = armada38x_rtc_read_alarm,
	447	.set_alarm = armada38x_rtc_set_alarm,
	448	.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
f94ffbc2 RK	449	.read_offset = armada38x_rtc_read_offset,
f94ffbc2 RK	450	.set_offset = armada38x_rtc_set_offset,
a3a42806 GC	451	};
a3a42806 GC	452
d748c981 RK	453	static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
	454	.read_time = armada38x_rtc_read_time,
	455	.set_time = armada38x_rtc_set_time,
	456	.read_alarm = armada38x_rtc_read_alarm,
f94ffbc2 RK	457	.read_offset = armada38x_rtc_read_offset,
f94ffbc2 RK	458	.set_offset = armada38x_rtc_set_offset,
d748c981 RK	459	};
d748c981 RK	460
75faea91 GC	461	static const struct armada38x_rtc_data armada38x_data = {
	462	.update_mbus_timing = rtc_update_38x_mbus_timing_params,
	463	.read_rtc_reg = read_rtc_register_38x_wa,
	464	.clear_isr = armada38x_clear_isr,
	465	.unmask_interrupt = armada38x_unmask_interrupt,
	466	.alarm = ALARM1,
	467	};
	468
34f54f57 GC	469	static const struct armada38x_rtc_data armada8k_data = {
	470	.update_mbus_timing = rtc_update_8k_mbus_timing_params,
	471	.read_rtc_reg = read_rtc_register,
	472	.clear_isr = armada8k_clear_isr,
	473	.unmask_interrupt = armada8k_unmask_interrupt,
	474	.alarm = ALARM2,
	475	};
	476
75faea91 GC	477	#ifdef CONFIG_OF
	478	static const struct of_device_id armada38x_rtc_of_match_table[] = {
	479	{
	480	.compatible = "marvell,armada-380-rtc",
	481	.data = &armada38x_data,
	482	},
34f54f57 GC	483	{
	484	.compatible = "marvell,armada-8k-rtc",
	485	.data = &armada8k_data,
	486	},
75faea91 GC	487	{}
	488	};
	489	MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
	490	#endif
	491
a3a42806 GC	492	static __init int armada38x_rtc_probe(struct platform_device *pdev)
a3a42806 GC	493	{
d748c981	494	const struct rtc_class_ops *ops;
a3a42806 GC	495	struct resource *res;
a3a42806 GC	496	struct armada38x_rtc *rtc;
75faea91	497	const struct of_device_id *match;
a3a42806 GC	498	int ret;
a3a42806 GC	499
75faea91 GC	500	match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev);
	501	if (!match)
	502	return -ENODEV;
	503
a3a42806 GC	504	rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
	505	GFP_KERNEL);
	506	if (!rtc)
	507	return -ENOMEM;
	508
844a3073 GC	509	rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
	510	sizeof(struct value_to_freq), GFP_KERNEL);
	511	if (!rtc->val_to_freq)
	512	return -ENOMEM;
	513
a3a42806 GC	514	spin_lock_init(&rtc->lock);
	515
	516	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
	517	rtc->regs = devm_ioremap_resource(&pdev->dev, res);
	518	if (IS_ERR(rtc->regs))
	519	return PTR_ERR(rtc->regs);
	520	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
	521	rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
	522	if (IS_ERR(rtc->regs_soc))
	523	return PTR_ERR(rtc->regs_soc);
	524
	525	rtc->irq = platform_get_irq(pdev, 0);
	526
	527	if (rtc->irq < 0) {
	528	dev_err(&pdev->dev, "no irq\n");
	529	return rtc->irq;
	530	}
	531	if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
	532	0, pdev->name, rtc) < 0) {
	533	dev_warn(&pdev->dev, "Interrupt not available.\n");
	534	rtc->irq = -1;
d748c981 RK	535	}
	536	platform_set_drvdata(pdev, rtc);
	537
	538	if (rtc->irq != -1) {
	539	device_init_wakeup(&pdev->dev, 1);
	540	ops = &armada38x_rtc_ops;
	541	} else {
a3a42806 GC	542	/*
	543	* If there is no interrupt available then we can't
	544	* use the alarm
	545	*/
d748c981	546	ops = &armada38x_rtc_ops_noirq;
a3a42806	547	}
75faea91 GC	548	rtc->data = (struct armada38x_rtc_data *)match->data;
75faea91 GC	549
a3a42806	550
844a3073	551	/* Update RTC-MBUS bridge timing parameters */
75faea91	552	rtc->data->update_mbus_timing(rtc);
844a3073	553
a3a42806	554	rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
d748c981	555	ops, THIS_MODULE);
a3a42806 GC	556	if (IS_ERR(rtc->rtc_dev)) {
	557	ret = PTR_ERR(rtc->rtc_dev);
	558	dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
	559	return ret;
	560	}
	561	return 0;
	562	}
	563
	564	#ifdef CONFIG_PM_SLEEP
	565	static int armada38x_rtc_suspend(struct device *dev)
	566	{
	567	if (device_may_wakeup(dev)) {
	568	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	569
	570	return enable_irq_wake(rtc->irq);
	571	}
	572
	573	return 0;
	574	}
	575
	576	static int armada38x_rtc_resume(struct device *dev)
	577	{
	578	if (device_may_wakeup(dev)) {
	579	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	580
844a3073	581	/* Update RTC-MBUS bridge timing parameters */
75faea91	582	rtc->data->update_mbus_timing(rtc);
844a3073	583
a3a42806 GC	584	return disable_irq_wake(rtc->irq);
	585	}
	586
	587	return 0;
	588	}
	589	#endif
	590
	591	static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
	592	armada38x_rtc_suspend, armada38x_rtc_resume);
	593
a3a42806 GC	594	static struct platform_driver armada38x_rtc_driver = {
	595	.driver = {
	596	.name = "armada38x-rtc",
	597	.pm = &armada38x_rtc_pm_ops,
	598	.of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
	599	},
	600	};
	601
	602	module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
	603
	604	MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
	605	MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
	606	MODULE_LICENSE("GPL");