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Commit | Line | Data |
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788b1fc6 AV |
1 | /* |
2 | * Real Time Clock interface for Linux on Atmel AT91RM9200 | |
3 | * | |
4 | * Copyright (C) 2002 Rick Bronson | |
5 | * | |
6 | * Converted to RTC class model by Andrew Victor | |
7 | * | |
8 | * Ported to Linux 2.6 by Steven Scholz | |
9 | * Based on s3c2410-rtc.c Simtec Electronics | |
10 | * | |
11 | * Based on sa1100-rtc.c by Nils Faerber | |
12 | * Based on rtc.c by Paul Gortmaker | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License | |
16 | * as published by the Free Software Foundation; either version | |
17 | * 2 of the License, or (at your option) any later version. | |
18 | * | |
19 | */ | |
20 | ||
788b1fc6 | 21 | #include <linux/bcd.h> |
11f67a8b | 22 | #include <linux/clk.h> |
74000eb1 | 23 | #include <linux/completion.h> |
788b1fc6 AV |
24 | #include <linux/interrupt.h> |
25 | #include <linux/ioctl.h> | |
14070ade | 26 | #include <linux/io.h> |
74000eb1 AB |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> | |
7c1b68d4 | 29 | #include <linux/of_device.h> |
74000eb1 AB |
30 | #include <linux/of.h> |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/rtc.h> | |
33 | #include <linux/spinlock.h> | |
dd1f1f39 | 34 | #include <linux/suspend.h> |
74000eb1 | 35 | #include <linux/time.h> |
8ecc0bf4 | 36 | #include <linux/uaccess.h> |
fb0d4ec4 | 37 | |
75984df0 | 38 | #include "rtc-at91rm9200.h" |
d73e3cd7 | 39 | |
d28bdfc5 | 40 | #define at91_rtc_read(field) \ |
6da7bb1e | 41 | readl_relaxed(at91_rtc_regs + field) |
d28bdfc5 | 42 | #define at91_rtc_write(field, val) \ |
6da7bb1e | 43 | writel_relaxed((val), at91_rtc_regs + field) |
788b1fc6 | 44 | |
788b1fc6 AV |
45 | #define AT91_RTC_EPOCH 1900UL /* just like arch/arm/common/rtctime.c */ |
46 | ||
de645475 | 47 | struct at91_rtc_config { |
e9f08bbe | 48 | bool use_shadow_imr; |
de645475 JH |
49 | }; |
50 | ||
51 | static const struct at91_rtc_config *at91_rtc_config; | |
788b1fc6 | 52 | static DECLARE_COMPLETION(at91_rtc_updated); |
2fe121e1 | 53 | static DECLARE_COMPLETION(at91_rtc_upd_rdy); |
788b1fc6 | 54 | static unsigned int at91_alarm_year = AT91_RTC_EPOCH; |
d28bdfc5 JCPV |
55 | static void __iomem *at91_rtc_regs; |
56 | static int irq; | |
e9f08bbe JH |
57 | static DEFINE_SPINLOCK(at91_rtc_lock); |
58 | static u32 at91_rtc_shadow_imr; | |
dd1f1f39 BB |
59 | static bool suspended; |
60 | static DEFINE_SPINLOCK(suspended_lock); | |
61 | static unsigned long cached_events; | |
62 | static u32 at91_rtc_imr; | |
11f67a8b | 63 | static struct clk *sclk; |
788b1fc6 | 64 | |
e304fcd0 JH |
65 | static void at91_rtc_write_ier(u32 mask) |
66 | { | |
e9f08bbe JH |
67 | unsigned long flags; |
68 | ||
69 | spin_lock_irqsave(&at91_rtc_lock, flags); | |
70 | at91_rtc_shadow_imr |= mask; | |
e304fcd0 | 71 | at91_rtc_write(AT91_RTC_IER, mask); |
e9f08bbe | 72 | spin_unlock_irqrestore(&at91_rtc_lock, flags); |
e304fcd0 JH |
73 | } |
74 | ||
75 | static void at91_rtc_write_idr(u32 mask) | |
76 | { | |
e9f08bbe JH |
77 | unsigned long flags; |
78 | ||
79 | spin_lock_irqsave(&at91_rtc_lock, flags); | |
e304fcd0 | 80 | at91_rtc_write(AT91_RTC_IDR, mask); |
e9f08bbe JH |
81 | /* |
82 | * Register read back (of any RTC-register) needed to make sure | |
83 | * IDR-register write has reached the peripheral before updating | |
84 | * shadow mask. | |
85 | * | |
86 | * Note that there is still a possibility that the mask is updated | |
87 | * before interrupts have actually been disabled in hardware. The only | |
88 | * way to be certain would be to poll the IMR-register, which is is | |
89 | * the very register we are trying to emulate. The register read back | |
90 | * is a reasonable heuristic. | |
91 | */ | |
92 | at91_rtc_read(AT91_RTC_SR); | |
93 | at91_rtc_shadow_imr &= ~mask; | |
94 | spin_unlock_irqrestore(&at91_rtc_lock, flags); | |
e304fcd0 JH |
95 | } |
96 | ||
97 | static u32 at91_rtc_read_imr(void) | |
98 | { | |
e9f08bbe JH |
99 | unsigned long flags; |
100 | u32 mask; | |
101 | ||
102 | if (at91_rtc_config->use_shadow_imr) { | |
103 | spin_lock_irqsave(&at91_rtc_lock, flags); | |
104 | mask = at91_rtc_shadow_imr; | |
105 | spin_unlock_irqrestore(&at91_rtc_lock, flags); | |
106 | } else { | |
107 | mask = at91_rtc_read(AT91_RTC_IMR); | |
108 | } | |
109 | ||
110 | return mask; | |
e304fcd0 JH |
111 | } |
112 | ||
788b1fc6 AV |
113 | /* |
114 | * Decode time/date into rtc_time structure | |
115 | */ | |
e7a8bb12 AM |
116 | static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg, |
117 | struct rtc_time *tm) | |
788b1fc6 AV |
118 | { |
119 | unsigned int time, date; | |
120 | ||
121 | /* must read twice in case it changes */ | |
122 | do { | |
d28bdfc5 JCPV |
123 | time = at91_rtc_read(timereg); |
124 | date = at91_rtc_read(calreg); | |
125 | } while ((time != at91_rtc_read(timereg)) || | |
126 | (date != at91_rtc_read(calreg))); | |
788b1fc6 | 127 | |
fe20ba70 AB |
128 | tm->tm_sec = bcd2bin((time & AT91_RTC_SEC) >> 0); |
129 | tm->tm_min = bcd2bin((time & AT91_RTC_MIN) >> 8); | |
130 | tm->tm_hour = bcd2bin((time & AT91_RTC_HOUR) >> 16); | |
788b1fc6 AV |
131 | |
132 | /* | |
133 | * The Calendar Alarm register does not have a field for | |
134 | * the year - so these will return an invalid value. When an | |
25985edc | 135 | * alarm is set, at91_alarm_year will store the current year. |
788b1fc6 | 136 | */ |
fe20ba70 AB |
137 | tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */ |
138 | tm->tm_year += bcd2bin((date & AT91_RTC_YEAR) >> 8); /* year */ | |
788b1fc6 | 139 | |
fe20ba70 AB |
140 | tm->tm_wday = bcd2bin((date & AT91_RTC_DAY) >> 21) - 1; /* day of the week [0-6], Sunday=0 */ |
141 | tm->tm_mon = bcd2bin((date & AT91_RTC_MONTH) >> 16) - 1; | |
142 | tm->tm_mday = bcd2bin((date & AT91_RTC_DATE) >> 24); | |
788b1fc6 AV |
143 | } |
144 | ||
145 | /* | |
146 | * Read current time and date in RTC | |
147 | */ | |
148 | static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) | |
149 | { | |
150 | at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm); | |
151 | tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); | |
152 | tm->tm_year = tm->tm_year - 1900; | |
153 | ||
6588208c | 154 | dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__, |
e7a8bb12 AM |
155 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
156 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
788b1fc6 AV |
157 | |
158 | return 0; | |
159 | } | |
160 | ||
161 | /* | |
162 | * Set current time and date in RTC | |
163 | */ | |
164 | static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) | |
165 | { | |
166 | unsigned long cr; | |
167 | ||
6588208c | 168 | dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__, |
e7a8bb12 AM |
169 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
170 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
788b1fc6 | 171 | |
2fe121e1 BB |
172 | wait_for_completion(&at91_rtc_upd_rdy); |
173 | ||
788b1fc6 | 174 | /* Stop Time/Calendar from counting */ |
d28bdfc5 JCPV |
175 | cr = at91_rtc_read(AT91_RTC_CR); |
176 | at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM); | |
788b1fc6 | 177 | |
e304fcd0 | 178 | at91_rtc_write_ier(AT91_RTC_ACKUPD); |
e7a8bb12 | 179 | wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */ |
e304fcd0 | 180 | at91_rtc_write_idr(AT91_RTC_ACKUPD); |
788b1fc6 | 181 | |
d28bdfc5 | 182 | at91_rtc_write(AT91_RTC_TIMR, |
fe20ba70 AB |
183 | bin2bcd(tm->tm_sec) << 0 |
184 | | bin2bcd(tm->tm_min) << 8 | |
185 | | bin2bcd(tm->tm_hour) << 16); | |
788b1fc6 | 186 | |
d28bdfc5 | 187 | at91_rtc_write(AT91_RTC_CALR, |
fe20ba70 AB |
188 | bin2bcd((tm->tm_year + 1900) / 100) /* century */ |
189 | | bin2bcd(tm->tm_year % 100) << 8 /* year */ | |
190 | | bin2bcd(tm->tm_mon + 1) << 16 /* tm_mon starts at zero */ | |
191 | | bin2bcd(tm->tm_wday + 1) << 21 /* day of the week [0-6], Sunday=0 */ | |
192 | | bin2bcd(tm->tm_mday) << 24); | |
788b1fc6 AV |
193 | |
194 | /* Restart Time/Calendar */ | |
d28bdfc5 | 195 | cr = at91_rtc_read(AT91_RTC_CR); |
2fe121e1 | 196 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV); |
d28bdfc5 | 197 | at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM)); |
2fe121e1 | 198 | at91_rtc_write_ier(AT91_RTC_SECEV); |
788b1fc6 AV |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* | |
204 | * Read alarm time and date in RTC | |
205 | */ | |
206 | static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
207 | { | |
208 | struct rtc_time *tm = &alrm->time; | |
209 | ||
210 | at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm); | |
788b1fc6 AV |
211 | tm->tm_year = at91_alarm_year - 1900; |
212 | ||
e304fcd0 | 213 | alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM) |
a2db8dfc DB |
214 | ? 1 : 0; |
215 | ||
6588208c | 216 | dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__, |
e7a8bb12 AM |
217 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
218 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
788b1fc6 AV |
219 | |
220 | return 0; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Set alarm time and date in RTC | |
225 | */ | |
226 | static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
227 | { | |
228 | struct rtc_time tm; | |
229 | ||
230 | at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, &tm); | |
231 | ||
232 | at91_alarm_year = tm.tm_year; | |
233 | ||
eb3c2272 LP |
234 | tm.tm_mon = alrm->time.tm_mon; |
235 | tm.tm_mday = alrm->time.tm_mday; | |
788b1fc6 AV |
236 | tm.tm_hour = alrm->time.tm_hour; |
237 | tm.tm_min = alrm->time.tm_min; | |
238 | tm.tm_sec = alrm->time.tm_sec; | |
239 | ||
e304fcd0 | 240 | at91_rtc_write_idr(AT91_RTC_ALARM); |
d28bdfc5 | 241 | at91_rtc_write(AT91_RTC_TIMALR, |
fe20ba70 AB |
242 | bin2bcd(tm.tm_sec) << 0 |
243 | | bin2bcd(tm.tm_min) << 8 | |
244 | | bin2bcd(tm.tm_hour) << 16 | |
788b1fc6 | 245 | | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN); |
d28bdfc5 | 246 | at91_rtc_write(AT91_RTC_CALALR, |
fe20ba70 AB |
247 | bin2bcd(tm.tm_mon + 1) << 16 /* tm_mon starts at zero */ |
248 | | bin2bcd(tm.tm_mday) << 24 | |
788b1fc6 AV |
249 | | AT91_RTC_DATEEN | AT91_RTC_MTHEN); |
250 | ||
449321b3 | 251 | if (alrm->enabled) { |
d28bdfc5 | 252 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
e304fcd0 | 253 | at91_rtc_write_ier(AT91_RTC_ALARM); |
449321b3 | 254 | } |
5d4675a8 | 255 | |
6588208c | 256 | dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__, |
e7a8bb12 AM |
257 | at91_alarm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, |
258 | tm.tm_min, tm.tm_sec); | |
788b1fc6 AV |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
16380c15 JS |
263 | static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
264 | { | |
6588208c | 265 | dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled); |
16380c15 JS |
266 | |
267 | if (enabled) { | |
d28bdfc5 | 268 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
e304fcd0 | 269 | at91_rtc_write_ier(AT91_RTC_ALARM); |
e24b0bfa | 270 | } else |
e304fcd0 | 271 | at91_rtc_write_idr(AT91_RTC_ALARM); |
16380c15 JS |
272 | |
273 | return 0; | |
274 | } | |
788b1fc6 AV |
275 | /* |
276 | * Provide additional RTC information in /proc/driver/rtc | |
277 | */ | |
278 | static int at91_rtc_proc(struct device *dev, struct seq_file *seq) | |
279 | { | |
e304fcd0 | 280 | unsigned long imr = at91_rtc_read_imr(); |
e24b0bfa | 281 | |
e7a8bb12 | 282 | seq_printf(seq, "update_IRQ\t: %s\n", |
e24b0bfa | 283 | (imr & AT91_RTC_ACKUPD) ? "yes" : "no"); |
e7a8bb12 | 284 | seq_printf(seq, "periodic_IRQ\t: %s\n", |
e24b0bfa | 285 | (imr & AT91_RTC_SECEV) ? "yes" : "no"); |
788b1fc6 AV |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /* | |
291 | * IRQ handler for the RTC | |
292 | */ | |
7d12e780 | 293 | static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id) |
788b1fc6 | 294 | { |
e7a8bb12 | 295 | struct platform_device *pdev = dev_id; |
788b1fc6 AV |
296 | struct rtc_device *rtc = platform_get_drvdata(pdev); |
297 | unsigned int rtsr; | |
298 | unsigned long events = 0; | |
dd1f1f39 | 299 | int ret = IRQ_NONE; |
788b1fc6 | 300 | |
dd1f1f39 | 301 | spin_lock(&suspended_lock); |
e304fcd0 | 302 | rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr(); |
788b1fc6 AV |
303 | if (rtsr) { /* this interrupt is shared! Is it ours? */ |
304 | if (rtsr & AT91_RTC_ALARM) | |
305 | events |= (RTC_AF | RTC_IRQF); | |
2fe121e1 BB |
306 | if (rtsr & AT91_RTC_SECEV) { |
307 | complete(&at91_rtc_upd_rdy); | |
308 | at91_rtc_write_idr(AT91_RTC_SECEV); | |
309 | } | |
788b1fc6 AV |
310 | if (rtsr & AT91_RTC_ACKUPD) |
311 | complete(&at91_rtc_updated); | |
312 | ||
d28bdfc5 | 313 | at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */ |
788b1fc6 | 314 | |
dd1f1f39 BB |
315 | if (!suspended) { |
316 | rtc_update_irq(rtc, 1, events); | |
788b1fc6 | 317 | |
dd1f1f39 BB |
318 | dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n", |
319 | __func__, events >> 8, events & 0x000000FF); | |
320 | } else { | |
321 | cached_events |= events; | |
322 | at91_rtc_write_idr(at91_rtc_imr); | |
323 | pm_system_wakeup(); | |
324 | } | |
788b1fc6 | 325 | |
dd1f1f39 | 326 | ret = IRQ_HANDLED; |
788b1fc6 | 327 | } |
88601683 | 328 | spin_unlock(&suspended_lock); |
dd1f1f39 BB |
329 | |
330 | return ret; | |
788b1fc6 AV |
331 | } |
332 | ||
de645475 JH |
333 | static const struct at91_rtc_config at91rm9200_config = { |
334 | }; | |
335 | ||
bba00e59 JH |
336 | static const struct at91_rtc_config at91sam9x5_config = { |
337 | .use_shadow_imr = true, | |
338 | }; | |
339 | ||
de645475 JH |
340 | #ifdef CONFIG_OF |
341 | static const struct of_device_id at91_rtc_dt_ids[] = { | |
342 | { | |
343 | .compatible = "atmel,at91rm9200-rtc", | |
344 | .data = &at91rm9200_config, | |
bba00e59 JH |
345 | }, { |
346 | .compatible = "atmel,at91sam9x5-rtc", | |
347 | .data = &at91sam9x5_config, | |
de645475 JH |
348 | }, { |
349 | /* sentinel */ | |
350 | } | |
351 | }; | |
352 | MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); | |
353 | #endif | |
354 | ||
355 | static const struct at91_rtc_config * | |
356 | at91_rtc_get_config(struct platform_device *pdev) | |
357 | { | |
358 | const struct of_device_id *match; | |
359 | ||
360 | if (pdev->dev.of_node) { | |
361 | match = of_match_node(at91_rtc_dt_ids, pdev->dev.of_node); | |
362 | if (!match) | |
363 | return NULL; | |
364 | return (const struct at91_rtc_config *)match->data; | |
365 | } | |
366 | ||
367 | return &at91rm9200_config; | |
368 | } | |
369 | ||
ff8371ac | 370 | static const struct rtc_class_ops at91_rtc_ops = { |
788b1fc6 AV |
371 | .read_time = at91_rtc_readtime, |
372 | .set_time = at91_rtc_settime, | |
373 | .read_alarm = at91_rtc_readalarm, | |
374 | .set_alarm = at91_rtc_setalarm, | |
375 | .proc = at91_rtc_proc, | |
16380c15 | 376 | .alarm_irq_enable = at91_rtc_alarm_irq_enable, |
788b1fc6 AV |
377 | }; |
378 | ||
379 | /* | |
380 | * Initialize and install RTC driver | |
381 | */ | |
382 | static int __init at91_rtc_probe(struct platform_device *pdev) | |
383 | { | |
384 | struct rtc_device *rtc; | |
d28bdfc5 JCPV |
385 | struct resource *regs; |
386 | int ret = 0; | |
788b1fc6 | 387 | |
de645475 JH |
388 | at91_rtc_config = at91_rtc_get_config(pdev); |
389 | if (!at91_rtc_config) | |
390 | return -ENODEV; | |
391 | ||
d28bdfc5 JCPV |
392 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
393 | if (!regs) { | |
394 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
395 | return -ENXIO; | |
396 | } | |
397 | ||
398 | irq = platform_get_irq(pdev, 0); | |
399 | if (irq < 0) { | |
400 | dev_err(&pdev->dev, "no irq resource defined\n"); | |
401 | return -ENXIO; | |
402 | } | |
403 | ||
f3766250 SK |
404 | at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start, |
405 | resource_size(regs)); | |
d28bdfc5 JCPV |
406 | if (!at91_rtc_regs) { |
407 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
408 | return -ENOMEM; | |
409 | } | |
410 | ||
735ae205 AB |
411 | rtc = devm_rtc_allocate_device(&pdev->dev); |
412 | if (IS_ERR(rtc)) | |
413 | return PTR_ERR(rtc); | |
414 | platform_set_drvdata(pdev, rtc); | |
415 | ||
11f67a8b AB |
416 | sclk = devm_clk_get(&pdev->dev, NULL); |
417 | if (IS_ERR(sclk)) | |
418 | return PTR_ERR(sclk); | |
419 | ||
420 | ret = clk_prepare_enable(sclk); | |
421 | if (ret) { | |
422 | dev_err(&pdev->dev, "Could not enable slow clock\n"); | |
423 | return ret; | |
424 | } | |
425 | ||
d28bdfc5 JCPV |
426 | at91_rtc_write(AT91_RTC_CR, 0); |
427 | at91_rtc_write(AT91_RTC_MR, 0); /* 24 hour mode */ | |
788b1fc6 AV |
428 | |
429 | /* Disable all interrupts */ | |
e304fcd0 | 430 | at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
e7a8bb12 AM |
431 | AT91_RTC_SECEV | AT91_RTC_TIMEV | |
432 | AT91_RTC_CALEV); | |
788b1fc6 | 433 | |
f3766250 | 434 | ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt, |
dd1f1f39 BB |
435 | IRQF_SHARED | IRQF_COND_SUSPEND, |
436 | "at91_rtc", pdev); | |
788b1fc6 | 437 | if (ret) { |
6588208c | 438 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq); |
11f67a8b | 439 | goto err_clk; |
788b1fc6 AV |
440 | } |
441 | ||
5d4675a8 DB |
442 | /* cpu init code should really have flagged this device as |
443 | * being wake-capable; if it didn't, do that here. | |
444 | */ | |
445 | if (!device_can_wakeup(&pdev->dev)) | |
446 | device_init_wakeup(&pdev->dev, 1); | |
447 | ||
735ae205 AB |
448 | rtc->ops = &at91_rtc_ops; |
449 | ret = rtc_register_device(rtc); | |
450 | if (ret) | |
11f67a8b | 451 | goto err_clk; |
788b1fc6 | 452 | |
2fe121e1 BB |
453 | /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy |
454 | * completion. | |
455 | */ | |
456 | at91_rtc_write_ier(AT91_RTC_SECEV); | |
457 | ||
6588208c | 458 | dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n"); |
788b1fc6 | 459 | return 0; |
11f67a8b AB |
460 | |
461 | err_clk: | |
462 | clk_disable_unprepare(sclk); | |
463 | ||
464 | return ret; | |
788b1fc6 AV |
465 | } |
466 | ||
467 | /* | |
468 | * Disable and remove the RTC driver | |
469 | */ | |
5d4675a8 | 470 | static int __exit at91_rtc_remove(struct platform_device *pdev) |
788b1fc6 | 471 | { |
788b1fc6 | 472 | /* Disable all interrupts */ |
e304fcd0 | 473 | at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
e7a8bb12 AM |
474 | AT91_RTC_SECEV | AT91_RTC_TIMEV | |
475 | AT91_RTC_CALEV); | |
788b1fc6 | 476 | |
11f67a8b AB |
477 | clk_disable_unprepare(sclk); |
478 | ||
788b1fc6 AV |
479 | return 0; |
480 | } | |
481 | ||
51a0d036 JH |
482 | static void at91_rtc_shutdown(struct platform_device *pdev) |
483 | { | |
484 | /* Disable all interrupts */ | |
485 | at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM | | |
486 | AT91_RTC_SECEV | AT91_RTC_TIMEV | | |
487 | AT91_RTC_CALEV); | |
488 | } | |
489 | ||
6975a9c1 | 490 | #ifdef CONFIG_PM_SLEEP |
788b1fc6 AV |
491 | |
492 | /* AT91RM9200 RTC Power management control */ | |
493 | ||
dac94d9e | 494 | static int at91_rtc_suspend(struct device *dev) |
788b1fc6 | 495 | { |
90b4d648 DB |
496 | /* this IRQ is shared with DBGU and other hardware which isn't |
497 | * necessarily doing PM like we are... | |
498 | */ | |
921372bf WY |
499 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
500 | ||
e304fcd0 | 501 | at91_rtc_imr = at91_rtc_read_imr() |
e24b0bfa JH |
502 | & (AT91_RTC_ALARM|AT91_RTC_SECEV); |
503 | if (at91_rtc_imr) { | |
dd1f1f39 BB |
504 | if (device_may_wakeup(dev)) { |
505 | unsigned long flags; | |
506 | ||
d28bdfc5 | 507 | enable_irq_wake(irq); |
dd1f1f39 BB |
508 | |
509 | spin_lock_irqsave(&suspended_lock, flags); | |
510 | suspended = true; | |
511 | spin_unlock_irqrestore(&suspended_lock, flags); | |
512 | } else { | |
e304fcd0 | 513 | at91_rtc_write_idr(at91_rtc_imr); |
dd1f1f39 | 514 | } |
e24b0bfa | 515 | } |
788b1fc6 AV |
516 | return 0; |
517 | } | |
518 | ||
dac94d9e | 519 | static int at91_rtc_resume(struct device *dev) |
788b1fc6 | 520 | { |
dd1f1f39 BB |
521 | struct rtc_device *rtc = dev_get_drvdata(dev); |
522 | ||
e24b0bfa | 523 | if (at91_rtc_imr) { |
dd1f1f39 BB |
524 | if (device_may_wakeup(dev)) { |
525 | unsigned long flags; | |
526 | ||
527 | spin_lock_irqsave(&suspended_lock, flags); | |
528 | ||
529 | if (cached_events) { | |
530 | rtc_update_irq(rtc, 1, cached_events); | |
531 | cached_events = 0; | |
532 | } | |
533 | ||
534 | suspended = false; | |
535 | spin_unlock_irqrestore(&suspended_lock, flags); | |
536 | ||
d28bdfc5 | 537 | disable_irq_wake(irq); |
dd1f1f39 BB |
538 | } |
539 | at91_rtc_write_ier(at91_rtc_imr); | |
90b4d648 | 540 | } |
788b1fc6 AV |
541 | return 0; |
542 | } | |
788b1fc6 AV |
543 | #endif |
544 | ||
6975a9c1 JH |
545 | static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); |
546 | ||
788b1fc6 | 547 | static struct platform_driver at91_rtc_driver = { |
5d4675a8 | 548 | .remove = __exit_p(at91_rtc_remove), |
51a0d036 | 549 | .shutdown = at91_rtc_shutdown, |
788b1fc6 AV |
550 | .driver = { |
551 | .name = "at91_rtc", | |
6975a9c1 | 552 | .pm = &at91_rtc_pm_ops, |
7c1b68d4 | 553 | .of_match_table = of_match_ptr(at91_rtc_dt_ids), |
788b1fc6 AV |
554 | }, |
555 | }; | |
556 | ||
ac36960f | 557 | module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe); |
788b1fc6 AV |
558 | |
559 | MODULE_AUTHOR("Rick Bronson"); | |
560 | MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200"); | |
561 | MODULE_LICENSE("GPL"); | |
ad28a07b | 562 | MODULE_ALIAS("platform:at91_rtc"); |