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Commit | Line | Data |
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8cc75c9a WB |
1 | /* |
2 | * Blackfin On-Chip Real Time Clock Driver | |
9980060b | 3 | * Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x |
8cc75c9a | 4 | * |
d7c7ef90 | 5 | * Copyright 2004-2010 Analog Devices Inc. |
8cc75c9a WB |
6 | * |
7 | * Enter bugs at http://blackfin.uclinux.org/ | |
8 | * | |
9 | * Licensed under the GPL-2 or later. | |
10 | */ | |
11 | ||
12 | /* The biggest issue we deal with in this driver is that register writes are | |
13 | * synced to the RTC frequency of 1Hz. So if you write to a register and | |
14 | * attempt to write again before the first write has completed, the new write | |
15 | * is simply discarded. This can easily be troublesome if userspace disables | |
16 | * one event (say periodic) and then right after enables an event (say alarm). | |
17 | * Since all events are maintained in the same interrupt mask register, if | |
18 | * we wrote to it to disable the first event and then wrote to it again to | |
19 | * enable the second event, that second event would not be enabled as the | |
20 | * write would be discarded and things quickly fall apart. | |
21 | * | |
22 | * To keep this delay from significantly degrading performance (we, in theory, | |
23 | * would have to sleep for up to 1 second everytime we wanted to write a | |
24 | * register), we only check the write pending status before we start to issue | |
25 | * a new write. We bank on the idea that it doesnt matter when the sync | |
26 | * happens so long as we don't attempt another write before it does. The only | |
27 | * time userspace would take this penalty is when they try and do multiple | |
28 | * operations right after another ... but in this case, they need to take the | |
29 | * sync penalty, so we should be OK. | |
30 | * | |
31 | * Also note that the RTC_ISTAT register does not suffer this penalty; its | |
32 | * writes to clear status registers complete immediately. | |
33 | */ | |
34 | ||
26cb8bb2 MF |
35 | /* It may seem odd that there is no SWCNT code in here (which would be exposed |
36 | * via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral | |
37 | * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ | |
38 | * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs. | |
39 | * The same exact behavior can be accomplished by using the update interrupt | |
40 | * event (UIE). Maybe down the line the RTC peripheral will suck less in which | |
41 | * case we can re-introduce PIE support. | |
42 | */ | |
43 | ||
8cc75c9a | 44 | #include <linux/bcd.h> |
095b9d54 MF |
45 | #include <linux/completion.h> |
46 | #include <linux/delay.h> | |
8cc75c9a | 47 | #include <linux/init.h> |
095b9d54 MF |
48 | #include <linux/interrupt.h> |
49 | #include <linux/kernel.h> | |
50 | #include <linux/module.h> | |
8cc75c9a | 51 | #include <linux/platform_device.h> |
095b9d54 | 52 | #include <linux/rtc.h> |
8cc75c9a | 53 | #include <linux/seq_file.h> |
5a0e3ad6 | 54 | #include <linux/slab.h> |
8cc75c9a WB |
55 | |
56 | #include <asm/blackfin.h> | |
57 | ||
5438de44 | 58 | #define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__) |
8cc75c9a WB |
59 | |
60 | struct bfin_rtc { | |
61 | struct rtc_device *rtc_dev; | |
62 | struct rtc_time rtc_alarm; | |
095b9d54 | 63 | u16 rtc_wrote_regs; |
8cc75c9a WB |
64 | }; |
65 | ||
66 | /* Bit values for the ISTAT / ICTL registers */ | |
67 | #define RTC_ISTAT_WRITE_COMPLETE 0x8000 | |
68 | #define RTC_ISTAT_WRITE_PENDING 0x4000 | |
69 | #define RTC_ISTAT_ALARM_DAY 0x0040 | |
70 | #define RTC_ISTAT_24HR 0x0020 | |
71 | #define RTC_ISTAT_HOUR 0x0010 | |
72 | #define RTC_ISTAT_MIN 0x0008 | |
73 | #define RTC_ISTAT_SEC 0x0004 | |
74 | #define RTC_ISTAT_ALARM 0x0002 | |
75 | #define RTC_ISTAT_STOPWATCH 0x0001 | |
76 | ||
77 | /* Shift values for RTC_STAT register */ | |
78 | #define DAY_BITS_OFF 17 | |
79 | #define HOUR_BITS_OFF 12 | |
80 | #define MIN_BITS_OFF 6 | |
81 | #define SEC_BITS_OFF 0 | |
82 | ||
83 | /* Some helper functions to convert between the common RTC notion of time | |
5c236343 | 84 | * and the internal Blackfin notion that is encoded in 32bits. |
8cc75c9a WB |
85 | */ |
86 | static inline u32 rtc_time_to_bfin(unsigned long now) | |
87 | { | |
88 | u32 sec = (now % 60); | |
89 | u32 min = (now % (60 * 60)) / 60; | |
90 | u32 hour = (now % (60 * 60 * 24)) / (60 * 60); | |
91 | u32 days = (now / (60 * 60 * 24)); | |
92 | return (sec << SEC_BITS_OFF) + | |
93 | (min << MIN_BITS_OFF) + | |
94 | (hour << HOUR_BITS_OFF) + | |
95 | (days << DAY_BITS_OFF); | |
96 | } | |
97 | static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin) | |
98 | { | |
99 | return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) + | |
100 | (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) + | |
101 | (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) + | |
102 | (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24); | |
103 | } | |
104 | static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm) | |
105 | { | |
106 | rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm); | |
107 | } | |
108 | ||
095b9d54 MF |
109 | /** |
110 | * bfin_rtc_sync_pending - make sure pending writes have complete | |
111 | * | |
112 | * Wait for the previous write to a RTC register to complete. | |
8cc75c9a WB |
113 | * Unfortunately, we can't sleep here as that introduces a race condition when |
114 | * turning on interrupt events. Consider this: | |
115 | * - process sets alarm | |
116 | * - process enables alarm | |
117 | * - process sleeps while waiting for rtc write to sync | |
118 | * - interrupt fires while process is sleeping | |
119 | * - interrupt acks the event by writing to ISTAT | |
120 | * - interrupt sets the WRITE PENDING bit | |
121 | * - interrupt handler finishes | |
122 | * - process wakes up, sees WRITE PENDING bit set, goes to sleep | |
123 | * - interrupt fires while process is sleeping | |
124 | * If anyone can point out the obvious solution here, i'm listening :). This | |
125 | * shouldn't be an issue on an SMP or preempt system as this function should | |
126 | * only be called with the rtc lock held. | |
5c236343 MF |
127 | * |
128 | * Other options: | |
129 | * - disable PREN so the sync happens at 32.768kHZ ... but this changes the | |
130 | * inc rate for all RTC registers from 1HZ to 32.768kHZ ... | |
131 | * - use the write complete IRQ | |
8cc75c9a | 132 | */ |
095b9d54 MF |
133 | /* |
134 | static void bfin_rtc_sync_pending_polled(void) | |
8cc75c9a | 135 | { |
095b9d54 | 136 | while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE)) |
8cc75c9a WB |
137 | if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)) |
138 | break; | |
8cc75c9a WB |
139 | bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); |
140 | } | |
095b9d54 MF |
141 | */ |
142 | static DECLARE_COMPLETION(bfin_write_complete); | |
143 | static void bfin_rtc_sync_pending(struct device *dev) | |
144 | { | |
145 | dev_dbg_stamp(dev); | |
146 | while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) | |
147 | wait_for_completion_timeout(&bfin_write_complete, HZ * 5); | |
148 | dev_dbg_stamp(dev); | |
149 | } | |
8cc75c9a | 150 | |
095b9d54 MF |
151 | /** |
152 | * bfin_rtc_reset - set RTC to sane/known state | |
153 | * | |
154 | * Initialize the RTC. Enable pre-scaler to scale RTC clock | |
155 | * to 1Hz and clear interrupt/status registers. | |
156 | */ | |
3b128fe0 | 157 | static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl) |
8cc75c9a | 158 | { |
5438de44 | 159 | struct bfin_rtc *rtc = dev_get_drvdata(dev); |
095b9d54 MF |
160 | dev_dbg_stamp(dev); |
161 | bfin_rtc_sync_pending(dev); | |
8cc75c9a | 162 | bfin_write_RTC_PREN(0x1); |
3b128fe0 | 163 | bfin_write_RTC_ICTL(rtc_ictl); |
8cc75c9a WB |
164 | bfin_write_RTC_ALARM(0); |
165 | bfin_write_RTC_ISTAT(0xFFFF); | |
095b9d54 | 166 | rtc->rtc_wrote_regs = 0; |
8cc75c9a WB |
167 | } |
168 | ||
095b9d54 MF |
169 | /** |
170 | * bfin_rtc_interrupt - handle interrupt from RTC | |
171 | * | |
172 | * Since we handle all RTC events here, we have to make sure the requested | |
173 | * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT) | |
174 | * always gets updated regardless of the interrupt being enabled. So when one | |
175 | * even we care about (e.g. stopwatch) goes off, we don't want to turn around | |
176 | * and say that other events have happened as well (e.g. second). We do not | |
177 | * have to worry about pending writes to the RTC_ICTL register as interrupts | |
178 | * only fire if they are enabled in the RTC_ICTL register. | |
179 | */ | |
8cc75c9a WB |
180 | static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id) |
181 | { | |
d7827d88 MF |
182 | struct device *dev = dev_id; |
183 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
8cc75c9a | 184 | unsigned long events = 0; |
095b9d54 | 185 | bool write_complete = false; |
286f9f95 | 186 | u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits; |
8cc75c9a | 187 | |
5438de44 | 188 | dev_dbg_stamp(dev); |
8cc75c9a | 189 | |
8cc75c9a | 190 | rtc_istat = bfin_read_RTC_ISTAT(); |
095b9d54 | 191 | rtc_ictl = bfin_read_RTC_ICTL(); |
286f9f95 | 192 | rtc_istat_clear = 0; |
8cc75c9a | 193 | |
286f9f95 MF |
194 | bits = RTC_ISTAT_WRITE_COMPLETE; |
195 | if (rtc_istat & bits) { | |
196 | rtc_istat_clear |= bits; | |
095b9d54 MF |
197 | write_complete = true; |
198 | complete(&bfin_write_complete); | |
8cc75c9a WB |
199 | } |
200 | ||
286f9f95 MF |
201 | bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY); |
202 | if (rtc_ictl & bits) { | |
203 | if (rtc_istat & bits) { | |
204 | rtc_istat_clear |= bits; | |
095b9d54 MF |
205 | events |= RTC_AF | RTC_IRQF; |
206 | } | |
8cc75c9a WB |
207 | } |
208 | ||
286f9f95 MF |
209 | bits = RTC_ISTAT_SEC; |
210 | if (rtc_ictl & bits) { | |
211 | if (rtc_istat & bits) { | |
212 | rtc_istat_clear |= bits; | |
095b9d54 MF |
213 | events |= RTC_UF | RTC_IRQF; |
214 | } | |
215 | } | |
8cc75c9a | 216 | |
095b9d54 MF |
217 | if (events) |
218 | rtc_update_irq(rtc->rtc_dev, 1, events); | |
8cc75c9a | 219 | |
286f9f95 MF |
220 | if (write_complete || events) { |
221 | bfin_write_RTC_ISTAT(rtc_istat_clear); | |
095b9d54 | 222 | return IRQ_HANDLED; |
286f9f95 | 223 | } else |
095b9d54 | 224 | return IRQ_NONE; |
8cc75c9a WB |
225 | } |
226 | ||
605eb8b3 | 227 | static void bfin_rtc_int_set(u16 rtc_int) |
095b9d54 MF |
228 | { |
229 | bfin_write_RTC_ISTAT(rtc_int); | |
230 | bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int); | |
231 | } | |
605eb8b3 | 232 | static void bfin_rtc_int_clear(u16 rtc_int) |
095b9d54 MF |
233 | { |
234 | bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int); | |
235 | } | |
236 | static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc) | |
237 | { | |
238 | /* Blackfin has different bits for whether the alarm is | |
239 | * more than 24 hours away. | |
240 | */ | |
605eb8b3 | 241 | bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY); |
095b9d54 | 242 | } |
8cc75c9a | 243 | |
16380c15 JS |
244 | static int bfin_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
245 | { | |
246 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
247 | ||
248 | dev_dbg_stamp(dev); | |
249 | if (enabled) | |
250 | bfin_rtc_int_set_alarm(rtc); | |
251 | else | |
252 | bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); | |
253 | } | |
254 | ||
8cc75c9a WB |
255 | static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm) |
256 | { | |
257 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
258 | ||
5438de44 | 259 | dev_dbg_stamp(dev); |
8cc75c9a | 260 | |
095b9d54 MF |
261 | if (rtc->rtc_wrote_regs & 0x1) |
262 | bfin_rtc_sync_pending(dev); | |
263 | ||
8cc75c9a | 264 | rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm); |
8cc75c9a WB |
265 | |
266 | return 0; | |
267 | } | |
268 | ||
269 | static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
270 | { | |
271 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
272 | int ret; | |
273 | unsigned long now; | |
274 | ||
5438de44 | 275 | dev_dbg_stamp(dev); |
8cc75c9a | 276 | |
8cc75c9a WB |
277 | ret = rtc_tm_to_time(tm, &now); |
278 | if (ret == 0) { | |
095b9d54 MF |
279 | if (rtc->rtc_wrote_regs & 0x1) |
280 | bfin_rtc_sync_pending(dev); | |
8cc75c9a | 281 | bfin_write_RTC_STAT(rtc_time_to_bfin(now)); |
095b9d54 | 282 | rtc->rtc_wrote_regs = 0x1; |
8cc75c9a WB |
283 | } |
284 | ||
8cc75c9a WB |
285 | return ret; |
286 | } | |
287 | ||
288 | static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
289 | { | |
290 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
5438de44 | 291 | dev_dbg_stamp(dev); |
48c1a56b | 292 | alrm->time = rtc->rtc_alarm; |
095b9d54 | 293 | bfin_rtc_sync_pending(dev); |
68db3047 | 294 | alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); |
8cc75c9a WB |
295 | return 0; |
296 | } | |
297 | ||
298 | static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
299 | { | |
300 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
095b9d54 MF |
301 | unsigned long rtc_alarm; |
302 | ||
5438de44 | 303 | dev_dbg_stamp(dev); |
095b9d54 MF |
304 | |
305 | if (rtc_tm_to_time(&alrm->time, &rtc_alarm)) | |
306 | return -EINVAL; | |
307 | ||
68db3047 | 308 | rtc->rtc_alarm = alrm->time; |
095b9d54 MF |
309 | |
310 | bfin_rtc_sync_pending(dev); | |
311 | bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm)); | |
312 | if (alrm->enabled) | |
313 | bfin_rtc_int_set_alarm(rtc); | |
314 | ||
8cc75c9a WB |
315 | return 0; |
316 | } | |
317 | ||
318 | static int bfin_rtc_proc(struct device *dev, struct seq_file *seq) | |
319 | { | |
64061160 | 320 | #define yesno(x) ((x) ? "yes" : "no") |
8cc75c9a | 321 | u16 ictl = bfin_read_RTC_ICTL(); |
5438de44 | 322 | dev_dbg_stamp(dev); |
64061160 MF |
323 | seq_printf(seq, |
324 | "alarm_IRQ\t: %s\n" | |
325 | "wkalarm_IRQ\t: %s\n" | |
26cb8bb2 | 326 | "seconds_IRQ\t: %s\n", |
64061160 MF |
327 | yesno(ictl & RTC_ISTAT_ALARM), |
328 | yesno(ictl & RTC_ISTAT_ALARM_DAY), | |
26cb8bb2 | 329 | yesno(ictl & RTC_ISTAT_SEC)); |
8cc75c9a | 330 | return 0; |
64061160 | 331 | #undef yesno |
8cc75c9a WB |
332 | } |
333 | ||
8cc75c9a | 334 | static struct rtc_class_ops bfin_rtc_ops = { |
8cc75c9a WB |
335 | .read_time = bfin_rtc_read_time, |
336 | .set_time = bfin_rtc_set_time, | |
337 | .read_alarm = bfin_rtc_read_alarm, | |
338 | .set_alarm = bfin_rtc_set_alarm, | |
339 | .proc = bfin_rtc_proc, | |
16380c15 | 340 | .alarm_irq_enable = bfin_rtc_alarm_irq_enable, |
8cc75c9a WB |
341 | }; |
342 | ||
343 | static int __devinit bfin_rtc_probe(struct platform_device *pdev) | |
344 | { | |
345 | struct bfin_rtc *rtc; | |
fe2e1cf8 | 346 | struct device *dev = &pdev->dev; |
8cc75c9a | 347 | int ret = 0; |
9980060b | 348 | unsigned long timeout = jiffies + HZ; |
8cc75c9a | 349 | |
fe2e1cf8 | 350 | dev_dbg_stamp(dev); |
8cc75c9a | 351 | |
fe2e1cf8 | 352 | /* Allocate memory for our RTC struct */ |
8cc75c9a WB |
353 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); |
354 | if (unlikely(!rtc)) | |
355 | return -ENOMEM; | |
fe2e1cf8 | 356 | platform_set_drvdata(pdev, rtc); |
8c9166f7 | 357 | device_init_wakeup(dev, 1); |
8cc75c9a | 358 | |
9980060b MF |
359 | /* Register our RTC with the RTC framework */ |
360 | rtc->rtc_dev = rtc_device_register(pdev->name, dev, &bfin_rtc_ops, | |
361 | THIS_MODULE); | |
362 | if (unlikely(IS_ERR(rtc->rtc_dev))) { | |
363 | ret = PTR_ERR(rtc->rtc_dev); | |
364 | goto err; | |
365 | } | |
366 | ||
fe2e1cf8 | 367 | /* Grab the IRQ and init the hardware */ |
6bff5fb8 | 368 | ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, 0, pdev->name, dev); |
fe2e1cf8 | 369 | if (unlikely(ret)) |
9980060b | 370 | goto err_reg; |
d0fd9378 MF |
371 | /* sometimes the bootloader touched things, but the write complete was not |
372 | * enabled, so let's just do a quick timeout here since the IRQ will not fire ... | |
373 | */ | |
d0fd9378 MF |
374 | while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) |
375 | if (time_after(jiffies, timeout)) | |
376 | break; | |
fe2e1cf8 | 377 | bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE); |
26cb8bb2 | 378 | bfin_write_RTC_SWCNT(0); |
8cc75c9a | 379 | |
8cc75c9a WB |
380 | return 0; |
381 | ||
9980060b MF |
382 | err_reg: |
383 | rtc_device_unregister(rtc->rtc_dev); | |
384 | err: | |
8cc75c9a WB |
385 | kfree(rtc); |
386 | return ret; | |
387 | } | |
388 | ||
389 | static int __devexit bfin_rtc_remove(struct platform_device *pdev) | |
390 | { | |
391 | struct bfin_rtc *rtc = platform_get_drvdata(pdev); | |
fe2e1cf8 | 392 | struct device *dev = &pdev->dev; |
8cc75c9a | 393 | |
fe2e1cf8 MF |
394 | bfin_rtc_reset(dev, 0); |
395 | free_irq(IRQ_RTC, dev); | |
8cc75c9a WB |
396 | rtc_device_unregister(rtc->rtc_dev); |
397 | platform_set_drvdata(pdev, NULL); | |
398 | kfree(rtc); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
5aeb776d SZ |
403 | #ifdef CONFIG_PM |
404 | static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state) | |
405 | { | |
d7c7ef90 MF |
406 | struct device *dev = &pdev->dev; |
407 | ||
408 | dev_dbg_stamp(dev); | |
409 | ||
410 | if (device_may_wakeup(dev)) { | |
813006f4 | 411 | enable_irq_wake(IRQ_RTC); |
d7c7ef90 | 412 | bfin_rtc_sync_pending(dev); |
140fab14 | 413 | } else |
110b7e96 | 414 | bfin_rtc_int_clear(0); |
813006f4 | 415 | |
5aeb776d SZ |
416 | return 0; |
417 | } | |
418 | ||
419 | static int bfin_rtc_resume(struct platform_device *pdev) | |
420 | { | |
d7c7ef90 MF |
421 | struct device *dev = &pdev->dev; |
422 | ||
423 | dev_dbg_stamp(dev); | |
424 | ||
425 | if (device_may_wakeup(dev)) | |
813006f4 | 426 | disable_irq_wake(IRQ_RTC); |
b6de8606 MF |
427 | |
428 | /* | |
429 | * Since only some of the RTC bits are maintained externally in the | |
430 | * Vbat domain, we need to wait for the RTC MMRs to be synced into | |
431 | * the core after waking up. This happens every RTC 1HZ. Once that | |
432 | * has happened, we can go ahead and re-enable the important write | |
433 | * complete interrupt event. | |
434 | */ | |
435 | while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC)) | |
436 | continue; | |
437 | bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE); | |
813006f4 | 438 | |
5aeb776d SZ |
439 | return 0; |
440 | } | |
813006f4 MF |
441 | #else |
442 | # define bfin_rtc_suspend NULL | |
443 | # define bfin_rtc_resume NULL | |
5aeb776d SZ |
444 | #endif |
445 | ||
8cc75c9a WB |
446 | static struct platform_driver bfin_rtc_driver = { |
447 | .driver = { | |
448 | .name = "rtc-bfin", | |
449 | .owner = THIS_MODULE, | |
450 | }, | |
451 | .probe = bfin_rtc_probe, | |
452 | .remove = __devexit_p(bfin_rtc_remove), | |
5aeb776d SZ |
453 | .suspend = bfin_rtc_suspend, |
454 | .resume = bfin_rtc_resume, | |
8cc75c9a WB |
455 | }; |
456 | ||
457 | static int __init bfin_rtc_init(void) | |
458 | { | |
8cc75c9a WB |
459 | return platform_driver_register(&bfin_rtc_driver); |
460 | } | |
461 | ||
462 | static void __exit bfin_rtc_exit(void) | |
463 | { | |
464 | platform_driver_unregister(&bfin_rtc_driver); | |
465 | } | |
466 | ||
467 | module_init(bfin_rtc_init); | |
468 | module_exit(bfin_rtc_exit); | |
469 | ||
470 | MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver"); | |
471 | MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>"); | |
472 | MODULE_LICENSE("GPL"); | |
ad28a07b | 473 | MODULE_ALIAS("platform:rtc-bfin"); |