]>
Commit | Line | Data |
---|---|---|
7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
5d2a5037 | 38 | #include <linux/log2.h> |
2fb08e6c | 39 | #include <linux/pm.h> |
3bcbaf6e SAS |
40 | #include <linux/of.h> |
41 | #include <linux/of_platform.h> | |
7be2c7c9 DB |
42 | |
43 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | |
44 | #include <asm-generic/rtc.h> | |
45 | ||
7be2c7c9 DB |
46 | struct cmos_rtc { |
47 | struct rtc_device *rtc; | |
48 | struct device *dev; | |
49 | int irq; | |
50 | struct resource *iomem; | |
51 | ||
87ac84f4 DB |
52 | void (*wake_on)(struct device *); |
53 | void (*wake_off)(struct device *); | |
54 | ||
55 | u8 enabled_wake; | |
7be2c7c9 DB |
56 | u8 suspend_ctrl; |
57 | ||
58 | /* newer hardware extends the original register set */ | |
59 | u8 day_alrm; | |
60 | u8 mon_alrm; | |
61 | u8 century; | |
62 | }; | |
63 | ||
64 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
2fac6674 | 65 | #define is_valid_irq(n) ((n) > 0) |
7be2c7c9 DB |
66 | |
67 | static const char driver_name[] = "rtc_cmos"; | |
68 | ||
bcd9b89c DB |
69 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
70 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
71 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
72 | */ | |
73 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
74 | ||
75 | static inline int is_intr(u8 rtc_intr) | |
76 | { | |
77 | if (!(rtc_intr & RTC_IRQF)) | |
78 | return 0; | |
79 | return rtc_intr & RTC_IRQMASK; | |
80 | } | |
81 | ||
7be2c7c9 DB |
82 | /*----------------------------------------------------------------*/ |
83 | ||
35d3fdd5 DB |
84 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because |
85 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | |
86 | * used in a broken "legacy replacement" mode. The breakage includes | |
87 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | |
88 | * other (better) use. | |
89 | * | |
90 | * When that broken mode is in use, platform glue provides a partial | |
91 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | |
92 | * want to use HPET for anything except those IRQs though... | |
93 | */ | |
94 | #ifdef CONFIG_HPET_EMULATE_RTC | |
95 | #include <asm/hpet.h> | |
96 | #else | |
97 | ||
98 | static inline int is_hpet_enabled(void) | |
99 | { | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | |
104 | { | |
105 | return 0; | |
106 | } | |
107 | ||
108 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | |
109 | { | |
110 | return 0; | |
111 | } | |
112 | ||
113 | static inline int | |
114 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
115 | { | |
116 | return 0; | |
117 | } | |
118 | ||
119 | static inline int hpet_set_periodic_freq(unsigned long freq) | |
120 | { | |
121 | return 0; | |
122 | } | |
123 | ||
124 | static inline int hpet_rtc_dropped_irq(void) | |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static inline int hpet_rtc_timer_init(void) | |
130 | { | |
131 | return 0; | |
132 | } | |
133 | ||
134 | extern irq_handler_t hpet_rtc_interrupt; | |
135 | ||
136 | static inline int hpet_register_irq_handler(irq_handler_t handler) | |
137 | { | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | |
142 | { | |
143 | return 0; | |
144 | } | |
145 | ||
146 | #endif | |
147 | ||
148 | /*----------------------------------------------------------------*/ | |
149 | ||
c8fc40cd DB |
150 | #ifdef RTC_PORT |
151 | ||
152 | /* Most newer x86 systems have two register banks, the first used | |
153 | * for RTC and NVRAM and the second only for NVRAM. Caller must | |
154 | * own rtc_lock ... and we won't worry about access during NMI. | |
155 | */ | |
156 | #define can_bank2 true | |
157 | ||
158 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
159 | { | |
160 | outb(addr, RTC_PORT(2)); | |
161 | return inb(RTC_PORT(3)); | |
162 | } | |
163 | ||
164 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
165 | { | |
166 | outb(addr, RTC_PORT(2)); | |
b43c1ea4 | 167 | outb(val, RTC_PORT(3)); |
c8fc40cd DB |
168 | } |
169 | ||
170 | #else | |
171 | ||
172 | #define can_bank2 false | |
173 | ||
174 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
175 | { | |
176 | return 0; | |
177 | } | |
178 | ||
179 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
180 | { | |
181 | } | |
182 | ||
183 | #endif | |
184 | ||
185 | /*----------------------------------------------------------------*/ | |
186 | ||
7be2c7c9 DB |
187 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
188 | { | |
189 | /* REVISIT: if the clock has a "century" register, use | |
190 | * that instead of the heuristic in get_rtc_time(). | |
191 | * That'll make Y3K compatility (year > 2070) easy! | |
192 | */ | |
193 | get_rtc_time(t); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
198 | { | |
199 | /* REVISIT: set the "century" register if available | |
200 | * | |
201 | * NOTE: this ignores the issue whereby updating the seconds | |
202 | * takes effect exactly 500ms after we write the register. | |
203 | * (Also queueing and other delays before we get this far.) | |
204 | */ | |
205 | return set_rtc_time(t); | |
206 | } | |
207 | ||
208 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
209 | { | |
210 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
211 | unsigned char rtc_control; | |
212 | ||
213 | if (!is_valid_irq(cmos->irq)) | |
214 | return -EIO; | |
215 | ||
216 | /* Basic alarms only support hour, minute, and seconds fields. | |
217 | * Some also support day and month, for alarms up to a year in | |
218 | * the future. | |
219 | */ | |
220 | t->time.tm_mday = -1; | |
221 | t->time.tm_mon = -1; | |
222 | ||
223 | spin_lock_irq(&rtc_lock); | |
224 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
225 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
226 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
227 | ||
228 | if (cmos->day_alrm) { | |
615bb29c ML |
229 | /* ignore upper bits on readback per ACPI spec */ |
230 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
231 | if (!t->time.tm_mday) |
232 | t->time.tm_mday = -1; | |
233 | ||
234 | if (cmos->mon_alrm) { | |
235 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
236 | if (!t->time.tm_mon) | |
237 | t->time.tm_mon = -1; | |
238 | } | |
239 | } | |
240 | ||
241 | rtc_control = CMOS_READ(RTC_CONTROL); | |
242 | spin_unlock_irq(&rtc_lock); | |
243 | ||
3804a89b AP |
244 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { |
245 | if (((unsigned)t->time.tm_sec) < 0x60) | |
246 | t->time.tm_sec = bcd2bin(t->time.tm_sec); | |
7be2c7c9 | 247 | else |
3804a89b AP |
248 | t->time.tm_sec = -1; |
249 | if (((unsigned)t->time.tm_min) < 0x60) | |
250 | t->time.tm_min = bcd2bin(t->time.tm_min); | |
251 | else | |
252 | t->time.tm_min = -1; | |
253 | if (((unsigned)t->time.tm_hour) < 0x24) | |
254 | t->time.tm_hour = bcd2bin(t->time.tm_hour); | |
255 | else | |
256 | t->time.tm_hour = -1; | |
257 | ||
258 | if (cmos->day_alrm) { | |
259 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
260 | t->time.tm_mday = bcd2bin(t->time.tm_mday); | |
7be2c7c9 | 261 | else |
3804a89b AP |
262 | t->time.tm_mday = -1; |
263 | ||
264 | if (cmos->mon_alrm) { | |
265 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
266 | t->time.tm_mon = bcd2bin(t->time.tm_mon)-1; | |
267 | else | |
268 | t->time.tm_mon = -1; | |
269 | } | |
7be2c7c9 DB |
270 | } |
271 | } | |
272 | t->time.tm_year = -1; | |
273 | ||
274 | t->enabled = !!(rtc_control & RTC_AIE); | |
275 | t->pending = 0; | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
7e2a31da DB |
280 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) |
281 | { | |
282 | unsigned char rtc_intr; | |
283 | ||
284 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
285 | * allegedly some older rtcs need that to handle irqs properly | |
286 | */ | |
287 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
288 | ||
289 | if (is_hpet_enabled()) | |
290 | return; | |
291 | ||
292 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
293 | if (is_intr(rtc_intr)) | |
294 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
295 | } | |
296 | ||
297 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | |
298 | { | |
299 | unsigned char rtc_control; | |
300 | ||
301 | /* flush any pending IRQ status, notably for update irqs, | |
302 | * before we enable new IRQs | |
303 | */ | |
304 | rtc_control = CMOS_READ(RTC_CONTROL); | |
305 | cmos_checkintr(cmos, rtc_control); | |
306 | ||
307 | rtc_control |= mask; | |
308 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
309 | hpet_set_rtc_irq_bit(mask); | |
310 | ||
311 | cmos_checkintr(cmos, rtc_control); | |
312 | } | |
313 | ||
314 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | |
315 | { | |
316 | unsigned char rtc_control; | |
317 | ||
318 | rtc_control = CMOS_READ(RTC_CONTROL); | |
319 | rtc_control &= ~mask; | |
320 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
321 | hpet_mask_rtc_irq_bit(mask); | |
322 | ||
323 | cmos_checkintr(cmos, rtc_control); | |
324 | } | |
325 | ||
7be2c7c9 DB |
326 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
327 | { | |
328 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
5e8599d2 | 329 | unsigned char mon, mday, hrs, min, sec, rtc_control; |
7be2c7c9 DB |
330 | |
331 | if (!is_valid_irq(cmos->irq)) | |
332 | return -EIO; | |
333 | ||
2b653e06 | 334 | mon = t->time.tm_mon + 1; |
7be2c7c9 | 335 | mday = t->time.tm_mday; |
7be2c7c9 | 336 | hrs = t->time.tm_hour; |
7be2c7c9 | 337 | min = t->time.tm_min; |
7be2c7c9 | 338 | sec = t->time.tm_sec; |
3804a89b AP |
339 | |
340 | rtc_control = CMOS_READ(RTC_CONTROL); | |
341 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { | |
342 | /* Writing 0xff means "don't care" or "match all". */ | |
343 | mon = (mon <= 12) ? bin2bcd(mon) : 0xff; | |
344 | mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; | |
345 | hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; | |
346 | min = (min < 60) ? bin2bcd(min) : 0xff; | |
347 | sec = (sec < 60) ? bin2bcd(sec) : 0xff; | |
348 | } | |
7be2c7c9 DB |
349 | |
350 | spin_lock_irq(&rtc_lock); | |
351 | ||
352 | /* next rtc irq must not be from previous alarm setting */ | |
7e2a31da | 353 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
354 | |
355 | /* update alarm */ | |
356 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
357 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
358 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
359 | ||
360 | /* the system may support an "enhanced" alarm */ | |
361 | if (cmos->day_alrm) { | |
362 | CMOS_WRITE(mday, cmos->day_alrm); | |
363 | if (cmos->mon_alrm) | |
364 | CMOS_WRITE(mon, cmos->mon_alrm); | |
365 | } | |
366 | ||
35d3fdd5 DB |
367 | /* FIXME the HPET alarm glue currently ignores day_alrm |
368 | * and mon_alrm ... | |
369 | */ | |
370 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | |
371 | ||
7e2a31da DB |
372 | if (t->enabled) |
373 | cmos_irq_enable(cmos, RTC_AIE); | |
7be2c7c9 DB |
374 | |
375 | spin_unlock_irq(&rtc_lock); | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
a8462ef6 | 380 | static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled) |
7be2c7c9 DB |
381 | { |
382 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
7be2c7c9 DB |
383 | unsigned long flags; |
384 | ||
a8462ef6 HRK |
385 | if (!is_valid_irq(cmos->irq)) |
386 | return -EINVAL; | |
7be2c7c9 DB |
387 | |
388 | spin_lock_irqsave(&rtc_lock, flags); | |
a8462ef6 HRK |
389 | |
390 | if (enabled) | |
7e2a31da | 391 | cmos_irq_enable(cmos, RTC_AIE); |
a8462ef6 HRK |
392 | else |
393 | cmos_irq_disable(cmos, RTC_AIE); | |
394 | ||
7be2c7c9 DB |
395 | spin_unlock_irqrestore(&rtc_lock, flags); |
396 | return 0; | |
397 | } | |
398 | ||
7be2c7c9 DB |
399 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) |
400 | ||
401 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
402 | { | |
403 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
404 | unsigned char rtc_control, valid; | |
405 | ||
406 | spin_lock_irq(&rtc_lock); | |
407 | rtc_control = CMOS_READ(RTC_CONTROL); | |
408 | valid = CMOS_READ(RTC_VALID); | |
409 | spin_unlock_irq(&rtc_lock); | |
410 | ||
411 | /* NOTE: at least ICH6 reports battery status using a different | |
412 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
413 | */ | |
414 | return seq_printf(seq, | |
415 | "periodic_IRQ\t: %s\n" | |
416 | "update_IRQ\t: %s\n" | |
c8626a1d | 417 | "HPET_emulated\t: %s\n" |
7be2c7c9 | 418 | // "square_wave\t: %s\n" |
3804a89b | 419 | "BCD\t\t: %s\n" |
7be2c7c9 DB |
420 | "DST_enable\t: %s\n" |
421 | "periodic_freq\t: %d\n" | |
422 | "batt_status\t: %s\n", | |
423 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
424 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 425 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 | 426 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
3804a89b | 427 | (rtc_control & RTC_DM_BINARY) ? "no" : "yes", |
7be2c7c9 DB |
428 | (rtc_control & RTC_DST_EN) ? "yes" : "no", |
429 | cmos->rtc->irq_freq, | |
430 | (valid & RTC_VRT) ? "okay" : "dead"); | |
431 | } | |
432 | ||
433 | #else | |
434 | #define cmos_procfs NULL | |
435 | #endif | |
436 | ||
437 | static const struct rtc_class_ops cmos_rtc_ops = { | |
a8462ef6 HRK |
438 | .read_time = cmos_read_time, |
439 | .set_time = cmos_set_time, | |
440 | .read_alarm = cmos_read_alarm, | |
441 | .set_alarm = cmos_set_alarm, | |
442 | .proc = cmos_procfs, | |
a8462ef6 | 443 | .alarm_irq_enable = cmos_alarm_irq_enable, |
7be2c7c9 DB |
444 | }; |
445 | ||
446 | /*----------------------------------------------------------------*/ | |
447 | ||
e07e232c DB |
448 | /* |
449 | * All these chips have at least 64 bytes of address space, shared by | |
450 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
451 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
452 | */ | |
453 | ||
454 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
455 | ||
456 | static ssize_t | |
2c3c8bea CW |
457 | cmos_nvram_read(struct file *filp, struct kobject *kobj, |
458 | struct bin_attribute *attr, | |
e07e232c DB |
459 | char *buf, loff_t off, size_t count) |
460 | { | |
461 | int retval; | |
462 | ||
463 | if (unlikely(off >= attr->size)) | |
464 | return 0; | |
c8fc40cd DB |
465 | if (unlikely(off < 0)) |
466 | return -EINVAL; | |
e07e232c DB |
467 | if ((off + count) > attr->size) |
468 | count = attr->size - off; | |
469 | ||
c8fc40cd | 470 | off += NVRAM_OFFSET; |
e07e232c | 471 | spin_lock_irq(&rtc_lock); |
c8fc40cd DB |
472 | for (retval = 0; count; count--, off++, retval++) { |
473 | if (off < 128) | |
474 | *buf++ = CMOS_READ(off); | |
475 | else if (can_bank2) | |
476 | *buf++ = cmos_read_bank2(off); | |
477 | else | |
478 | break; | |
479 | } | |
e07e232c DB |
480 | spin_unlock_irq(&rtc_lock); |
481 | ||
482 | return retval; | |
483 | } | |
484 | ||
485 | static ssize_t | |
2c3c8bea CW |
486 | cmos_nvram_write(struct file *filp, struct kobject *kobj, |
487 | struct bin_attribute *attr, | |
e07e232c DB |
488 | char *buf, loff_t off, size_t count) |
489 | { | |
490 | struct cmos_rtc *cmos; | |
491 | int retval; | |
492 | ||
493 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
494 | if (unlikely(off >= attr->size)) | |
495 | return -EFBIG; | |
c8fc40cd DB |
496 | if (unlikely(off < 0)) |
497 | return -EINVAL; | |
e07e232c DB |
498 | if ((off + count) > attr->size) |
499 | count = attr->size - off; | |
500 | ||
501 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
502 | * checksum on part of the NVRAM data. That's currently ignored | |
503 | * here. If userspace is smart enough to know what fields of | |
504 | * NVRAM to update, updating checksums is also part of its job. | |
505 | */ | |
c8fc40cd | 506 | off += NVRAM_OFFSET; |
e07e232c | 507 | spin_lock_irq(&rtc_lock); |
c8fc40cd | 508 | for (retval = 0; count; count--, off++, retval++) { |
e07e232c DB |
509 | /* don't trash RTC registers */ |
510 | if (off == cmos->day_alrm | |
511 | || off == cmos->mon_alrm | |
512 | || off == cmos->century) | |
513 | buf++; | |
c8fc40cd | 514 | else if (off < 128) |
e07e232c | 515 | CMOS_WRITE(*buf++, off); |
c8fc40cd DB |
516 | else if (can_bank2) |
517 | cmos_write_bank2(*buf++, off); | |
518 | else | |
519 | break; | |
e07e232c DB |
520 | } |
521 | spin_unlock_irq(&rtc_lock); | |
522 | ||
523 | return retval; | |
524 | } | |
525 | ||
526 | static struct bin_attribute nvram = { | |
527 | .attr = { | |
528 | .name = "nvram", | |
529 | .mode = S_IRUGO | S_IWUSR, | |
e07e232c DB |
530 | }, |
531 | ||
532 | .read = cmos_nvram_read, | |
533 | .write = cmos_nvram_write, | |
534 | /* size gets set up later */ | |
535 | }; | |
536 | ||
537 | /*----------------------------------------------------------------*/ | |
538 | ||
7be2c7c9 DB |
539 | static struct cmos_rtc cmos_rtc; |
540 | ||
541 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
542 | { | |
543 | u8 irqstat; | |
8a0bdfd7 | 544 | u8 rtc_control; |
7be2c7c9 DB |
545 | |
546 | spin_lock(&rtc_lock); | |
35d3fdd5 DB |
547 | |
548 | /* When the HPET interrupt handler calls us, the interrupt | |
549 | * status is passed as arg1 instead of the irq number. But | |
550 | * always clear irq status, even when HPET is in the way. | |
551 | * | |
552 | * Note that HPET and RTC are almost certainly out of phase, | |
553 | * giving different IRQ status ... | |
9d8af78b | 554 | */ |
35d3fdd5 DB |
555 | irqstat = CMOS_READ(RTC_INTR_FLAGS); |
556 | rtc_control = CMOS_READ(RTC_CONTROL); | |
9d8af78b BW |
557 | if (is_hpet_enabled()) |
558 | irqstat = (unsigned long)irq & 0xF0; | |
998a0605 DB |
559 | |
560 | /* If we were suspended, RTC_CONTROL may not be accurate since the | |
561 | * bios may have cleared it. | |
562 | */ | |
563 | if (!cmos_rtc.suspend_ctrl) | |
564 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
565 | else | |
566 | irqstat &= (cmos_rtc.suspend_ctrl & RTC_IRQMASK) | RTC_IRQF; | |
8a0bdfd7 DB |
567 | |
568 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
569 | * Similar code may be needed in system wakeup paths, in case the | |
570 | * alarm woke the system. | |
571 | */ | |
572 | if (irqstat & RTC_AIE) { | |
998a0605 | 573 | cmos_rtc.suspend_ctrl &= ~RTC_AIE; |
8a0bdfd7 DB |
574 | rtc_control &= ~RTC_AIE; |
575 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
35d3fdd5 | 576 | hpet_mask_rtc_irq_bit(RTC_AIE); |
8a0bdfd7 DB |
577 | CMOS_READ(RTC_INTR_FLAGS); |
578 | } | |
7be2c7c9 DB |
579 | spin_unlock(&rtc_lock); |
580 | ||
bcd9b89c | 581 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
582 | rtc_update_irq(p, 1, irqstat); |
583 | return IRQ_HANDLED; | |
584 | } else | |
585 | return IRQ_NONE; | |
586 | } | |
587 | ||
41ac8df9 | 588 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
589 | #define INITSECTION |
590 | ||
591 | #else | |
7be2c7c9 DB |
592 | #define INITSECTION __init |
593 | #endif | |
594 | ||
595 | static int INITSECTION | |
596 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
597 | { | |
598 | struct cmos_rtc_board_info *info = dev->platform_data; | |
599 | int retval = 0; | |
600 | unsigned char rtc_control; | |
e07e232c | 601 | unsigned address_space; |
7be2c7c9 DB |
602 | |
603 | /* there can be only one ... */ | |
604 | if (cmos_rtc.dev) | |
605 | return -EBUSY; | |
606 | ||
607 | if (!ports) | |
608 | return -ENODEV; | |
609 | ||
05440dfc DB |
610 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
611 | * | |
612 | * REVISIT non-x86 systems may instead use memory space resources | |
613 | * (needing ioremap etc), not i/o space resources like this ... | |
614 | */ | |
615 | ports = request_region(ports->start, | |
28f65c11 | 616 | resource_size(ports), |
05440dfc DB |
617 | driver_name); |
618 | if (!ports) { | |
619 | dev_dbg(dev, "i/o registers already in use\n"); | |
620 | return -EBUSY; | |
621 | } | |
622 | ||
7be2c7c9 DB |
623 | cmos_rtc.irq = rtc_irq; |
624 | cmos_rtc.iomem = ports; | |
625 | ||
e07e232c DB |
626 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
627 | * driver did, but don't reject unknown configs. Old hardware | |
c8fc40cd DB |
628 | * won't address 128 bytes. Newer chips have multiple banks, |
629 | * though they may not be listed in one I/O resource. | |
e07e232c DB |
630 | */ |
631 | #if defined(CONFIG_ATARI) | |
632 | address_space = 64; | |
95abd0df | 633 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ |
8cb7c71b SK |
634 | || defined(__sparc__) || defined(__mips__) \ |
635 | || defined(__powerpc__) | |
e07e232c DB |
636 | address_space = 128; |
637 | #else | |
638 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
639 | address_space = 128; | |
640 | #endif | |
c8fc40cd DB |
641 | if (can_bank2 && ports->end > (ports->start + 1)) |
642 | address_space = 256; | |
e07e232c | 643 | |
87ac84f4 DB |
644 | /* For ACPI systems extension info comes from the FADT. On others, |
645 | * board specific setup provides it as appropriate. Systems where | |
646 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
647 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
648 | * |
649 | * Note that ACPI doesn't preclude putting these registers into | |
650 | * "extended" areas of the chip, including some that we won't yet | |
651 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
652 | */ |
653 | if (info) { | |
e07e232c DB |
654 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
655 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
656 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
657 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
658 | if (info->rtc_century && info->rtc_century < 128) | |
659 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
660 | |
661 | if (info->wake_on && info->wake_off) { | |
662 | cmos_rtc.wake_on = info->wake_on; | |
663 | cmos_rtc.wake_off = info->wake_off; | |
664 | } | |
7be2c7c9 DB |
665 | } |
666 | ||
6ba8bcd4 DC |
667 | cmos_rtc.dev = dev; |
668 | dev_set_drvdata(dev, &cmos_rtc); | |
669 | ||
7be2c7c9 DB |
670 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, |
671 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
672 | if (IS_ERR(cmos_rtc.rtc)) { |
673 | retval = PTR_ERR(cmos_rtc.rtc); | |
674 | goto cleanup0; | |
675 | } | |
7be2c7c9 | 676 | |
d4afc76c | 677 | rename_region(ports, dev_name(&cmos_rtc.rtc->dev)); |
7be2c7c9 DB |
678 | |
679 | spin_lock_irq(&rtc_lock); | |
680 | ||
681 | /* force periodic irq to CMOS reset default of 1024Hz; | |
682 | * | |
683 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
684 | * doesn't use 32KHz here ... for portability we might need to | |
685 | * do something about other clock frequencies. | |
686 | */ | |
7be2c7c9 | 687 | cmos_rtc.rtc->irq_freq = 1024; |
35d3fdd5 DB |
688 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); |
689 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 | 690 | |
7e2a31da DB |
691 | /* disable irqs */ |
692 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | |
35d3fdd5 | 693 | |
7e2a31da | 694 | rtc_control = CMOS_READ(RTC_CONTROL); |
7be2c7c9 DB |
695 | |
696 | spin_unlock_irq(&rtc_lock); | |
697 | ||
3804a89b | 698 | /* FIXME: |
7be2c7c9 DB |
699 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. |
700 | */ | |
5e8599d2 | 701 | if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { |
3804a89b | 702 | dev_warn(dev, "only 24-hr supported\n"); |
7be2c7c9 DB |
703 | retval = -ENXIO; |
704 | goto cleanup1; | |
705 | } | |
706 | ||
9d8af78b BW |
707 | if (is_valid_irq(rtc_irq)) { |
708 | irq_handler_t rtc_cmos_int_handler; | |
709 | ||
710 | if (is_hpet_enabled()) { | |
711 | int err; | |
712 | ||
713 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
714 | err = hpet_register_irq_handler(cmos_interrupt); | |
715 | if (err != 0) { | |
ee443357 | 716 | dev_warn(dev, "hpet_register_irq_handler " |
9d8af78b BW |
717 | " failed in rtc_init()."); |
718 | goto cleanup1; | |
719 | } | |
720 | } else | |
721 | rtc_cmos_int_handler = cmos_interrupt; | |
722 | ||
723 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
2f6e5f94 | 724 | 0, dev_name(&cmos_rtc.rtc->dev), |
ab6a2d70 | 725 | cmos_rtc.rtc); |
9d8af78b BW |
726 | if (retval < 0) { |
727 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
728 | goto cleanup1; | |
729 | } | |
7be2c7c9 | 730 | } |
9d8af78b | 731 | hpet_rtc_timer_init(); |
7be2c7c9 | 732 | |
e07e232c DB |
733 | /* export at least the first block of NVRAM */ |
734 | nvram.size = address_space - NVRAM_OFFSET; | |
735 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
736 | if (retval < 0) { | |
737 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
738 | goto cleanup2; | |
739 | } | |
7be2c7c9 | 740 | |
ee443357 | 741 | dev_info(dev, "%s%s, %zd bytes nvram%s\n", |
6d029b64 KH |
742 | !is_valid_irq(rtc_irq) ? "no alarms" : |
743 | cmos_rtc.mon_alrm ? "alarms up to one year" : | |
744 | cmos_rtc.day_alrm ? "alarms up to one month" : | |
745 | "alarms up to one day", | |
746 | cmos_rtc.century ? ", y3k" : "", | |
747 | nvram.size, | |
748 | is_hpet_enabled() ? ", hpet irqs" : ""); | |
7be2c7c9 DB |
749 | |
750 | return 0; | |
751 | ||
e07e232c DB |
752 | cleanup2: |
753 | if (is_valid_irq(rtc_irq)) | |
754 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 755 | cleanup1: |
05440dfc | 756 | cmos_rtc.dev = NULL; |
7be2c7c9 | 757 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc | 758 | cleanup0: |
28f65c11 | 759 | release_region(ports->start, resource_size(ports)); |
7be2c7c9 DB |
760 | return retval; |
761 | } | |
762 | ||
763 | static void cmos_do_shutdown(void) | |
764 | { | |
7be2c7c9 | 765 | spin_lock_irq(&rtc_lock); |
7e2a31da | 766 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); |
7be2c7c9 DB |
767 | spin_unlock_irq(&rtc_lock); |
768 | } | |
769 | ||
770 | static void __exit cmos_do_remove(struct device *dev) | |
771 | { | |
772 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 773 | struct resource *ports; |
7be2c7c9 DB |
774 | |
775 | cmos_do_shutdown(); | |
776 | ||
e07e232c DB |
777 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
778 | ||
9d8af78b | 779 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 780 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
781 | hpet_unregister_irq_handler(cmos_interrupt); |
782 | } | |
7be2c7c9 | 783 | |
05440dfc DB |
784 | rtc_device_unregister(cmos->rtc); |
785 | cmos->rtc = NULL; | |
7be2c7c9 | 786 | |
05440dfc | 787 | ports = cmos->iomem; |
28f65c11 | 788 | release_region(ports->start, resource_size(ports)); |
05440dfc DB |
789 | cmos->iomem = NULL; |
790 | ||
791 | cmos->dev = NULL; | |
7be2c7c9 DB |
792 | dev_set_drvdata(dev, NULL); |
793 | } | |
794 | ||
795 | #ifdef CONFIG_PM | |
796 | ||
2fb08e6c | 797 | static int cmos_suspend(struct device *dev) |
7be2c7c9 DB |
798 | { |
799 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
bcd9b89c | 800 | unsigned char tmp; |
7be2c7c9 DB |
801 | |
802 | /* only the alarm might be a wakeup event source */ | |
803 | spin_lock_irq(&rtc_lock); | |
804 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
805 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
35d3fdd5 | 806 | unsigned char mask; |
bcd9b89c | 807 | |
74c4633d | 808 | if (device_may_wakeup(dev)) |
35d3fdd5 | 809 | mask = RTC_IRQMASK & ~RTC_AIE; |
7be2c7c9 | 810 | else |
35d3fdd5 DB |
811 | mask = RTC_IRQMASK; |
812 | tmp &= ~mask; | |
7be2c7c9 | 813 | CMOS_WRITE(tmp, RTC_CONTROL); |
e005715e | 814 | hpet_mask_rtc_irq_bit(mask); |
35d3fdd5 | 815 | |
7e2a31da | 816 | cmos_checkintr(cmos, tmp); |
bcd9b89c | 817 | } |
7be2c7c9 DB |
818 | spin_unlock_irq(&rtc_lock); |
819 | ||
87ac84f4 DB |
820 | if (tmp & RTC_AIE) { |
821 | cmos->enabled_wake = 1; | |
822 | if (cmos->wake_on) | |
823 | cmos->wake_on(dev); | |
824 | else | |
825 | enable_irq_wake(cmos->irq); | |
826 | } | |
7be2c7c9 | 827 | |
ee443357 | 828 | dev_dbg(dev, "suspend%s, ctrl %02x\n", |
7be2c7c9 DB |
829 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
830 | tmp); | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
74c4633d RW |
835 | /* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even |
836 | * after a detour through G3 "mechanical off", although the ACPI spec | |
837 | * says wakeup should only work from G1/S4 "hibernate". To most users, | |
838 | * distinctions between S4 and S5 are pointless. So when the hardware | |
839 | * allows, don't draw that distinction. | |
840 | */ | |
841 | static inline int cmos_poweroff(struct device *dev) | |
842 | { | |
2fb08e6c | 843 | return cmos_suspend(dev); |
74c4633d RW |
844 | } |
845 | ||
7be2c7c9 DB |
846 | static int cmos_resume(struct device *dev) |
847 | { | |
848 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
998a0605 DB |
849 | unsigned char tmp; |
850 | ||
851 | if (cmos->enabled_wake) { | |
852 | if (cmos->wake_off) | |
853 | cmos->wake_off(dev); | |
854 | else | |
855 | disable_irq_wake(cmos->irq); | |
856 | cmos->enabled_wake = 0; | |
857 | } | |
7be2c7c9 | 858 | |
998a0605 DB |
859 | spin_lock_irq(&rtc_lock); |
860 | tmp = cmos->suspend_ctrl; | |
861 | cmos->suspend_ctrl = 0; | |
7be2c7c9 | 862 | /* re-enable any irqs previously active */ |
35d3fdd5 DB |
863 | if (tmp & RTC_IRQMASK) { |
864 | unsigned char mask; | |
7be2c7c9 | 865 | |
ebf8d6c8 DB |
866 | if (device_may_wakeup(dev)) |
867 | hpet_rtc_timer_init(); | |
868 | ||
35d3fdd5 DB |
869 | do { |
870 | CMOS_WRITE(tmp, RTC_CONTROL); | |
871 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); | |
872 | ||
873 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
874 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | |
7e2a31da | 875 | if (!is_hpet_enabled() || !is_intr(mask)) |
35d3fdd5 DB |
876 | break; |
877 | ||
878 | /* force one-shot behavior if HPET blocked | |
879 | * the wake alarm's irq | |
880 | */ | |
881 | rtc_update_irq(cmos->rtc, 1, mask); | |
882 | tmp &= ~RTC_AIE; | |
883 | hpet_mask_rtc_irq_bit(RTC_AIE); | |
884 | } while (mask & RTC_AIE); | |
7be2c7c9 | 885 | } |
998a0605 | 886 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 | 887 | |
ee443357 | 888 | dev_dbg(dev, "resume, ctrl %02x\n", tmp); |
7be2c7c9 DB |
889 | |
890 | return 0; | |
891 | } | |
892 | ||
2fb08e6c PF |
893 | static SIMPLE_DEV_PM_OPS(cmos_pm_ops, cmos_suspend, cmos_resume); |
894 | ||
7be2c7c9 | 895 | #else |
74c4633d RW |
896 | |
897 | static inline int cmos_poweroff(struct device *dev) | |
898 | { | |
899 | return -ENOSYS; | |
900 | } | |
901 | ||
7be2c7c9 DB |
902 | #endif |
903 | ||
904 | /*----------------------------------------------------------------*/ | |
905 | ||
e07e232c DB |
906 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
907 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
908 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
909 | * | |
910 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
911 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
912 | */ |
913 | ||
a474aaed BH |
914 | #ifdef CONFIG_ACPI |
915 | ||
916 | #include <linux/acpi.h> | |
917 | ||
a474aaed BH |
918 | static u32 rtc_handler(void *context) |
919 | { | |
b2201e54 DD |
920 | struct device *dev = context; |
921 | ||
922 | pm_wakeup_event(dev, 0); | |
a474aaed BH |
923 | acpi_clear_event(ACPI_EVENT_RTC); |
924 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
925 | return ACPI_INTERRUPT_HANDLED; | |
926 | } | |
927 | ||
b2201e54 | 928 | static inline void rtc_wake_setup(struct device *dev) |
a474aaed | 929 | { |
b2201e54 | 930 | acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, dev); |
a474aaed BH |
931 | /* |
932 | * After the RTC handler is installed, the Fixed_RTC event should | |
933 | * be disabled. Only when the RTC alarm is set will it be enabled. | |
934 | */ | |
935 | acpi_clear_event(ACPI_EVENT_RTC); | |
936 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
937 | } | |
938 | ||
939 | static void rtc_wake_on(struct device *dev) | |
940 | { | |
941 | acpi_clear_event(ACPI_EVENT_RTC); | |
942 | acpi_enable_event(ACPI_EVENT_RTC, 0); | |
943 | } | |
944 | ||
945 | static void rtc_wake_off(struct device *dev) | |
946 | { | |
947 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
948 | } | |
a474aaed BH |
949 | |
950 | /* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find | |
951 | * its device node and pass extra config data. This helps its driver use | |
952 | * capabilities that the now-obsolete mc146818 didn't have, and informs it | |
953 | * that this board's RTC is wakeup-capable (per ACPI spec). | |
954 | */ | |
955 | static struct cmos_rtc_board_info acpi_rtc_info; | |
956 | ||
5a167f45 | 957 | static void cmos_wake_setup(struct device *dev) |
a474aaed BH |
958 | { |
959 | if (acpi_disabled) | |
960 | return; | |
961 | ||
b2201e54 | 962 | rtc_wake_setup(dev); |
a474aaed BH |
963 | acpi_rtc_info.wake_on = rtc_wake_on; |
964 | acpi_rtc_info.wake_off = rtc_wake_off; | |
965 | ||
966 | /* workaround bug in some ACPI tables */ | |
967 | if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) { | |
968 | dev_dbg(dev, "bogus FADT month_alarm (%d)\n", | |
969 | acpi_gbl_FADT.month_alarm); | |
970 | acpi_gbl_FADT.month_alarm = 0; | |
971 | } | |
972 | ||
973 | acpi_rtc_info.rtc_day_alarm = acpi_gbl_FADT.day_alarm; | |
974 | acpi_rtc_info.rtc_mon_alarm = acpi_gbl_FADT.month_alarm; | |
975 | acpi_rtc_info.rtc_century = acpi_gbl_FADT.century; | |
976 | ||
977 | /* NOTE: S4_RTC_WAKE is NOT currently useful to Linux */ | |
978 | if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE) | |
979 | dev_info(dev, "RTC can wake from S4\n"); | |
980 | ||
981 | dev->platform_data = &acpi_rtc_info; | |
982 | ||
983 | /* RTC always wakes from S1/S2/S3, and often S4/STD */ | |
984 | device_init_wakeup(dev, 1); | |
985 | } | |
986 | ||
987 | #else | |
988 | ||
5a167f45 | 989 | static void cmos_wake_setup(struct device *dev) |
a474aaed BH |
990 | { |
991 | } | |
992 | ||
993 | #endif | |
994 | ||
41ac8df9 | 995 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
996 | |
997 | #include <linux/pnp.h> | |
998 | ||
5a167f45 | 999 | static int cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) |
7be2c7c9 | 1000 | { |
a474aaed BH |
1001 | cmos_wake_setup(&pnp->dev); |
1002 | ||
5e8599d2 | 1003 | if (pnp_port_start(pnp, 0) == 0x70 && !pnp_irq_valid(pnp, 0)) |
6cd8fa87 MG |
1004 | /* Some machines contain a PNP entry for the RTC, but |
1005 | * don't define the IRQ. It should always be safe to | |
1006 | * hardcode it in these cases | |
1007 | */ | |
8766ad0c BH |
1008 | return cmos_do_probe(&pnp->dev, |
1009 | pnp_get_resource(pnp, IORESOURCE_IO, 0), 8); | |
6cd8fa87 MG |
1010 | else |
1011 | return cmos_do_probe(&pnp->dev, | |
8766ad0c BH |
1012 | pnp_get_resource(pnp, IORESOURCE_IO, 0), |
1013 | pnp_irq(pnp, 0)); | |
7be2c7c9 DB |
1014 | } |
1015 | ||
1016 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
1017 | { | |
1018 | cmos_do_remove(&pnp->dev); | |
1019 | } | |
1020 | ||
004731b2 | 1021 | static void cmos_pnp_shutdown(struct pnp_dev *pnp) |
74c4633d | 1022 | { |
004731b2 | 1023 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pnp->dev)) |
74c4633d RW |
1024 | return; |
1025 | ||
1026 | cmos_do_shutdown(); | |
1027 | } | |
7be2c7c9 DB |
1028 | |
1029 | static const struct pnp_device_id rtc_ids[] = { | |
1030 | { .id = "PNP0b00", }, | |
1031 | { .id = "PNP0b01", }, | |
1032 | { .id = "PNP0b02", }, | |
1033 | { }, | |
1034 | }; | |
1035 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
1036 | ||
1037 | static struct pnp_driver cmos_pnp_driver = { | |
1038 | .name = (char *) driver_name, | |
1039 | .id_table = rtc_ids, | |
1040 | .probe = cmos_pnp_probe, | |
1041 | .remove = __exit_p(cmos_pnp_remove), | |
004731b2 | 1042 | .shutdown = cmos_pnp_shutdown, |
7be2c7c9 DB |
1043 | |
1044 | /* flag ensures resume() gets called, and stops syslog spam */ | |
1045 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
a8a3808b SK |
1046 | #ifdef CONFIG_PM_SLEEP |
1047 | .driver = { | |
1048 | .pm = &cmos_pm_ops, | |
1049 | }, | |
1050 | #endif | |
7be2c7c9 DB |
1051 | }; |
1052 | ||
1da2e3d6 | 1053 | #endif /* CONFIG_PNP */ |
7be2c7c9 | 1054 | |
3bcbaf6e SAS |
1055 | #ifdef CONFIG_OF |
1056 | static const struct of_device_id of_cmos_match[] = { | |
1057 | { | |
1058 | .compatible = "motorola,mc146818", | |
1059 | }, | |
1060 | { }, | |
1061 | }; | |
1062 | MODULE_DEVICE_TABLE(of, of_cmos_match); | |
1063 | ||
1064 | static __init void cmos_of_init(struct platform_device *pdev) | |
1065 | { | |
1066 | struct device_node *node = pdev->dev.of_node; | |
1067 | struct rtc_time time; | |
1068 | int ret; | |
1069 | const __be32 *val; | |
1070 | ||
1071 | if (!node) | |
1072 | return; | |
1073 | ||
1074 | val = of_get_property(node, "ctrl-reg", NULL); | |
1075 | if (val) | |
1076 | CMOS_WRITE(be32_to_cpup(val), RTC_CONTROL); | |
1077 | ||
1078 | val = of_get_property(node, "freq-reg", NULL); | |
1079 | if (val) | |
1080 | CMOS_WRITE(be32_to_cpup(val), RTC_FREQ_SELECT); | |
1081 | ||
1082 | get_rtc_time(&time); | |
1083 | ret = rtc_valid_tm(&time); | |
1084 | if (ret) { | |
1085 | struct rtc_time def_time = { | |
1086 | .tm_year = 1, | |
1087 | .tm_mday = 1, | |
1088 | }; | |
1089 | set_rtc_time(&def_time); | |
1090 | } | |
1091 | } | |
1092 | #else | |
1093 | static inline void cmos_of_init(struct platform_device *pdev) {} | |
3bcbaf6e | 1094 | #endif |
7be2c7c9 DB |
1095 | /*----------------------------------------------------------------*/ |
1096 | ||
41ac8df9 | 1097 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 1098 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
1099 | */ |
1100 | ||
1101 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
1102 | { | |
3bcbaf6e | 1103 | cmos_of_init(pdev); |
a474aaed | 1104 | cmos_wake_setup(&pdev->dev); |
7be2c7c9 DB |
1105 | return cmos_do_probe(&pdev->dev, |
1106 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
1107 | platform_get_irq(pdev, 0)); | |
1108 | } | |
1109 | ||
1110 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
1111 | { | |
1112 | cmos_do_remove(&pdev->dev); | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
1117 | { | |
74c4633d RW |
1118 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pdev->dev)) |
1119 | return; | |
1120 | ||
7be2c7c9 DB |
1121 | cmos_do_shutdown(); |
1122 | } | |
1123 | ||
ad28a07b KS |
1124 | /* work with hotplug and coldplug */ |
1125 | MODULE_ALIAS("platform:rtc_cmos"); | |
1126 | ||
7be2c7c9 DB |
1127 | static struct platform_driver cmos_platform_driver = { |
1128 | .remove = __exit_p(cmos_platform_remove), | |
1129 | .shutdown = cmos_platform_shutdown, | |
1130 | .driver = { | |
1131 | .name = (char *) driver_name, | |
2fb08e6c PF |
1132 | #ifdef CONFIG_PM |
1133 | .pm = &cmos_pm_ops, | |
1134 | #endif | |
c8a6046e | 1135 | .of_match_table = of_match_ptr(of_cmos_match), |
7be2c7c9 DB |
1136 | } |
1137 | }; | |
1138 | ||
65909814 TLSC |
1139 | #ifdef CONFIG_PNP |
1140 | static bool pnp_driver_registered; | |
1141 | #endif | |
1142 | static bool platform_driver_registered; | |
1143 | ||
7be2c7c9 DB |
1144 | static int __init cmos_init(void) |
1145 | { | |
72f22b1e BH |
1146 | int retval = 0; |
1147 | ||
1da2e3d6 | 1148 | #ifdef CONFIG_PNP |
65909814 TLSC |
1149 | retval = pnp_register_driver(&cmos_pnp_driver); |
1150 | if (retval == 0) | |
1151 | pnp_driver_registered = true; | |
72f22b1e BH |
1152 | #endif |
1153 | ||
65909814 | 1154 | if (!cmos_rtc.dev) { |
72f22b1e BH |
1155 | retval = platform_driver_probe(&cmos_platform_driver, |
1156 | cmos_platform_probe); | |
65909814 TLSC |
1157 | if (retval == 0) |
1158 | platform_driver_registered = true; | |
1159 | } | |
72f22b1e BH |
1160 | |
1161 | if (retval == 0) | |
1162 | return 0; | |
1163 | ||
1164 | #ifdef CONFIG_PNP | |
65909814 TLSC |
1165 | if (pnp_driver_registered) |
1166 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e BH |
1167 | #endif |
1168 | return retval; | |
7be2c7c9 DB |
1169 | } |
1170 | module_init(cmos_init); | |
1171 | ||
1172 | static void __exit cmos_exit(void) | |
1173 | { | |
1da2e3d6 | 1174 | #ifdef CONFIG_PNP |
65909814 TLSC |
1175 | if (pnp_driver_registered) |
1176 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e | 1177 | #endif |
65909814 TLSC |
1178 | if (platform_driver_registered) |
1179 | platform_driver_unregister(&cmos_platform_driver); | |
7be2c7c9 DB |
1180 | } |
1181 | module_exit(cmos_exit); | |
1182 | ||
1183 | ||
7be2c7c9 DB |
1184 | MODULE_AUTHOR("David Brownell"); |
1185 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
1186 | MODULE_LICENSE("GPL"); |