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Commit | Line | Data |
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7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
5d2a5037 | 38 | #include <linux/log2.h> |
2fb08e6c | 39 | #include <linux/pm.h> |
7be2c7c9 DB |
40 | |
41 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | |
42 | #include <asm-generic/rtc.h> | |
43 | ||
7be2c7c9 DB |
44 | struct cmos_rtc { |
45 | struct rtc_device *rtc; | |
46 | struct device *dev; | |
47 | int irq; | |
48 | struct resource *iomem; | |
49 | ||
87ac84f4 DB |
50 | void (*wake_on)(struct device *); |
51 | void (*wake_off)(struct device *); | |
52 | ||
53 | u8 enabled_wake; | |
7be2c7c9 DB |
54 | u8 suspend_ctrl; |
55 | ||
56 | /* newer hardware extends the original register set */ | |
57 | u8 day_alrm; | |
58 | u8 mon_alrm; | |
59 | u8 century; | |
60 | }; | |
61 | ||
62 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
2fac6674 | 63 | #define is_valid_irq(n) ((n) > 0) |
7be2c7c9 DB |
64 | |
65 | static const char driver_name[] = "rtc_cmos"; | |
66 | ||
bcd9b89c DB |
67 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
68 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
69 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
70 | */ | |
71 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
72 | ||
73 | static inline int is_intr(u8 rtc_intr) | |
74 | { | |
75 | if (!(rtc_intr & RTC_IRQF)) | |
76 | return 0; | |
77 | return rtc_intr & RTC_IRQMASK; | |
78 | } | |
79 | ||
7be2c7c9 DB |
80 | /*----------------------------------------------------------------*/ |
81 | ||
35d3fdd5 DB |
82 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because |
83 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | |
84 | * used in a broken "legacy replacement" mode. The breakage includes | |
85 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | |
86 | * other (better) use. | |
87 | * | |
88 | * When that broken mode is in use, platform glue provides a partial | |
89 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | |
90 | * want to use HPET for anything except those IRQs though... | |
91 | */ | |
92 | #ifdef CONFIG_HPET_EMULATE_RTC | |
93 | #include <asm/hpet.h> | |
94 | #else | |
95 | ||
96 | static inline int is_hpet_enabled(void) | |
97 | { | |
98 | return 0; | |
99 | } | |
100 | ||
101 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | |
102 | { | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | |
107 | { | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static inline int | |
112 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
113 | { | |
114 | return 0; | |
115 | } | |
116 | ||
117 | static inline int hpet_set_periodic_freq(unsigned long freq) | |
118 | { | |
119 | return 0; | |
120 | } | |
121 | ||
122 | static inline int hpet_rtc_dropped_irq(void) | |
123 | { | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static inline int hpet_rtc_timer_init(void) | |
128 | { | |
129 | return 0; | |
130 | } | |
131 | ||
132 | extern irq_handler_t hpet_rtc_interrupt; | |
133 | ||
134 | static inline int hpet_register_irq_handler(irq_handler_t handler) | |
135 | { | |
136 | return 0; | |
137 | } | |
138 | ||
139 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | |
140 | { | |
141 | return 0; | |
142 | } | |
143 | ||
144 | #endif | |
145 | ||
146 | /*----------------------------------------------------------------*/ | |
147 | ||
c8fc40cd DB |
148 | #ifdef RTC_PORT |
149 | ||
150 | /* Most newer x86 systems have two register banks, the first used | |
151 | * for RTC and NVRAM and the second only for NVRAM. Caller must | |
152 | * own rtc_lock ... and we won't worry about access during NMI. | |
153 | */ | |
154 | #define can_bank2 true | |
155 | ||
156 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
157 | { | |
158 | outb(addr, RTC_PORT(2)); | |
159 | return inb(RTC_PORT(3)); | |
160 | } | |
161 | ||
162 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
163 | { | |
164 | outb(addr, RTC_PORT(2)); | |
165 | outb(val, RTC_PORT(2)); | |
166 | } | |
167 | ||
168 | #else | |
169 | ||
170 | #define can_bank2 false | |
171 | ||
172 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
173 | { | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
178 | { | |
179 | } | |
180 | ||
181 | #endif | |
182 | ||
183 | /*----------------------------------------------------------------*/ | |
184 | ||
7be2c7c9 DB |
185 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
186 | { | |
187 | /* REVISIT: if the clock has a "century" register, use | |
188 | * that instead of the heuristic in get_rtc_time(). | |
189 | * That'll make Y3K compatility (year > 2070) easy! | |
190 | */ | |
191 | get_rtc_time(t); | |
192 | return 0; | |
193 | } | |
194 | ||
195 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
196 | { | |
197 | /* REVISIT: set the "century" register if available | |
198 | * | |
199 | * NOTE: this ignores the issue whereby updating the seconds | |
200 | * takes effect exactly 500ms after we write the register. | |
201 | * (Also queueing and other delays before we get this far.) | |
202 | */ | |
203 | return set_rtc_time(t); | |
204 | } | |
205 | ||
206 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
207 | { | |
208 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
209 | unsigned char rtc_control; | |
210 | ||
211 | if (!is_valid_irq(cmos->irq)) | |
212 | return -EIO; | |
213 | ||
214 | /* Basic alarms only support hour, minute, and seconds fields. | |
215 | * Some also support day and month, for alarms up to a year in | |
216 | * the future. | |
217 | */ | |
218 | t->time.tm_mday = -1; | |
219 | t->time.tm_mon = -1; | |
220 | ||
221 | spin_lock_irq(&rtc_lock); | |
222 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
223 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
224 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
225 | ||
226 | if (cmos->day_alrm) { | |
615bb29c ML |
227 | /* ignore upper bits on readback per ACPI spec */ |
228 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
229 | if (!t->time.tm_mday) |
230 | t->time.tm_mday = -1; | |
231 | ||
232 | if (cmos->mon_alrm) { | |
233 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
234 | if (!t->time.tm_mon) | |
235 | t->time.tm_mon = -1; | |
236 | } | |
237 | } | |
238 | ||
239 | rtc_control = CMOS_READ(RTC_CONTROL); | |
240 | spin_unlock_irq(&rtc_lock); | |
241 | ||
3804a89b AP |
242 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { |
243 | if (((unsigned)t->time.tm_sec) < 0x60) | |
244 | t->time.tm_sec = bcd2bin(t->time.tm_sec); | |
7be2c7c9 | 245 | else |
3804a89b AP |
246 | t->time.tm_sec = -1; |
247 | if (((unsigned)t->time.tm_min) < 0x60) | |
248 | t->time.tm_min = bcd2bin(t->time.tm_min); | |
249 | else | |
250 | t->time.tm_min = -1; | |
251 | if (((unsigned)t->time.tm_hour) < 0x24) | |
252 | t->time.tm_hour = bcd2bin(t->time.tm_hour); | |
253 | else | |
254 | t->time.tm_hour = -1; | |
255 | ||
256 | if (cmos->day_alrm) { | |
257 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
258 | t->time.tm_mday = bcd2bin(t->time.tm_mday); | |
7be2c7c9 | 259 | else |
3804a89b AP |
260 | t->time.tm_mday = -1; |
261 | ||
262 | if (cmos->mon_alrm) { | |
263 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
264 | t->time.tm_mon = bcd2bin(t->time.tm_mon)-1; | |
265 | else | |
266 | t->time.tm_mon = -1; | |
267 | } | |
7be2c7c9 DB |
268 | } |
269 | } | |
270 | t->time.tm_year = -1; | |
271 | ||
272 | t->enabled = !!(rtc_control & RTC_AIE); | |
273 | t->pending = 0; | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
7e2a31da DB |
278 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) |
279 | { | |
280 | unsigned char rtc_intr; | |
281 | ||
282 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
283 | * allegedly some older rtcs need that to handle irqs properly | |
284 | */ | |
285 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
286 | ||
287 | if (is_hpet_enabled()) | |
288 | return; | |
289 | ||
290 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
291 | if (is_intr(rtc_intr)) | |
292 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
293 | } | |
294 | ||
295 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | |
296 | { | |
297 | unsigned char rtc_control; | |
298 | ||
299 | /* flush any pending IRQ status, notably for update irqs, | |
300 | * before we enable new IRQs | |
301 | */ | |
302 | rtc_control = CMOS_READ(RTC_CONTROL); | |
303 | cmos_checkintr(cmos, rtc_control); | |
304 | ||
305 | rtc_control |= mask; | |
306 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
307 | hpet_set_rtc_irq_bit(mask); | |
308 | ||
309 | cmos_checkintr(cmos, rtc_control); | |
310 | } | |
311 | ||
312 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | |
313 | { | |
314 | unsigned char rtc_control; | |
315 | ||
316 | rtc_control = CMOS_READ(RTC_CONTROL); | |
317 | rtc_control &= ~mask; | |
318 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
319 | hpet_mask_rtc_irq_bit(mask); | |
320 | ||
321 | cmos_checkintr(cmos, rtc_control); | |
322 | } | |
323 | ||
7be2c7c9 DB |
324 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
325 | { | |
326 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
3804a89b | 327 | unsigned char mon, mday, hrs, min, sec, rtc_control; |
7be2c7c9 DB |
328 | |
329 | if (!is_valid_irq(cmos->irq)) | |
330 | return -EIO; | |
331 | ||
2b653e06 | 332 | mon = t->time.tm_mon + 1; |
7be2c7c9 | 333 | mday = t->time.tm_mday; |
7be2c7c9 | 334 | hrs = t->time.tm_hour; |
7be2c7c9 | 335 | min = t->time.tm_min; |
7be2c7c9 | 336 | sec = t->time.tm_sec; |
3804a89b AP |
337 | |
338 | rtc_control = CMOS_READ(RTC_CONTROL); | |
339 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { | |
340 | /* Writing 0xff means "don't care" or "match all". */ | |
341 | mon = (mon <= 12) ? bin2bcd(mon) : 0xff; | |
342 | mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; | |
343 | hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; | |
344 | min = (min < 60) ? bin2bcd(min) : 0xff; | |
345 | sec = (sec < 60) ? bin2bcd(sec) : 0xff; | |
346 | } | |
7be2c7c9 DB |
347 | |
348 | spin_lock_irq(&rtc_lock); | |
349 | ||
350 | /* next rtc irq must not be from previous alarm setting */ | |
7e2a31da | 351 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
352 | |
353 | /* update alarm */ | |
354 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
355 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
356 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
357 | ||
358 | /* the system may support an "enhanced" alarm */ | |
359 | if (cmos->day_alrm) { | |
360 | CMOS_WRITE(mday, cmos->day_alrm); | |
361 | if (cmos->mon_alrm) | |
362 | CMOS_WRITE(mon, cmos->mon_alrm); | |
363 | } | |
364 | ||
35d3fdd5 DB |
365 | /* FIXME the HPET alarm glue currently ignores day_alrm |
366 | * and mon_alrm ... | |
367 | */ | |
368 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | |
369 | ||
7e2a31da DB |
370 | if (t->enabled) |
371 | cmos_irq_enable(cmos, RTC_AIE); | |
7be2c7c9 DB |
372 | |
373 | spin_unlock_irq(&rtc_lock); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
57deb526 | 378 | static int cmos_irq_set_freq(struct device *dev, int freq) |
7be2c7c9 DB |
379 | { |
380 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
381 | int f; | |
382 | unsigned long flags; | |
383 | ||
384 | if (!is_valid_irq(cmos->irq)) | |
385 | return -ENXIO; | |
386 | ||
5d2a5037 JC |
387 | if (!is_power_of_2(freq)) |
388 | return -EINVAL; | |
7be2c7c9 DB |
389 | /* 0 = no irqs; 1 = 2^15 Hz ... 15 = 2^0 Hz */ |
390 | f = ffs(freq); | |
97144c67 DB |
391 | if (f-- > 16) |
392 | return -EINVAL; | |
393 | f = 16 - f; | |
7be2c7c9 DB |
394 | |
395 | spin_lock_irqsave(&rtc_lock, flags); | |
35d3fdd5 DB |
396 | hpet_set_periodic_freq(freq); |
397 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
398 | spin_unlock_irqrestore(&rtc_lock, flags); |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
57deb526 AZ |
403 | static int cmos_irq_set_state(struct device *dev, int enabled) |
404 | { | |
405 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
57deb526 AZ |
406 | unsigned long flags; |
407 | ||
408 | if (!is_valid_irq(cmos->irq)) | |
409 | return -ENXIO; | |
410 | ||
411 | spin_lock_irqsave(&rtc_lock, flags); | |
57deb526 | 412 | |
7e2a31da DB |
413 | if (enabled) |
414 | cmos_irq_enable(cmos, RTC_PIE); | |
415 | else | |
416 | cmos_irq_disable(cmos, RTC_PIE); | |
57deb526 AZ |
417 | |
418 | spin_unlock_irqrestore(&rtc_lock, flags); | |
419 | return 0; | |
420 | } | |
421 | ||
a8462ef6 | 422 | static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled) |
7be2c7c9 DB |
423 | { |
424 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
7be2c7c9 DB |
425 | unsigned long flags; |
426 | ||
a8462ef6 HRK |
427 | if (!is_valid_irq(cmos->irq)) |
428 | return -EINVAL; | |
7be2c7c9 DB |
429 | |
430 | spin_lock_irqsave(&rtc_lock, flags); | |
a8462ef6 HRK |
431 | |
432 | if (enabled) | |
7e2a31da | 433 | cmos_irq_enable(cmos, RTC_AIE); |
a8462ef6 HRK |
434 | else |
435 | cmos_irq_disable(cmos, RTC_AIE); | |
436 | ||
7be2c7c9 DB |
437 | spin_unlock_irqrestore(&rtc_lock, flags); |
438 | return 0; | |
439 | } | |
440 | ||
a8462ef6 HRK |
441 | static int cmos_update_irq_enable(struct device *dev, unsigned int enabled) |
442 | { | |
443 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
444 | unsigned long flags; | |
445 | ||
446 | if (!is_valid_irq(cmos->irq)) | |
447 | return -EINVAL; | |
448 | ||
449 | spin_lock_irqsave(&rtc_lock, flags); | |
450 | ||
451 | if (enabled) | |
452 | cmos_irq_enable(cmos, RTC_UIE); | |
453 | else | |
454 | cmos_irq_disable(cmos, RTC_UIE); | |
455 | ||
456 | spin_unlock_irqrestore(&rtc_lock, flags); | |
457 | return 0; | |
458 | } | |
7be2c7c9 DB |
459 | |
460 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
461 | ||
462 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
463 | { | |
464 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
465 | unsigned char rtc_control, valid; | |
466 | ||
467 | spin_lock_irq(&rtc_lock); | |
468 | rtc_control = CMOS_READ(RTC_CONTROL); | |
469 | valid = CMOS_READ(RTC_VALID); | |
470 | spin_unlock_irq(&rtc_lock); | |
471 | ||
472 | /* NOTE: at least ICH6 reports battery status using a different | |
473 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
474 | */ | |
475 | return seq_printf(seq, | |
476 | "periodic_IRQ\t: %s\n" | |
477 | "update_IRQ\t: %s\n" | |
c8626a1d | 478 | "HPET_emulated\t: %s\n" |
7be2c7c9 | 479 | // "square_wave\t: %s\n" |
3804a89b | 480 | "BCD\t\t: %s\n" |
7be2c7c9 DB |
481 | "DST_enable\t: %s\n" |
482 | "periodic_freq\t: %d\n" | |
483 | "batt_status\t: %s\n", | |
484 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
485 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 486 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 | 487 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
3804a89b | 488 | (rtc_control & RTC_DM_BINARY) ? "no" : "yes", |
7be2c7c9 DB |
489 | (rtc_control & RTC_DST_EN) ? "yes" : "no", |
490 | cmos->rtc->irq_freq, | |
491 | (valid & RTC_VRT) ? "okay" : "dead"); | |
492 | } | |
493 | ||
494 | #else | |
495 | #define cmos_procfs NULL | |
496 | #endif | |
497 | ||
498 | static const struct rtc_class_ops cmos_rtc_ops = { | |
a8462ef6 HRK |
499 | .read_time = cmos_read_time, |
500 | .set_time = cmos_set_time, | |
501 | .read_alarm = cmos_read_alarm, | |
502 | .set_alarm = cmos_set_alarm, | |
503 | .proc = cmos_procfs, | |
504 | .irq_set_freq = cmos_irq_set_freq, | |
505 | .irq_set_state = cmos_irq_set_state, | |
506 | .alarm_irq_enable = cmos_alarm_irq_enable, | |
507 | .update_irq_enable = cmos_update_irq_enable, | |
7be2c7c9 DB |
508 | }; |
509 | ||
510 | /*----------------------------------------------------------------*/ | |
511 | ||
e07e232c DB |
512 | /* |
513 | * All these chips have at least 64 bytes of address space, shared by | |
514 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
515 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
516 | */ | |
517 | ||
518 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
519 | ||
520 | static ssize_t | |
2c3c8bea CW |
521 | cmos_nvram_read(struct file *filp, struct kobject *kobj, |
522 | struct bin_attribute *attr, | |
e07e232c DB |
523 | char *buf, loff_t off, size_t count) |
524 | { | |
525 | int retval; | |
526 | ||
527 | if (unlikely(off >= attr->size)) | |
528 | return 0; | |
c8fc40cd DB |
529 | if (unlikely(off < 0)) |
530 | return -EINVAL; | |
e07e232c DB |
531 | if ((off + count) > attr->size) |
532 | count = attr->size - off; | |
533 | ||
c8fc40cd | 534 | off += NVRAM_OFFSET; |
e07e232c | 535 | spin_lock_irq(&rtc_lock); |
c8fc40cd DB |
536 | for (retval = 0; count; count--, off++, retval++) { |
537 | if (off < 128) | |
538 | *buf++ = CMOS_READ(off); | |
539 | else if (can_bank2) | |
540 | *buf++ = cmos_read_bank2(off); | |
541 | else | |
542 | break; | |
543 | } | |
e07e232c DB |
544 | spin_unlock_irq(&rtc_lock); |
545 | ||
546 | return retval; | |
547 | } | |
548 | ||
549 | static ssize_t | |
2c3c8bea CW |
550 | cmos_nvram_write(struct file *filp, struct kobject *kobj, |
551 | struct bin_attribute *attr, | |
e07e232c DB |
552 | char *buf, loff_t off, size_t count) |
553 | { | |
554 | struct cmos_rtc *cmos; | |
555 | int retval; | |
556 | ||
557 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
558 | if (unlikely(off >= attr->size)) | |
559 | return -EFBIG; | |
c8fc40cd DB |
560 | if (unlikely(off < 0)) |
561 | return -EINVAL; | |
e07e232c DB |
562 | if ((off + count) > attr->size) |
563 | count = attr->size - off; | |
564 | ||
565 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
566 | * checksum on part of the NVRAM data. That's currently ignored | |
567 | * here. If userspace is smart enough to know what fields of | |
568 | * NVRAM to update, updating checksums is also part of its job. | |
569 | */ | |
c8fc40cd | 570 | off += NVRAM_OFFSET; |
e07e232c | 571 | spin_lock_irq(&rtc_lock); |
c8fc40cd | 572 | for (retval = 0; count; count--, off++, retval++) { |
e07e232c DB |
573 | /* don't trash RTC registers */ |
574 | if (off == cmos->day_alrm | |
575 | || off == cmos->mon_alrm | |
576 | || off == cmos->century) | |
577 | buf++; | |
c8fc40cd | 578 | else if (off < 128) |
e07e232c | 579 | CMOS_WRITE(*buf++, off); |
c8fc40cd DB |
580 | else if (can_bank2) |
581 | cmos_write_bank2(*buf++, off); | |
582 | else | |
583 | break; | |
e07e232c DB |
584 | } |
585 | spin_unlock_irq(&rtc_lock); | |
586 | ||
587 | return retval; | |
588 | } | |
589 | ||
590 | static struct bin_attribute nvram = { | |
591 | .attr = { | |
592 | .name = "nvram", | |
593 | .mode = S_IRUGO | S_IWUSR, | |
e07e232c DB |
594 | }, |
595 | ||
596 | .read = cmos_nvram_read, | |
597 | .write = cmos_nvram_write, | |
598 | /* size gets set up later */ | |
599 | }; | |
600 | ||
601 | /*----------------------------------------------------------------*/ | |
602 | ||
7be2c7c9 DB |
603 | static struct cmos_rtc cmos_rtc; |
604 | ||
605 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
606 | { | |
607 | u8 irqstat; | |
8a0bdfd7 | 608 | u8 rtc_control; |
7be2c7c9 DB |
609 | |
610 | spin_lock(&rtc_lock); | |
35d3fdd5 DB |
611 | |
612 | /* When the HPET interrupt handler calls us, the interrupt | |
613 | * status is passed as arg1 instead of the irq number. But | |
614 | * always clear irq status, even when HPET is in the way. | |
615 | * | |
616 | * Note that HPET and RTC are almost certainly out of phase, | |
617 | * giving different IRQ status ... | |
9d8af78b | 618 | */ |
35d3fdd5 DB |
619 | irqstat = CMOS_READ(RTC_INTR_FLAGS); |
620 | rtc_control = CMOS_READ(RTC_CONTROL); | |
9d8af78b BW |
621 | if (is_hpet_enabled()) |
622 | irqstat = (unsigned long)irq & 0xF0; | |
35d3fdd5 | 623 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
8a0bdfd7 DB |
624 | |
625 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
626 | * Similar code may be needed in system wakeup paths, in case the | |
627 | * alarm woke the system. | |
628 | */ | |
629 | if (irqstat & RTC_AIE) { | |
630 | rtc_control &= ~RTC_AIE; | |
631 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
35d3fdd5 DB |
632 | hpet_mask_rtc_irq_bit(RTC_AIE); |
633 | ||
8a0bdfd7 DB |
634 | CMOS_READ(RTC_INTR_FLAGS); |
635 | } | |
7be2c7c9 DB |
636 | spin_unlock(&rtc_lock); |
637 | ||
bcd9b89c | 638 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
639 | rtc_update_irq(p, 1, irqstat); |
640 | return IRQ_HANDLED; | |
641 | } else | |
642 | return IRQ_NONE; | |
643 | } | |
644 | ||
41ac8df9 | 645 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
646 | #define INITSECTION |
647 | ||
648 | #else | |
7be2c7c9 DB |
649 | #define INITSECTION __init |
650 | #endif | |
651 | ||
652 | static int INITSECTION | |
653 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
654 | { | |
655 | struct cmos_rtc_board_info *info = dev->platform_data; | |
656 | int retval = 0; | |
657 | unsigned char rtc_control; | |
e07e232c | 658 | unsigned address_space; |
7be2c7c9 DB |
659 | |
660 | /* there can be only one ... */ | |
661 | if (cmos_rtc.dev) | |
662 | return -EBUSY; | |
663 | ||
664 | if (!ports) | |
665 | return -ENODEV; | |
666 | ||
05440dfc DB |
667 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
668 | * | |
669 | * REVISIT non-x86 systems may instead use memory space resources | |
670 | * (needing ioremap etc), not i/o space resources like this ... | |
671 | */ | |
672 | ports = request_region(ports->start, | |
673 | ports->end + 1 - ports->start, | |
674 | driver_name); | |
675 | if (!ports) { | |
676 | dev_dbg(dev, "i/o registers already in use\n"); | |
677 | return -EBUSY; | |
678 | } | |
679 | ||
7be2c7c9 DB |
680 | cmos_rtc.irq = rtc_irq; |
681 | cmos_rtc.iomem = ports; | |
682 | ||
e07e232c DB |
683 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
684 | * driver did, but don't reject unknown configs. Old hardware | |
c8fc40cd DB |
685 | * won't address 128 bytes. Newer chips have multiple banks, |
686 | * though they may not be listed in one I/O resource. | |
e07e232c DB |
687 | */ |
688 | #if defined(CONFIG_ATARI) | |
689 | address_space = 64; | |
95abd0df | 690 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ |
8cb7c71b SK |
691 | || defined(__sparc__) || defined(__mips__) \ |
692 | || defined(__powerpc__) | |
e07e232c DB |
693 | address_space = 128; |
694 | #else | |
695 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
696 | address_space = 128; | |
697 | #endif | |
c8fc40cd DB |
698 | if (can_bank2 && ports->end > (ports->start + 1)) |
699 | address_space = 256; | |
e07e232c | 700 | |
87ac84f4 DB |
701 | /* For ACPI systems extension info comes from the FADT. On others, |
702 | * board specific setup provides it as appropriate. Systems where | |
703 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
704 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
705 | * |
706 | * Note that ACPI doesn't preclude putting these registers into | |
707 | * "extended" areas of the chip, including some that we won't yet | |
708 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
709 | */ |
710 | if (info) { | |
e07e232c DB |
711 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
712 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
713 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
714 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
715 | if (info->rtc_century && info->rtc_century < 128) | |
716 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
717 | |
718 | if (info->wake_on && info->wake_off) { | |
719 | cmos_rtc.wake_on = info->wake_on; | |
720 | cmos_rtc.wake_off = info->wake_off; | |
721 | } | |
7be2c7c9 DB |
722 | } |
723 | ||
6ba8bcd4 DC |
724 | cmos_rtc.dev = dev; |
725 | dev_set_drvdata(dev, &cmos_rtc); | |
726 | ||
7be2c7c9 DB |
727 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, |
728 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
729 | if (IS_ERR(cmos_rtc.rtc)) { |
730 | retval = PTR_ERR(cmos_rtc.rtc); | |
731 | goto cleanup0; | |
732 | } | |
7be2c7c9 | 733 | |
d4afc76c | 734 | rename_region(ports, dev_name(&cmos_rtc.rtc->dev)); |
7be2c7c9 DB |
735 | |
736 | spin_lock_irq(&rtc_lock); | |
737 | ||
738 | /* force periodic irq to CMOS reset default of 1024Hz; | |
739 | * | |
740 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
741 | * doesn't use 32KHz here ... for portability we might need to | |
742 | * do something about other clock frequencies. | |
743 | */ | |
7be2c7c9 | 744 | cmos_rtc.rtc->irq_freq = 1024; |
35d3fdd5 DB |
745 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); |
746 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 | 747 | |
7e2a31da DB |
748 | /* disable irqs */ |
749 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | |
35d3fdd5 | 750 | |
7e2a31da | 751 | rtc_control = CMOS_READ(RTC_CONTROL); |
7be2c7c9 DB |
752 | |
753 | spin_unlock_irq(&rtc_lock); | |
754 | ||
3804a89b | 755 | /* FIXME: |
7be2c7c9 DB |
756 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. |
757 | */ | |
3804a89b AP |
758 | if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { |
759 | dev_warn(dev, "only 24-hr supported\n"); | |
7be2c7c9 DB |
760 | retval = -ENXIO; |
761 | goto cleanup1; | |
762 | } | |
763 | ||
9d8af78b BW |
764 | if (is_valid_irq(rtc_irq)) { |
765 | irq_handler_t rtc_cmos_int_handler; | |
766 | ||
767 | if (is_hpet_enabled()) { | |
768 | int err; | |
769 | ||
770 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
771 | err = hpet_register_irq_handler(cmos_interrupt); | |
772 | if (err != 0) { | |
773 | printk(KERN_WARNING "hpet_register_irq_handler " | |
774 | " failed in rtc_init()."); | |
775 | goto cleanup1; | |
776 | } | |
777 | } else | |
778 | rtc_cmos_int_handler = cmos_interrupt; | |
779 | ||
780 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
d4afc76c | 781 | IRQF_DISABLED, dev_name(&cmos_rtc.rtc->dev), |
ab6a2d70 | 782 | cmos_rtc.rtc); |
9d8af78b BW |
783 | if (retval < 0) { |
784 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
785 | goto cleanup1; | |
786 | } | |
7be2c7c9 | 787 | } |
9d8af78b | 788 | hpet_rtc_timer_init(); |
7be2c7c9 | 789 | |
e07e232c DB |
790 | /* export at least the first block of NVRAM */ |
791 | nvram.size = address_space - NVRAM_OFFSET; | |
792 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
793 | if (retval < 0) { | |
794 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
795 | goto cleanup2; | |
796 | } | |
7be2c7c9 | 797 | |
6d029b64 KH |
798 | pr_info("%s: %s%s, %zd bytes nvram%s\n", |
799 | dev_name(&cmos_rtc.rtc->dev), | |
800 | !is_valid_irq(rtc_irq) ? "no alarms" : | |
801 | cmos_rtc.mon_alrm ? "alarms up to one year" : | |
802 | cmos_rtc.day_alrm ? "alarms up to one month" : | |
803 | "alarms up to one day", | |
804 | cmos_rtc.century ? ", y3k" : "", | |
805 | nvram.size, | |
806 | is_hpet_enabled() ? ", hpet irqs" : ""); | |
7be2c7c9 DB |
807 | |
808 | return 0; | |
809 | ||
e07e232c DB |
810 | cleanup2: |
811 | if (is_valid_irq(rtc_irq)) | |
812 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 813 | cleanup1: |
05440dfc | 814 | cmos_rtc.dev = NULL; |
7be2c7c9 | 815 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc DB |
816 | cleanup0: |
817 | release_region(ports->start, ports->end + 1 - ports->start); | |
7be2c7c9 DB |
818 | return retval; |
819 | } | |
820 | ||
821 | static void cmos_do_shutdown(void) | |
822 | { | |
7be2c7c9 | 823 | spin_lock_irq(&rtc_lock); |
7e2a31da | 824 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); |
7be2c7c9 DB |
825 | spin_unlock_irq(&rtc_lock); |
826 | } | |
827 | ||
828 | static void __exit cmos_do_remove(struct device *dev) | |
829 | { | |
830 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 831 | struct resource *ports; |
7be2c7c9 DB |
832 | |
833 | cmos_do_shutdown(); | |
834 | ||
e07e232c DB |
835 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
836 | ||
9d8af78b | 837 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 838 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
839 | hpet_unregister_irq_handler(cmos_interrupt); |
840 | } | |
7be2c7c9 | 841 | |
05440dfc DB |
842 | rtc_device_unregister(cmos->rtc); |
843 | cmos->rtc = NULL; | |
7be2c7c9 | 844 | |
05440dfc DB |
845 | ports = cmos->iomem; |
846 | release_region(ports->start, ports->end + 1 - ports->start); | |
847 | cmos->iomem = NULL; | |
848 | ||
849 | cmos->dev = NULL; | |
7be2c7c9 DB |
850 | dev_set_drvdata(dev, NULL); |
851 | } | |
852 | ||
853 | #ifdef CONFIG_PM | |
854 | ||
2fb08e6c | 855 | static int cmos_suspend(struct device *dev) |
7be2c7c9 DB |
856 | { |
857 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
bcd9b89c | 858 | unsigned char tmp; |
7be2c7c9 DB |
859 | |
860 | /* only the alarm might be a wakeup event source */ | |
861 | spin_lock_irq(&rtc_lock); | |
862 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
863 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
35d3fdd5 | 864 | unsigned char mask; |
bcd9b89c | 865 | |
74c4633d | 866 | if (device_may_wakeup(dev)) |
35d3fdd5 | 867 | mask = RTC_IRQMASK & ~RTC_AIE; |
7be2c7c9 | 868 | else |
35d3fdd5 DB |
869 | mask = RTC_IRQMASK; |
870 | tmp &= ~mask; | |
7be2c7c9 | 871 | CMOS_WRITE(tmp, RTC_CONTROL); |
35d3fdd5 | 872 | |
d1b2efa8 ML |
873 | /* shut down hpet emulation - we don't need it for alarm */ |
874 | hpet_mask_rtc_irq_bit(RTC_PIE|RTC_AIE|RTC_UIE); | |
7e2a31da | 875 | cmos_checkintr(cmos, tmp); |
bcd9b89c | 876 | } |
7be2c7c9 DB |
877 | spin_unlock_irq(&rtc_lock); |
878 | ||
87ac84f4 DB |
879 | if (tmp & RTC_AIE) { |
880 | cmos->enabled_wake = 1; | |
881 | if (cmos->wake_on) | |
882 | cmos->wake_on(dev); | |
883 | else | |
884 | enable_irq_wake(cmos->irq); | |
885 | } | |
7be2c7c9 DB |
886 | |
887 | pr_debug("%s: suspend%s, ctrl %02x\n", | |
d4afc76c | 888 | dev_name(&cmos_rtc.rtc->dev), |
7be2c7c9 DB |
889 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
890 | tmp); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
74c4633d RW |
895 | /* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even |
896 | * after a detour through G3 "mechanical off", although the ACPI spec | |
897 | * says wakeup should only work from G1/S4 "hibernate". To most users, | |
898 | * distinctions between S4 and S5 are pointless. So when the hardware | |
899 | * allows, don't draw that distinction. | |
900 | */ | |
901 | static inline int cmos_poweroff(struct device *dev) | |
902 | { | |
2fb08e6c | 903 | return cmos_suspend(dev); |
74c4633d RW |
904 | } |
905 | ||
7be2c7c9 DB |
906 | static int cmos_resume(struct device *dev) |
907 | { | |
908 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
909 | unsigned char tmp = cmos->suspend_ctrl; | |
910 | ||
7be2c7c9 | 911 | /* re-enable any irqs previously active */ |
35d3fdd5 DB |
912 | if (tmp & RTC_IRQMASK) { |
913 | unsigned char mask; | |
7be2c7c9 | 914 | |
87ac84f4 DB |
915 | if (cmos->enabled_wake) { |
916 | if (cmos->wake_off) | |
917 | cmos->wake_off(dev); | |
918 | else | |
919 | disable_irq_wake(cmos->irq); | |
920 | cmos->enabled_wake = 0; | |
921 | } | |
7be2c7c9 DB |
922 | |
923 | spin_lock_irq(&rtc_lock); | |
35d3fdd5 DB |
924 | do { |
925 | CMOS_WRITE(tmp, RTC_CONTROL); | |
926 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); | |
927 | ||
928 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
929 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | |
7e2a31da | 930 | if (!is_hpet_enabled() || !is_intr(mask)) |
35d3fdd5 DB |
931 | break; |
932 | ||
933 | /* force one-shot behavior if HPET blocked | |
934 | * the wake alarm's irq | |
935 | */ | |
936 | rtc_update_irq(cmos->rtc, 1, mask); | |
937 | tmp &= ~RTC_AIE; | |
938 | hpet_mask_rtc_irq_bit(RTC_AIE); | |
939 | } while (mask & RTC_AIE); | |
bcd9b89c | 940 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 DB |
941 | } |
942 | ||
943 | pr_debug("%s: resume, ctrl %02x\n", | |
d4afc76c | 944 | dev_name(&cmos_rtc.rtc->dev), |
35d3fdd5 | 945 | tmp); |
7be2c7c9 DB |
946 | |
947 | return 0; | |
948 | } | |
949 | ||
2fb08e6c PF |
950 | static SIMPLE_DEV_PM_OPS(cmos_pm_ops, cmos_suspend, cmos_resume); |
951 | ||
7be2c7c9 | 952 | #else |
74c4633d RW |
953 | |
954 | static inline int cmos_poweroff(struct device *dev) | |
955 | { | |
956 | return -ENOSYS; | |
957 | } | |
958 | ||
7be2c7c9 DB |
959 | #endif |
960 | ||
961 | /*----------------------------------------------------------------*/ | |
962 | ||
e07e232c DB |
963 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
964 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
965 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
966 | * | |
967 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
968 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
969 | */ |
970 | ||
a474aaed BH |
971 | #ifdef CONFIG_ACPI |
972 | ||
973 | #include <linux/acpi.h> | |
974 | ||
a474aaed BH |
975 | static u32 rtc_handler(void *context) |
976 | { | |
977 | acpi_clear_event(ACPI_EVENT_RTC); | |
978 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
979 | return ACPI_INTERRUPT_HANDLED; | |
980 | } | |
981 | ||
982 | static inline void rtc_wake_setup(void) | |
983 | { | |
984 | acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, NULL); | |
985 | /* | |
986 | * After the RTC handler is installed, the Fixed_RTC event should | |
987 | * be disabled. Only when the RTC alarm is set will it be enabled. | |
988 | */ | |
989 | acpi_clear_event(ACPI_EVENT_RTC); | |
990 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
991 | } | |
992 | ||
993 | static void rtc_wake_on(struct device *dev) | |
994 | { | |
995 | acpi_clear_event(ACPI_EVENT_RTC); | |
996 | acpi_enable_event(ACPI_EVENT_RTC, 0); | |
997 | } | |
998 | ||
999 | static void rtc_wake_off(struct device *dev) | |
1000 | { | |
1001 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
1002 | } | |
a474aaed BH |
1003 | |
1004 | /* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find | |
1005 | * its device node and pass extra config data. This helps its driver use | |
1006 | * capabilities that the now-obsolete mc146818 didn't have, and informs it | |
1007 | * that this board's RTC is wakeup-capable (per ACPI spec). | |
1008 | */ | |
1009 | static struct cmos_rtc_board_info acpi_rtc_info; | |
1010 | ||
1011 | static void __devinit | |
1012 | cmos_wake_setup(struct device *dev) | |
1013 | { | |
1014 | if (acpi_disabled) | |
1015 | return; | |
1016 | ||
1017 | rtc_wake_setup(); | |
1018 | acpi_rtc_info.wake_on = rtc_wake_on; | |
1019 | acpi_rtc_info.wake_off = rtc_wake_off; | |
1020 | ||
1021 | /* workaround bug in some ACPI tables */ | |
1022 | if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) { | |
1023 | dev_dbg(dev, "bogus FADT month_alarm (%d)\n", | |
1024 | acpi_gbl_FADT.month_alarm); | |
1025 | acpi_gbl_FADT.month_alarm = 0; | |
1026 | } | |
1027 | ||
1028 | acpi_rtc_info.rtc_day_alarm = acpi_gbl_FADT.day_alarm; | |
1029 | acpi_rtc_info.rtc_mon_alarm = acpi_gbl_FADT.month_alarm; | |
1030 | acpi_rtc_info.rtc_century = acpi_gbl_FADT.century; | |
1031 | ||
1032 | /* NOTE: S4_RTC_WAKE is NOT currently useful to Linux */ | |
1033 | if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE) | |
1034 | dev_info(dev, "RTC can wake from S4\n"); | |
1035 | ||
1036 | dev->platform_data = &acpi_rtc_info; | |
1037 | ||
1038 | /* RTC always wakes from S1/S2/S3, and often S4/STD */ | |
1039 | device_init_wakeup(dev, 1); | |
1040 | } | |
1041 | ||
1042 | #else | |
1043 | ||
1044 | static void __devinit | |
1045 | cmos_wake_setup(struct device *dev) | |
1046 | { | |
1047 | } | |
1048 | ||
1049 | #endif | |
1050 | ||
41ac8df9 | 1051 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
1052 | |
1053 | #include <linux/pnp.h> | |
1054 | ||
1055 | static int __devinit | |
1056 | cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) | |
1057 | { | |
a474aaed BH |
1058 | cmos_wake_setup(&pnp->dev); |
1059 | ||
6cd8fa87 MG |
1060 | if (pnp_port_start(pnp,0) == 0x70 && !pnp_irq_valid(pnp,0)) |
1061 | /* Some machines contain a PNP entry for the RTC, but | |
1062 | * don't define the IRQ. It should always be safe to | |
1063 | * hardcode it in these cases | |
1064 | */ | |
8766ad0c BH |
1065 | return cmos_do_probe(&pnp->dev, |
1066 | pnp_get_resource(pnp, IORESOURCE_IO, 0), 8); | |
6cd8fa87 MG |
1067 | else |
1068 | return cmos_do_probe(&pnp->dev, | |
8766ad0c BH |
1069 | pnp_get_resource(pnp, IORESOURCE_IO, 0), |
1070 | pnp_irq(pnp, 0)); | |
7be2c7c9 DB |
1071 | } |
1072 | ||
1073 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
1074 | { | |
1075 | cmos_do_remove(&pnp->dev); | |
1076 | } | |
1077 | ||
1078 | #ifdef CONFIG_PM | |
1079 | ||
1080 | static int cmos_pnp_suspend(struct pnp_dev *pnp, pm_message_t mesg) | |
1081 | { | |
2fb08e6c | 1082 | return cmos_suspend(&pnp->dev); |
7be2c7c9 DB |
1083 | } |
1084 | ||
1085 | static int cmos_pnp_resume(struct pnp_dev *pnp) | |
1086 | { | |
1087 | return cmos_resume(&pnp->dev); | |
1088 | } | |
1089 | ||
1090 | #else | |
1091 | #define cmos_pnp_suspend NULL | |
1092 | #define cmos_pnp_resume NULL | |
1093 | #endif | |
1094 | ||
004731b2 | 1095 | static void cmos_pnp_shutdown(struct pnp_dev *pnp) |
74c4633d | 1096 | { |
004731b2 | 1097 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pnp->dev)) |
74c4633d RW |
1098 | return; |
1099 | ||
1100 | cmos_do_shutdown(); | |
1101 | } | |
7be2c7c9 DB |
1102 | |
1103 | static const struct pnp_device_id rtc_ids[] = { | |
1104 | { .id = "PNP0b00", }, | |
1105 | { .id = "PNP0b01", }, | |
1106 | { .id = "PNP0b02", }, | |
1107 | { }, | |
1108 | }; | |
1109 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
1110 | ||
1111 | static struct pnp_driver cmos_pnp_driver = { | |
1112 | .name = (char *) driver_name, | |
1113 | .id_table = rtc_ids, | |
1114 | .probe = cmos_pnp_probe, | |
1115 | .remove = __exit_p(cmos_pnp_remove), | |
004731b2 | 1116 | .shutdown = cmos_pnp_shutdown, |
7be2c7c9 DB |
1117 | |
1118 | /* flag ensures resume() gets called, and stops syslog spam */ | |
1119 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1120 | .suspend = cmos_pnp_suspend, | |
1121 | .resume = cmos_pnp_resume, | |
1122 | }; | |
1123 | ||
1da2e3d6 | 1124 | #endif /* CONFIG_PNP */ |
7be2c7c9 DB |
1125 | |
1126 | /*----------------------------------------------------------------*/ | |
1127 | ||
41ac8df9 | 1128 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 1129 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
1130 | */ |
1131 | ||
1132 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
1133 | { | |
a474aaed | 1134 | cmos_wake_setup(&pdev->dev); |
7be2c7c9 DB |
1135 | return cmos_do_probe(&pdev->dev, |
1136 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
1137 | platform_get_irq(pdev, 0)); | |
1138 | } | |
1139 | ||
1140 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
1141 | { | |
1142 | cmos_do_remove(&pdev->dev); | |
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
1147 | { | |
74c4633d RW |
1148 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pdev->dev)) |
1149 | return; | |
1150 | ||
7be2c7c9 DB |
1151 | cmos_do_shutdown(); |
1152 | } | |
1153 | ||
ad28a07b KS |
1154 | /* work with hotplug and coldplug */ |
1155 | MODULE_ALIAS("platform:rtc_cmos"); | |
1156 | ||
7be2c7c9 DB |
1157 | static struct platform_driver cmos_platform_driver = { |
1158 | .remove = __exit_p(cmos_platform_remove), | |
1159 | .shutdown = cmos_platform_shutdown, | |
1160 | .driver = { | |
1161 | .name = (char *) driver_name, | |
2fb08e6c PF |
1162 | #ifdef CONFIG_PM |
1163 | .pm = &cmos_pm_ops, | |
1164 | #endif | |
7be2c7c9 DB |
1165 | } |
1166 | }; | |
1167 | ||
65909814 TLSC |
1168 | #ifdef CONFIG_PNP |
1169 | static bool pnp_driver_registered; | |
1170 | #endif | |
1171 | static bool platform_driver_registered; | |
1172 | ||
7be2c7c9 DB |
1173 | static int __init cmos_init(void) |
1174 | { | |
72f22b1e BH |
1175 | int retval = 0; |
1176 | ||
1da2e3d6 | 1177 | #ifdef CONFIG_PNP |
65909814 TLSC |
1178 | retval = pnp_register_driver(&cmos_pnp_driver); |
1179 | if (retval == 0) | |
1180 | pnp_driver_registered = true; | |
72f22b1e BH |
1181 | #endif |
1182 | ||
65909814 | 1183 | if (!cmos_rtc.dev) { |
72f22b1e BH |
1184 | retval = platform_driver_probe(&cmos_platform_driver, |
1185 | cmos_platform_probe); | |
65909814 TLSC |
1186 | if (retval == 0) |
1187 | platform_driver_registered = true; | |
1188 | } | |
72f22b1e BH |
1189 | |
1190 | if (retval == 0) | |
1191 | return 0; | |
1192 | ||
1193 | #ifdef CONFIG_PNP | |
65909814 TLSC |
1194 | if (pnp_driver_registered) |
1195 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e BH |
1196 | #endif |
1197 | return retval; | |
7be2c7c9 DB |
1198 | } |
1199 | module_init(cmos_init); | |
1200 | ||
1201 | static void __exit cmos_exit(void) | |
1202 | { | |
1da2e3d6 | 1203 | #ifdef CONFIG_PNP |
65909814 TLSC |
1204 | if (pnp_driver_registered) |
1205 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e | 1206 | #endif |
65909814 TLSC |
1207 | if (platform_driver_registered) |
1208 | platform_driver_unregister(&cmos_platform_driver); | |
7be2c7c9 DB |
1209 | } |
1210 | module_exit(cmos_exit); | |
1211 | ||
1212 | ||
7be2c7c9 DB |
1213 | MODULE_AUTHOR("David Brownell"); |
1214 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
1215 | MODULE_LICENSE("GPL"); |