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Commit | Line | Data |
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7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
38 | ||
9d8af78b BW |
39 | #ifdef CONFIG_HPET_EMULATE_RTC |
40 | #include <asm/hpet.h> | |
41 | #endif | |
42 | ||
7be2c7c9 DB |
43 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ |
44 | #include <asm-generic/rtc.h> | |
45 | ||
9d8af78b BW |
46 | #ifndef CONFIG_HPET_EMULATE_RTC |
47 | #define is_hpet_enabled() 0 | |
48 | #define hpet_set_alarm_time(hrs, min, sec) do { } while (0) | |
49 | #define hpet_set_periodic_freq(arg) 0 | |
50 | #define hpet_mask_rtc_irq_bit(arg) do { } while (0) | |
51 | #define hpet_set_rtc_irq_bit(arg) do { } while (0) | |
52 | #define hpet_rtc_timer_init() do { } while (0) | |
53 | #define hpet_register_irq_handler(h) 0 | |
54 | #define hpet_unregister_irq_handler(h) do { } while (0) | |
55 | extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); | |
56 | #endif | |
7be2c7c9 DB |
57 | |
58 | struct cmos_rtc { | |
59 | struct rtc_device *rtc; | |
60 | struct device *dev; | |
61 | int irq; | |
62 | struct resource *iomem; | |
63 | ||
87ac84f4 DB |
64 | void (*wake_on)(struct device *); |
65 | void (*wake_off)(struct device *); | |
66 | ||
67 | u8 enabled_wake; | |
7be2c7c9 DB |
68 | u8 suspend_ctrl; |
69 | ||
70 | /* newer hardware extends the original register set */ | |
71 | u8 day_alrm; | |
72 | u8 mon_alrm; | |
73 | u8 century; | |
74 | }; | |
75 | ||
76 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
77 | #define is_valid_irq(n) ((n) >= 0) | |
78 | ||
79 | static const char driver_name[] = "rtc_cmos"; | |
80 | ||
bcd9b89c DB |
81 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
82 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
83 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
84 | */ | |
85 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
86 | ||
87 | static inline int is_intr(u8 rtc_intr) | |
88 | { | |
89 | if (!(rtc_intr & RTC_IRQF)) | |
90 | return 0; | |
91 | return rtc_intr & RTC_IRQMASK; | |
92 | } | |
93 | ||
7be2c7c9 DB |
94 | /*----------------------------------------------------------------*/ |
95 | ||
96 | static int cmos_read_time(struct device *dev, struct rtc_time *t) | |
97 | { | |
98 | /* REVISIT: if the clock has a "century" register, use | |
99 | * that instead of the heuristic in get_rtc_time(). | |
100 | * That'll make Y3K compatility (year > 2070) easy! | |
101 | */ | |
102 | get_rtc_time(t); | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
107 | { | |
108 | /* REVISIT: set the "century" register if available | |
109 | * | |
110 | * NOTE: this ignores the issue whereby updating the seconds | |
111 | * takes effect exactly 500ms after we write the register. | |
112 | * (Also queueing and other delays before we get this far.) | |
113 | */ | |
114 | return set_rtc_time(t); | |
115 | } | |
116 | ||
117 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
118 | { | |
119 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
120 | unsigned char rtc_control; | |
121 | ||
122 | if (!is_valid_irq(cmos->irq)) | |
123 | return -EIO; | |
124 | ||
125 | /* Basic alarms only support hour, minute, and seconds fields. | |
126 | * Some also support day and month, for alarms up to a year in | |
127 | * the future. | |
128 | */ | |
129 | t->time.tm_mday = -1; | |
130 | t->time.tm_mon = -1; | |
131 | ||
132 | spin_lock_irq(&rtc_lock); | |
133 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
134 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
135 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
136 | ||
137 | if (cmos->day_alrm) { | |
615bb29c ML |
138 | /* ignore upper bits on readback per ACPI spec */ |
139 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
140 | if (!t->time.tm_mday) |
141 | t->time.tm_mday = -1; | |
142 | ||
143 | if (cmos->mon_alrm) { | |
144 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
145 | if (!t->time.tm_mon) | |
146 | t->time.tm_mon = -1; | |
147 | } | |
148 | } | |
149 | ||
150 | rtc_control = CMOS_READ(RTC_CONTROL); | |
151 | spin_unlock_irq(&rtc_lock); | |
152 | ||
153 | /* REVISIT this assumes PC style usage: always BCD */ | |
154 | ||
155 | if (((unsigned)t->time.tm_sec) < 0x60) | |
156 | t->time.tm_sec = BCD2BIN(t->time.tm_sec); | |
157 | else | |
158 | t->time.tm_sec = -1; | |
159 | if (((unsigned)t->time.tm_min) < 0x60) | |
160 | t->time.tm_min = BCD2BIN(t->time.tm_min); | |
161 | else | |
162 | t->time.tm_min = -1; | |
163 | if (((unsigned)t->time.tm_hour) < 0x24) | |
164 | t->time.tm_hour = BCD2BIN(t->time.tm_hour); | |
165 | else | |
166 | t->time.tm_hour = -1; | |
167 | ||
168 | if (cmos->day_alrm) { | |
169 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
170 | t->time.tm_mday = BCD2BIN(t->time.tm_mday); | |
171 | else | |
172 | t->time.tm_mday = -1; | |
173 | if (cmos->mon_alrm) { | |
174 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
175 | t->time.tm_mon = BCD2BIN(t->time.tm_mon) - 1; | |
176 | else | |
177 | t->time.tm_mon = -1; | |
178 | } | |
179 | } | |
180 | t->time.tm_year = -1; | |
181 | ||
182 | t->enabled = !!(rtc_control & RTC_AIE); | |
183 | t->pending = 0; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
189 | { | |
190 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
191 | unsigned char mon, mday, hrs, min, sec; | |
192 | unsigned char rtc_control, rtc_intr; | |
193 | ||
194 | if (!is_valid_irq(cmos->irq)) | |
195 | return -EIO; | |
196 | ||
197 | /* REVISIT this assumes PC style usage: always BCD */ | |
198 | ||
199 | /* Writing 0xff means "don't care" or "match all". */ | |
200 | ||
201 | mon = t->time.tm_mon; | |
202 | mon = (mon < 12) ? BIN2BCD(mon) : 0xff; | |
203 | mon++; | |
204 | ||
205 | mday = t->time.tm_mday; | |
206 | mday = (mday >= 1 && mday <= 31) ? BIN2BCD(mday) : 0xff; | |
207 | ||
208 | hrs = t->time.tm_hour; | |
209 | hrs = (hrs < 24) ? BIN2BCD(hrs) : 0xff; | |
210 | ||
211 | min = t->time.tm_min; | |
212 | min = (min < 60) ? BIN2BCD(min) : 0xff; | |
213 | ||
214 | sec = t->time.tm_sec; | |
215 | sec = (sec < 60) ? BIN2BCD(sec) : 0xff; | |
216 | ||
9d8af78b | 217 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); |
7be2c7c9 DB |
218 | spin_lock_irq(&rtc_lock); |
219 | ||
220 | /* next rtc irq must not be from previous alarm setting */ | |
221 | rtc_control = CMOS_READ(RTC_CONTROL); | |
222 | rtc_control &= ~RTC_AIE; | |
223 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
224 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
225 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
226 | if (is_intr(rtc_intr)) | |
ab6a2d70 | 227 | rtc_update_irq(cmos->rtc, 1, rtc_intr); |
7be2c7c9 DB |
228 | |
229 | /* update alarm */ | |
230 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
231 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
232 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
233 | ||
234 | /* the system may support an "enhanced" alarm */ | |
235 | if (cmos->day_alrm) { | |
236 | CMOS_WRITE(mday, cmos->day_alrm); | |
237 | if (cmos->mon_alrm) | |
238 | CMOS_WRITE(mon, cmos->mon_alrm); | |
239 | } | |
240 | ||
241 | if (t->enabled) { | |
242 | rtc_control |= RTC_AIE; | |
243 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
244 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
245 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
246 | if (is_intr(rtc_intr)) | |
ab6a2d70 | 247 | rtc_update_irq(cmos->rtc, 1, rtc_intr); |
7be2c7c9 DB |
248 | } |
249 | ||
250 | spin_unlock_irq(&rtc_lock); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
57deb526 | 255 | static int cmos_irq_set_freq(struct device *dev, int freq) |
7be2c7c9 DB |
256 | { |
257 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
258 | int f; | |
259 | unsigned long flags; | |
260 | ||
261 | if (!is_valid_irq(cmos->irq)) | |
262 | return -ENXIO; | |
263 | ||
264 | /* 0 = no irqs; 1 = 2^15 Hz ... 15 = 2^0 Hz */ | |
265 | f = ffs(freq); | |
97144c67 DB |
266 | if (f-- > 16) |
267 | return -EINVAL; | |
268 | f = 16 - f; | |
7be2c7c9 DB |
269 | |
270 | spin_lock_irqsave(&rtc_lock, flags); | |
9d8af78b BW |
271 | if (!hpet_set_periodic_freq(freq)) |
272 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
273 | spin_unlock_irqrestore(&rtc_lock, flags); |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
57deb526 AZ |
278 | static int cmos_irq_set_state(struct device *dev, int enabled) |
279 | { | |
280 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
281 | unsigned char rtc_control, rtc_intr; | |
282 | unsigned long flags; | |
283 | ||
284 | if (!is_valid_irq(cmos->irq)) | |
285 | return -ENXIO; | |
286 | ||
287 | spin_lock_irqsave(&rtc_lock, flags); | |
288 | rtc_control = CMOS_READ(RTC_CONTROL); | |
289 | ||
290 | if (enabled) | |
291 | rtc_control |= RTC_PIE; | |
292 | else | |
293 | rtc_control &= ~RTC_PIE; | |
294 | ||
295 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
296 | ||
297 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
298 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
299 | if (is_intr(rtc_intr)) | |
300 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
301 | ||
302 | spin_unlock_irqrestore(&rtc_lock, flags); | |
303 | return 0; | |
304 | } | |
305 | ||
7be2c7c9 DB |
306 | #if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_RTC_INTF_DEV_MODULE) |
307 | ||
308 | static int | |
309 | cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
310 | { | |
311 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
312 | unsigned char rtc_control, rtc_intr; | |
313 | unsigned long flags; | |
314 | ||
315 | switch (cmd) { | |
316 | case RTC_AIE_OFF: | |
317 | case RTC_AIE_ON: | |
318 | case RTC_UIE_OFF: | |
319 | case RTC_UIE_ON: | |
320 | case RTC_PIE_OFF: | |
321 | case RTC_PIE_ON: | |
322 | if (!is_valid_irq(cmos->irq)) | |
323 | return -EINVAL; | |
324 | break; | |
325 | default: | |
326 | return -ENOIOCTLCMD; | |
327 | } | |
328 | ||
329 | spin_lock_irqsave(&rtc_lock, flags); | |
330 | rtc_control = CMOS_READ(RTC_CONTROL); | |
331 | switch (cmd) { | |
332 | case RTC_AIE_OFF: /* alarm off */ | |
333 | rtc_control &= ~RTC_AIE; | |
9d8af78b | 334 | hpet_mask_rtc_irq_bit(RTC_AIE); |
7be2c7c9 DB |
335 | break; |
336 | case RTC_AIE_ON: /* alarm on */ | |
337 | rtc_control |= RTC_AIE; | |
9d8af78b | 338 | hpet_set_rtc_irq_bit(RTC_AIE); |
7be2c7c9 DB |
339 | break; |
340 | case RTC_UIE_OFF: /* update off */ | |
341 | rtc_control &= ~RTC_UIE; | |
9d8af78b | 342 | hpet_mask_rtc_irq_bit(RTC_UIE); |
7be2c7c9 DB |
343 | break; |
344 | case RTC_UIE_ON: /* update on */ | |
345 | rtc_control |= RTC_UIE; | |
9d8af78b | 346 | hpet_set_rtc_irq_bit(RTC_UIE); |
7be2c7c9 DB |
347 | break; |
348 | case RTC_PIE_OFF: /* periodic off */ | |
349 | rtc_control &= ~RTC_PIE; | |
9d8af78b | 350 | hpet_mask_rtc_irq_bit(RTC_PIE); |
7be2c7c9 DB |
351 | break; |
352 | case RTC_PIE_ON: /* periodic on */ | |
353 | rtc_control |= RTC_PIE; | |
9d8af78b | 354 | hpet_set_rtc_irq_bit(RTC_PIE); |
7be2c7c9 DB |
355 | break; |
356 | } | |
9d8af78b BW |
357 | if (!is_hpet_enabled()) |
358 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
359 | ||
7be2c7c9 | 360 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); |
bcd9b89c DB |
361 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
362 | if (is_intr(rtc_intr)) | |
ab6a2d70 | 363 | rtc_update_irq(cmos->rtc, 1, rtc_intr); |
9d8af78b | 364 | |
7be2c7c9 DB |
365 | spin_unlock_irqrestore(&rtc_lock, flags); |
366 | return 0; | |
367 | } | |
368 | ||
369 | #else | |
370 | #define cmos_rtc_ioctl NULL | |
371 | #endif | |
372 | ||
373 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
374 | ||
375 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
376 | { | |
377 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
378 | unsigned char rtc_control, valid; | |
379 | ||
380 | spin_lock_irq(&rtc_lock); | |
381 | rtc_control = CMOS_READ(RTC_CONTROL); | |
382 | valid = CMOS_READ(RTC_VALID); | |
383 | spin_unlock_irq(&rtc_lock); | |
384 | ||
385 | /* NOTE: at least ICH6 reports battery status using a different | |
386 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
387 | */ | |
388 | return seq_printf(seq, | |
389 | "periodic_IRQ\t: %s\n" | |
390 | "update_IRQ\t: %s\n" | |
c8626a1d | 391 | "HPET_emulated\t: %s\n" |
7be2c7c9 DB |
392 | // "square_wave\t: %s\n" |
393 | // "BCD\t\t: %s\n" | |
394 | "DST_enable\t: %s\n" | |
395 | "periodic_freq\t: %d\n" | |
396 | "batt_status\t: %s\n", | |
397 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
398 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 399 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 DB |
400 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
401 | // (rtc_control & RTC_DM_BINARY) ? "no" : "yes", | |
402 | (rtc_control & RTC_DST_EN) ? "yes" : "no", | |
403 | cmos->rtc->irq_freq, | |
404 | (valid & RTC_VRT) ? "okay" : "dead"); | |
405 | } | |
406 | ||
407 | #else | |
408 | #define cmos_procfs NULL | |
409 | #endif | |
410 | ||
411 | static const struct rtc_class_ops cmos_rtc_ops = { | |
412 | .ioctl = cmos_rtc_ioctl, | |
413 | .read_time = cmos_read_time, | |
414 | .set_time = cmos_set_time, | |
415 | .read_alarm = cmos_read_alarm, | |
416 | .set_alarm = cmos_set_alarm, | |
417 | .proc = cmos_procfs, | |
57deb526 AZ |
418 | .irq_set_freq = cmos_irq_set_freq, |
419 | .irq_set_state = cmos_irq_set_state, | |
7be2c7c9 DB |
420 | }; |
421 | ||
422 | /*----------------------------------------------------------------*/ | |
423 | ||
e07e232c DB |
424 | /* |
425 | * All these chips have at least 64 bytes of address space, shared by | |
426 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
427 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
428 | */ | |
429 | ||
430 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
431 | ||
432 | static ssize_t | |
433 | cmos_nvram_read(struct kobject *kobj, struct bin_attribute *attr, | |
434 | char *buf, loff_t off, size_t count) | |
435 | { | |
436 | int retval; | |
437 | ||
438 | if (unlikely(off >= attr->size)) | |
439 | return 0; | |
440 | if ((off + count) > attr->size) | |
441 | count = attr->size - off; | |
442 | ||
443 | spin_lock_irq(&rtc_lock); | |
444 | for (retval = 0, off += NVRAM_OFFSET; count--; retval++, off++) | |
445 | *buf++ = CMOS_READ(off); | |
446 | spin_unlock_irq(&rtc_lock); | |
447 | ||
448 | return retval; | |
449 | } | |
450 | ||
451 | static ssize_t | |
452 | cmos_nvram_write(struct kobject *kobj, struct bin_attribute *attr, | |
453 | char *buf, loff_t off, size_t count) | |
454 | { | |
455 | struct cmos_rtc *cmos; | |
456 | int retval; | |
457 | ||
458 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
459 | if (unlikely(off >= attr->size)) | |
460 | return -EFBIG; | |
461 | if ((off + count) > attr->size) | |
462 | count = attr->size - off; | |
463 | ||
464 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
465 | * checksum on part of the NVRAM data. That's currently ignored | |
466 | * here. If userspace is smart enough to know what fields of | |
467 | * NVRAM to update, updating checksums is also part of its job. | |
468 | */ | |
469 | spin_lock_irq(&rtc_lock); | |
470 | for (retval = 0, off += NVRAM_OFFSET; count--; retval++, off++) { | |
471 | /* don't trash RTC registers */ | |
472 | if (off == cmos->day_alrm | |
473 | || off == cmos->mon_alrm | |
474 | || off == cmos->century) | |
475 | buf++; | |
476 | else | |
477 | CMOS_WRITE(*buf++, off); | |
478 | } | |
479 | spin_unlock_irq(&rtc_lock); | |
480 | ||
481 | return retval; | |
482 | } | |
483 | ||
484 | static struct bin_attribute nvram = { | |
485 | .attr = { | |
486 | .name = "nvram", | |
487 | .mode = S_IRUGO | S_IWUSR, | |
488 | .owner = THIS_MODULE, | |
489 | }, | |
490 | ||
491 | .read = cmos_nvram_read, | |
492 | .write = cmos_nvram_write, | |
493 | /* size gets set up later */ | |
494 | }; | |
495 | ||
496 | /*----------------------------------------------------------------*/ | |
497 | ||
7be2c7c9 DB |
498 | static struct cmos_rtc cmos_rtc; |
499 | ||
500 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
501 | { | |
502 | u8 irqstat; | |
8a0bdfd7 | 503 | u8 rtc_control; |
7be2c7c9 DB |
504 | |
505 | spin_lock(&rtc_lock); | |
9d8af78b BW |
506 | /* |
507 | * In this case it is HPET RTC interrupt handler | |
508 | * calling us, with the interrupt information | |
509 | * passed as arg1, instead of irq. | |
510 | */ | |
511 | if (is_hpet_enabled()) | |
512 | irqstat = (unsigned long)irq & 0xF0; | |
513 | else { | |
514 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | |
515 | rtc_control = CMOS_READ(RTC_CONTROL); | |
516 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
517 | } | |
8a0bdfd7 DB |
518 | |
519 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
520 | * Similar code may be needed in system wakeup paths, in case the | |
521 | * alarm woke the system. | |
522 | */ | |
523 | if (irqstat & RTC_AIE) { | |
9d8af78b | 524 | rtc_control = CMOS_READ(RTC_CONTROL); |
8a0bdfd7 DB |
525 | rtc_control &= ~RTC_AIE; |
526 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
527 | CMOS_READ(RTC_INTR_FLAGS); | |
528 | } | |
7be2c7c9 DB |
529 | spin_unlock(&rtc_lock); |
530 | ||
bcd9b89c | 531 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
532 | rtc_update_irq(p, 1, irqstat); |
533 | return IRQ_HANDLED; | |
534 | } else | |
535 | return IRQ_NONE; | |
536 | } | |
537 | ||
41ac8df9 | 538 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
539 | #define INITSECTION |
540 | ||
541 | #else | |
7be2c7c9 DB |
542 | #define INITSECTION __init |
543 | #endif | |
544 | ||
545 | static int INITSECTION | |
546 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
547 | { | |
548 | struct cmos_rtc_board_info *info = dev->platform_data; | |
549 | int retval = 0; | |
550 | unsigned char rtc_control; | |
e07e232c | 551 | unsigned address_space; |
7be2c7c9 DB |
552 | |
553 | /* there can be only one ... */ | |
554 | if (cmos_rtc.dev) | |
555 | return -EBUSY; | |
556 | ||
557 | if (!ports) | |
558 | return -ENODEV; | |
559 | ||
05440dfc DB |
560 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
561 | * | |
562 | * REVISIT non-x86 systems may instead use memory space resources | |
563 | * (needing ioremap etc), not i/o space resources like this ... | |
564 | */ | |
565 | ports = request_region(ports->start, | |
566 | ports->end + 1 - ports->start, | |
567 | driver_name); | |
568 | if (!ports) { | |
569 | dev_dbg(dev, "i/o registers already in use\n"); | |
570 | return -EBUSY; | |
571 | } | |
572 | ||
7be2c7c9 DB |
573 | cmos_rtc.irq = rtc_irq; |
574 | cmos_rtc.iomem = ports; | |
575 | ||
e07e232c DB |
576 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
577 | * driver did, but don't reject unknown configs. Old hardware | |
578 | * won't address 128 bytes, and for now we ignore the way newer | |
579 | * chips can address 256 bytes (using two more i/o ports). | |
580 | */ | |
581 | #if defined(CONFIG_ATARI) | |
582 | address_space = 64; | |
583 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) | |
584 | address_space = 128; | |
585 | #else | |
586 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
587 | address_space = 128; | |
588 | #endif | |
589 | ||
87ac84f4 DB |
590 | /* For ACPI systems extension info comes from the FADT. On others, |
591 | * board specific setup provides it as appropriate. Systems where | |
592 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
593 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
594 | * |
595 | * Note that ACPI doesn't preclude putting these registers into | |
596 | * "extended" areas of the chip, including some that we won't yet | |
597 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
598 | */ |
599 | if (info) { | |
e07e232c DB |
600 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
601 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
602 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
603 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
604 | if (info->rtc_century && info->rtc_century < 128) | |
605 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
606 | |
607 | if (info->wake_on && info->wake_off) { | |
608 | cmos_rtc.wake_on = info->wake_on; | |
609 | cmos_rtc.wake_off = info->wake_off; | |
610 | } | |
7be2c7c9 DB |
611 | } |
612 | ||
613 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, | |
614 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
615 | if (IS_ERR(cmos_rtc.rtc)) { |
616 | retval = PTR_ERR(cmos_rtc.rtc); | |
617 | goto cleanup0; | |
618 | } | |
7be2c7c9 DB |
619 | |
620 | cmos_rtc.dev = dev; | |
621 | dev_set_drvdata(dev, &cmos_rtc); | |
cd966209 | 622 | rename_region(ports, cmos_rtc.rtc->dev.bus_id); |
7be2c7c9 DB |
623 | |
624 | spin_lock_irq(&rtc_lock); | |
625 | ||
626 | /* force periodic irq to CMOS reset default of 1024Hz; | |
627 | * | |
628 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
629 | * doesn't use 32KHz here ... for portability we might need to | |
630 | * do something about other clock frequencies. | |
631 | */ | |
7be2c7c9 | 632 | cmos_rtc.rtc->irq_freq = 1024; |
9d8af78b BW |
633 | if (!hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq)) |
634 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
635 | |
636 | /* disable irqs. | |
637 | * | |
638 | * NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
639 | * allegedly some older rtcs need that to handle irqs properly | |
640 | */ | |
641 | rtc_control = CMOS_READ(RTC_CONTROL); | |
642 | rtc_control &= ~(RTC_PIE | RTC_AIE | RTC_UIE); | |
643 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
644 | CMOS_READ(RTC_INTR_FLAGS); | |
645 | ||
646 | spin_unlock_irq(&rtc_lock); | |
647 | ||
648 | /* FIXME teach the alarm code how to handle binary mode; | |
649 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. | |
650 | */ | |
651 | if (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY))) { | |
652 | dev_dbg(dev, "only 24-hr BCD mode supported\n"); | |
653 | retval = -ENXIO; | |
654 | goto cleanup1; | |
655 | } | |
656 | ||
9d8af78b BW |
657 | if (is_valid_irq(rtc_irq)) { |
658 | irq_handler_t rtc_cmos_int_handler; | |
659 | ||
660 | if (is_hpet_enabled()) { | |
661 | int err; | |
662 | ||
663 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
664 | err = hpet_register_irq_handler(cmos_interrupt); | |
665 | if (err != 0) { | |
666 | printk(KERN_WARNING "hpet_register_irq_handler " | |
667 | " failed in rtc_init()."); | |
668 | goto cleanup1; | |
669 | } | |
670 | } else | |
671 | rtc_cmos_int_handler = cmos_interrupt; | |
672 | ||
673 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
674 | IRQF_DISABLED, cmos_rtc.rtc->dev.bus_id, | |
ab6a2d70 | 675 | cmos_rtc.rtc); |
9d8af78b BW |
676 | if (retval < 0) { |
677 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
678 | goto cleanup1; | |
679 | } | |
7be2c7c9 | 680 | } |
9d8af78b | 681 | hpet_rtc_timer_init(); |
7be2c7c9 | 682 | |
e07e232c DB |
683 | /* export at least the first block of NVRAM */ |
684 | nvram.size = address_space - NVRAM_OFFSET; | |
685 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
686 | if (retval < 0) { | |
687 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
688 | goto cleanup2; | |
689 | } | |
7be2c7c9 DB |
690 | |
691 | pr_info("%s: alarms up to one %s%s\n", | |
cd966209 | 692 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
693 | is_valid_irq(rtc_irq) |
694 | ? (cmos_rtc.mon_alrm | |
695 | ? "year" | |
696 | : (cmos_rtc.day_alrm | |
697 | ? "month" : "day")) | |
698 | : "no", | |
699 | cmos_rtc.century ? ", y3k" : "" | |
700 | ); | |
701 | ||
702 | return 0; | |
703 | ||
e07e232c DB |
704 | cleanup2: |
705 | if (is_valid_irq(rtc_irq)) | |
706 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 707 | cleanup1: |
05440dfc | 708 | cmos_rtc.dev = NULL; |
7be2c7c9 | 709 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc DB |
710 | cleanup0: |
711 | release_region(ports->start, ports->end + 1 - ports->start); | |
7be2c7c9 DB |
712 | return retval; |
713 | } | |
714 | ||
715 | static void cmos_do_shutdown(void) | |
716 | { | |
717 | unsigned char rtc_control; | |
718 | ||
719 | spin_lock_irq(&rtc_lock); | |
720 | rtc_control = CMOS_READ(RTC_CONTROL); | |
721 | rtc_control &= ~(RTC_PIE|RTC_AIE|RTC_UIE); | |
722 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
723 | CMOS_READ(RTC_INTR_FLAGS); | |
724 | spin_unlock_irq(&rtc_lock); | |
725 | } | |
726 | ||
727 | static void __exit cmos_do_remove(struct device *dev) | |
728 | { | |
729 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 730 | struct resource *ports; |
7be2c7c9 DB |
731 | |
732 | cmos_do_shutdown(); | |
733 | ||
e07e232c DB |
734 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
735 | ||
9d8af78b | 736 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 737 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
738 | hpet_unregister_irq_handler(cmos_interrupt); |
739 | } | |
7be2c7c9 | 740 | |
05440dfc DB |
741 | rtc_device_unregister(cmos->rtc); |
742 | cmos->rtc = NULL; | |
7be2c7c9 | 743 | |
05440dfc DB |
744 | ports = cmos->iomem; |
745 | release_region(ports->start, ports->end + 1 - ports->start); | |
746 | cmos->iomem = NULL; | |
747 | ||
748 | cmos->dev = NULL; | |
7be2c7c9 DB |
749 | dev_set_drvdata(dev, NULL); |
750 | } | |
751 | ||
752 | #ifdef CONFIG_PM | |
753 | ||
754 | static int cmos_suspend(struct device *dev, pm_message_t mesg) | |
755 | { | |
756 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
757 | int do_wake = device_may_wakeup(dev); | |
bcd9b89c | 758 | unsigned char tmp; |
7be2c7c9 DB |
759 | |
760 | /* only the alarm might be a wakeup event source */ | |
761 | spin_lock_irq(&rtc_lock); | |
762 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
763 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
bcd9b89c DB |
764 | unsigned char irqstat; |
765 | ||
7be2c7c9 DB |
766 | if (do_wake) |
767 | tmp &= ~(RTC_PIE|RTC_UIE); | |
768 | else | |
769 | tmp &= ~(RTC_PIE|RTC_AIE|RTC_UIE); | |
770 | CMOS_WRITE(tmp, RTC_CONTROL); | |
771 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
772 | irqstat &= (tmp & RTC_IRQMASK) | RTC_IRQF; |
773 | if (is_intr(irqstat)) | |
ab6a2d70 | 774 | rtc_update_irq(cmos->rtc, 1, irqstat); |
bcd9b89c | 775 | } |
7be2c7c9 DB |
776 | spin_unlock_irq(&rtc_lock); |
777 | ||
87ac84f4 DB |
778 | if (tmp & RTC_AIE) { |
779 | cmos->enabled_wake = 1; | |
780 | if (cmos->wake_on) | |
781 | cmos->wake_on(dev); | |
782 | else | |
783 | enable_irq_wake(cmos->irq); | |
784 | } | |
7be2c7c9 DB |
785 | |
786 | pr_debug("%s: suspend%s, ctrl %02x\n", | |
cd966209 | 787 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
788 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
789 | tmp); | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
794 | static int cmos_resume(struct device *dev) | |
795 | { | |
796 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
797 | unsigned char tmp = cmos->suspend_ctrl; | |
798 | ||
7be2c7c9 DB |
799 | /* re-enable any irqs previously active */ |
800 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
801 | ||
87ac84f4 DB |
802 | if (cmos->enabled_wake) { |
803 | if (cmos->wake_off) | |
804 | cmos->wake_off(dev); | |
805 | else | |
806 | disable_irq_wake(cmos->irq); | |
807 | cmos->enabled_wake = 0; | |
808 | } | |
7be2c7c9 DB |
809 | |
810 | spin_lock_irq(&rtc_lock); | |
811 | CMOS_WRITE(tmp, RTC_CONTROL); | |
812 | tmp = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
813 | tmp &= (cmos->suspend_ctrl & RTC_IRQMASK) | RTC_IRQF; |
814 | if (is_intr(tmp)) | |
ab6a2d70 | 815 | rtc_update_irq(cmos->rtc, 1, tmp); |
bcd9b89c | 816 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 DB |
817 | } |
818 | ||
819 | pr_debug("%s: resume, ctrl %02x\n", | |
cd966209 | 820 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
821 | cmos->suspend_ctrl); |
822 | ||
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | #else | |
828 | #define cmos_suspend NULL | |
829 | #define cmos_resume NULL | |
830 | #endif | |
831 | ||
832 | /*----------------------------------------------------------------*/ | |
833 | ||
e07e232c DB |
834 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
835 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
836 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
837 | * | |
838 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
839 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
840 | */ |
841 | ||
41ac8df9 | 842 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
843 | |
844 | #include <linux/pnp.h> | |
845 | ||
846 | static int __devinit | |
847 | cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) | |
848 | { | |
849 | /* REVISIT paranoia argues for a shutdown notifier, since PNP | |
850 | * drivers can't provide shutdown() methods to disable IRQs. | |
851 | * Or better yet, fix PNP to allow those methods... | |
852 | */ | |
6cd8fa87 MG |
853 | if (pnp_port_start(pnp,0) == 0x70 && !pnp_irq_valid(pnp,0)) |
854 | /* Some machines contain a PNP entry for the RTC, but | |
855 | * don't define the IRQ. It should always be safe to | |
856 | * hardcode it in these cases | |
857 | */ | |
858 | return cmos_do_probe(&pnp->dev, &pnp->res.port_resource[0], 8); | |
859 | else | |
860 | return cmos_do_probe(&pnp->dev, | |
861 | &pnp->res.port_resource[0], | |
862 | pnp->res.irq_resource[0].start); | |
7be2c7c9 DB |
863 | } |
864 | ||
865 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
866 | { | |
867 | cmos_do_remove(&pnp->dev); | |
868 | } | |
869 | ||
870 | #ifdef CONFIG_PM | |
871 | ||
872 | static int cmos_pnp_suspend(struct pnp_dev *pnp, pm_message_t mesg) | |
873 | { | |
874 | return cmos_suspend(&pnp->dev, mesg); | |
875 | } | |
876 | ||
877 | static int cmos_pnp_resume(struct pnp_dev *pnp) | |
878 | { | |
879 | return cmos_resume(&pnp->dev); | |
880 | } | |
881 | ||
882 | #else | |
883 | #define cmos_pnp_suspend NULL | |
884 | #define cmos_pnp_resume NULL | |
885 | #endif | |
886 | ||
887 | ||
888 | static const struct pnp_device_id rtc_ids[] = { | |
889 | { .id = "PNP0b00", }, | |
890 | { .id = "PNP0b01", }, | |
891 | { .id = "PNP0b02", }, | |
892 | { }, | |
893 | }; | |
894 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
895 | ||
896 | static struct pnp_driver cmos_pnp_driver = { | |
897 | .name = (char *) driver_name, | |
898 | .id_table = rtc_ids, | |
899 | .probe = cmos_pnp_probe, | |
900 | .remove = __exit_p(cmos_pnp_remove), | |
901 | ||
902 | /* flag ensures resume() gets called, and stops syslog spam */ | |
903 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
904 | .suspend = cmos_pnp_suspend, | |
905 | .resume = cmos_pnp_resume, | |
906 | }; | |
907 | ||
908 | static int __init cmos_init(void) | |
909 | { | |
910 | return pnp_register_driver(&cmos_pnp_driver); | |
911 | } | |
912 | module_init(cmos_init); | |
913 | ||
914 | static void __exit cmos_exit(void) | |
915 | { | |
916 | pnp_unregister_driver(&cmos_pnp_driver); | |
917 | } | |
918 | module_exit(cmos_exit); | |
919 | ||
41ac8df9 | 920 | #else /* no PNP */ |
7be2c7c9 DB |
921 | |
922 | /*----------------------------------------------------------------*/ | |
923 | ||
41ac8df9 | 924 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 925 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
926 | */ |
927 | ||
928 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
929 | { | |
930 | return cmos_do_probe(&pdev->dev, | |
931 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
932 | platform_get_irq(pdev, 0)); | |
933 | } | |
934 | ||
935 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
936 | { | |
937 | cmos_do_remove(&pdev->dev); | |
938 | return 0; | |
939 | } | |
940 | ||
941 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
942 | { | |
943 | cmos_do_shutdown(); | |
944 | } | |
945 | ||
946 | static struct platform_driver cmos_platform_driver = { | |
947 | .remove = __exit_p(cmos_platform_remove), | |
948 | .shutdown = cmos_platform_shutdown, | |
949 | .driver = { | |
950 | .name = (char *) driver_name, | |
951 | .suspend = cmos_suspend, | |
952 | .resume = cmos_resume, | |
953 | } | |
954 | }; | |
955 | ||
956 | static int __init cmos_init(void) | |
957 | { | |
958 | return platform_driver_probe(&cmos_platform_driver, | |
959 | cmos_platform_probe); | |
960 | } | |
961 | module_init(cmos_init); | |
962 | ||
963 | static void __exit cmos_exit(void) | |
964 | { | |
965 | platform_driver_unregister(&cmos_platform_driver); | |
966 | } | |
967 | module_exit(cmos_exit); | |
968 | ||
969 | ||
41ac8df9 | 970 | #endif /* !PNP */ |
7be2c7c9 DB |
971 | |
972 | MODULE_AUTHOR("David Brownell"); | |
973 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
974 | MODULE_LICENSE("GPL"); |