]>
Commit | Line | Data |
---|---|---|
739d340d PM |
1 | /* |
2 | * Dallas DS1302 RTC Support | |
3 | * | |
2bfc3305 AZ |
4 | * Copyright (C) 2002 David McCullough |
5 | * Copyright (C) 2003 - 2007 Paul Mundt | |
739d340d PM |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
2bfc3305 | 8 | * License version 2. See the file "COPYING" in the main directory of |
739d340d PM |
9 | * this archive for more details. |
10 | */ | |
2bfc3305 | 11 | |
d25a5ed3 | 12 | #include <linux/bcd.h> |
739d340d | 13 | #include <linux/init.h> |
d25a5ed3 | 14 | #include <linux/io.h> |
739d340d | 15 | #include <linux/kernel.h> |
d25a5ed3 SY |
16 | #include <linux/module.h> |
17 | #include <linux/of.h> | |
739d340d | 18 | #include <linux/rtc.h> |
d25a5ed3 | 19 | #include <linux/spi/spi.h> |
739d340d PM |
20 | |
21 | #define DRV_NAME "rtc-ds1302" | |
739d340d PM |
22 | |
23 | #define RTC_CMD_READ 0x81 /* Read command */ | |
24 | #define RTC_CMD_WRITE 0x80 /* Write command */ | |
25 | ||
dfc657b1 SY |
26 | #define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */ |
27 | #define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */ | |
28 | ||
739d340d PM |
29 | #define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */ |
30 | #define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */ | |
d25a5ed3 SY |
31 | #define RTC_CLCK_BURST 0x1F /* Address of clock burst */ |
32 | #define RTC_CLCK_LEN 0x08 /* Size of clock burst */ | |
dfc657b1 | 33 | #define RTC_ADDR_CTRL 0x07 /* Address of control register */ |
739d340d PM |
34 | #define RTC_ADDR_YEAR 0x06 /* Address of year register */ |
35 | #define RTC_ADDR_DAY 0x05 /* Address of day of week register */ | |
36 | #define RTC_ADDR_MON 0x04 /* Address of month register */ | |
37 | #define RTC_ADDR_DATE 0x03 /* Address of day of month register */ | |
38 | #define RTC_ADDR_HOUR 0x02 /* Address of hour register */ | |
39 | #define RTC_ADDR_MIN 0x01 /* Address of minute register */ | |
40 | #define RTC_ADDR_SEC 0x00 /* Address of second register */ | |
41 | ||
d25a5ed3 | 42 | static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time) |
72cc8e51 | 43 | { |
d25a5ed3 SY |
44 | struct spi_device *spi = dev_get_drvdata(dev); |
45 | u8 buf[1 + RTC_CLCK_LEN]; | |
46 | u8 *bp = buf; | |
47 | int status; | |
48 | ||
49 | /* Enable writing */ | |
50 | bp = buf; | |
51 | *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE; | |
52 | *bp++ = RTC_CMD_WRITE_ENABLE; | |
53 | ||
54 | status = spi_write_then_read(spi, buf, 2, | |
55 | NULL, 0); | |
bc83a141 | 56 | if (status) |
d25a5ed3 SY |
57 | return status; |
58 | ||
59 | /* Write registers starting at the first time/date address. */ | |
60 | bp = buf; | |
61 | *bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE; | |
62 | ||
63 | *bp++ = bin2bcd(time->tm_sec); | |
64 | *bp++ = bin2bcd(time->tm_min); | |
65 | *bp++ = bin2bcd(time->tm_hour); | |
66 | *bp++ = bin2bcd(time->tm_mday); | |
67 | *bp++ = bin2bcd(time->tm_mon + 1); | |
ef50f86e | 68 | *bp++ = time->tm_wday + 1; |
d25a5ed3 SY |
69 | *bp++ = bin2bcd(time->tm_year % 100); |
70 | *bp++ = RTC_CMD_WRITE_DISABLE; | |
71 | ||
72 | /* use write-then-read since dma from stack is nonportable */ | |
73 | return spi_write_then_read(spi, buf, sizeof(buf), | |
74 | NULL, 0); | |
72cc8e51 MZ |
75 | } |
76 | ||
d25a5ed3 | 77 | static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time) |
72cc8e51 | 78 | { |
d25a5ed3 SY |
79 | struct spi_device *spi = dev_get_drvdata(dev); |
80 | u8 addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ; | |
81 | u8 buf[RTC_CLCK_LEN - 1]; | |
82 | int status; | |
83 | ||
84 | /* Use write-then-read to get all the date/time registers | |
85 | * since dma from stack is nonportable | |
86 | */ | |
87 | status = spi_write_then_read(spi, &addr, sizeof(addr), | |
88 | buf, sizeof(buf)); | |
89 | if (status < 0) | |
90 | return status; | |
91 | ||
92 | /* Decode the registers */ | |
93 | time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]); | |
94 | time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]); | |
95 | time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]); | |
96 | time->tm_wday = buf[RTC_ADDR_DAY] - 1; | |
97 | time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]); | |
98 | time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1; | |
99 | time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100; | |
100 | ||
101 | /* Time may not be set */ | |
102 | return rtc_valid_tm(time); | |
72cc8e51 MZ |
103 | } |
104 | ||
34c7b3ac | 105 | static const struct rtc_class_ops ds1302_rtc_ops = { |
d25a5ed3 SY |
106 | .read_time = ds1302_rtc_get_time, |
107 | .set_time = ds1302_rtc_set_time, | |
108 | }; | |
739d340d | 109 | |
d25a5ed3 | 110 | static int ds1302_probe(struct spi_device *spi) |
739d340d | 111 | { |
d25a5ed3 SY |
112 | struct rtc_device *rtc; |
113 | u8 addr; | |
114 | u8 buf[4]; | |
115 | u8 *bp = buf; | |
116 | int status; | |
117 | ||
118 | /* Sanity check board setup data. This may be hooked up | |
119 | * in 3wire mode, but we don't care. Note that unless | |
120 | * there's an inverter in place, this needs SPI_CS_HIGH! | |
121 | */ | |
122 | if (spi->bits_per_word && (spi->bits_per_word != 8)) { | |
123 | dev_err(&spi->dev, "bad word length\n"); | |
124 | return -EINVAL; | |
125 | } else if (spi->max_speed_hz > 2000000) { | |
126 | dev_err(&spi->dev, "speed is too high\n"); | |
127 | return -EINVAL; | |
128 | } else if (spi->mode & SPI_CPHA) { | |
129 | dev_err(&spi->dev, "bad mode\n"); | |
130 | return -EINVAL; | |
739d340d | 131 | } |
72cc8e51 | 132 | |
d25a5ed3 SY |
133 | addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ; |
134 | status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1); | |
135 | if (status < 0) { | |
136 | dev_err(&spi->dev, "control register read error %d\n", | |
137 | status); | |
138 | return status; | |
739d340d PM |
139 | } |
140 | ||
d25a5ed3 SY |
141 | if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) { |
142 | status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1); | |
143 | if (status < 0) { | |
144 | dev_err(&spi->dev, "control register read error %d\n", | |
145 | status); | |
146 | return status; | |
147 | } | |
148 | ||
149 | if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) { | |
150 | dev_err(&spi->dev, "junk in control register\n"); | |
151 | return -ENODEV; | |
152 | } | |
153 | } | |
154 | if (buf[0] == 0) { | |
155 | bp = buf; | |
156 | *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE; | |
157 | *bp++ = RTC_CMD_WRITE_DISABLE; | |
158 | ||
159 | status = spi_write_then_read(spi, buf, 2, NULL, 0); | |
160 | if (status < 0) { | |
161 | dev_err(&spi->dev, "control register write error %d\n", | |
162 | status); | |
163 | return status; | |
164 | } | |
165 | ||
166 | addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ; | |
167 | status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1); | |
168 | if (status < 0) { | |
169 | dev_err(&spi->dev, | |
170 | "error %d reading control register\n", | |
171 | status); | |
172 | return status; | |
173 | } | |
174 | ||
175 | if (buf[0] != RTC_CMD_WRITE_DISABLE) { | |
176 | dev_err(&spi->dev, "failed to detect chip\n"); | |
177 | return -ENODEV; | |
178 | } | |
179 | } | |
739d340d | 180 | |
d25a5ed3 | 181 | spi_set_drvdata(spi, spi); |
739d340d | 182 | |
d25a5ed3 SY |
183 | rtc = devm_rtc_device_register(&spi->dev, "ds1302", |
184 | &ds1302_rtc_ops, THIS_MODULE); | |
185 | if (IS_ERR(rtc)) { | |
186 | status = PTR_ERR(rtc); | |
187 | dev_err(&spi->dev, "error %d registering rtc\n", status); | |
188 | return status; | |
189 | } | |
dfc657b1 | 190 | |
739d340d PM |
191 | return 0; |
192 | } | |
193 | ||
d25a5ed3 | 194 | static int ds1302_remove(struct spi_device *spi) |
739d340d | 195 | { |
d25a5ed3 SY |
196 | spi_set_drvdata(spi, NULL); |
197 | return 0; | |
739d340d PM |
198 | } |
199 | ||
d25a5ed3 SY |
200 | #ifdef CONFIG_OF |
201 | static const struct of_device_id ds1302_dt_ids[] = { | |
202 | { .compatible = "maxim,ds1302", }, | |
203 | { /* sentinel */ } | |
739d340d | 204 | }; |
d25a5ed3 SY |
205 | MODULE_DEVICE_TABLE(of, ds1302_dt_ids); |
206 | #endif | |
739d340d | 207 | |
d25a5ed3 SY |
208 | static struct spi_driver ds1302_driver = { |
209 | .driver.name = "rtc-ds1302", | |
210 | .driver.of_match_table = of_match_ptr(ds1302_dt_ids), | |
211 | .probe = ds1302_probe, | |
212 | .remove = ds1302_remove, | |
739d340d PM |
213 | }; |
214 | ||
d25a5ed3 | 215 | module_spi_driver(ds1302_driver); |
739d340d PM |
216 | |
217 | MODULE_DESCRIPTION("Dallas DS1302 RTC driver"); | |
739d340d PM |
218 | MODULE_AUTHOR("Paul Mundt, David McCullough"); |
219 | MODULE_LICENSE("GPL v2"); |