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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
53e84b67 DB |
2 | /* |
3 | * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips | |
4 | * | |
5 | * Copyright (C) 2008 David Brownell | |
53e84b67 DB |
6 | */ |
7 | #include <linux/kernel.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/bcd.h> | |
5a0e3ad6 | 10 | #include <linux/slab.h> |
53e84b67 DB |
11 | #include <linux/rtc.h> |
12 | #include <linux/workqueue.h> | |
13 | ||
14 | #include <linux/spi/spi.h> | |
15 | #include <linux/spi/ds1305.h> | |
2113852b | 16 | #include <linux/module.h> |
53e84b67 DB |
17 | |
18 | ||
19 | /* | |
20 | * Registers ... mask DS1305_WRITE into register address to write, | |
21 | * otherwise you're reading it. All non-bitmask values are BCD. | |
22 | */ | |
23 | #define DS1305_WRITE 0x80 | |
24 | ||
25 | ||
26 | /* RTC date/time ... the main special cases are that we: | |
27 | * - Need fancy "hours" encoding in 12hour mode | |
28 | * - Don't rely on the "day-of-week" field (or tm_wday) | |
29 | * - Are a 21st-century clock (2000 <= year < 2100) | |
30 | */ | |
31 | #define DS1305_RTC_LEN 7 /* bytes for RTC regs */ | |
32 | ||
33 | #define DS1305_SEC 0x00 /* register addresses */ | |
34 | #define DS1305_MIN 0x01 | |
35 | #define DS1305_HOUR 0x02 | |
36 | # define DS1305_HR_12 0x40 /* set == 12 hr mode */ | |
37 | # define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */ | |
38 | #define DS1305_WDAY 0x03 | |
39 | #define DS1305_MDAY 0x04 | |
40 | #define DS1305_MON 0x05 | |
41 | #define DS1305_YEAR 0x06 | |
42 | ||
43 | ||
44 | /* The two alarms have only sec/min/hour/wday fields (ALM_LEN). | |
45 | * DS1305_ALM_DISABLE disables a match field (some combos are bad). | |
46 | * | |
47 | * NOTE that since we don't use WDAY, we limit ourselves to alarms | |
48 | * only one day into the future (vs potentially up to a week). | |
49 | * | |
50 | * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we | |
51 | * don't currently support them. We'd either need to do it only when | |
52 | * no alarm is pending (not the standard model), or to use the second | |
53 | * alarm (implying that this is a DS1305 not DS1306, *and* that either | |
54 | * it's wired up a second IRQ we know, or that INTCN is set) | |
55 | */ | |
56 | #define DS1305_ALM_LEN 4 /* bytes for ALM regs */ | |
57 | #define DS1305_ALM_DISABLE 0x80 | |
58 | ||
59 | #define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */ | |
60 | #define DS1305_ALM1(r) (0x0b + (r)) | |
61 | ||
62 | ||
63 | /* three control registers */ | |
64 | #define DS1305_CONTROL_LEN 3 /* bytes of control regs */ | |
65 | ||
66 | #define DS1305_CONTROL 0x0f /* register addresses */ | |
67 | # define DS1305_nEOSC 0x80 /* low enables oscillator */ | |
68 | # define DS1305_WP 0x40 /* write protect */ | |
69 | # define DS1305_INTCN 0x04 /* clear == only int0 used */ | |
70 | # define DS1306_1HZ 0x04 /* enable 1Hz output */ | |
71 | # define DS1305_AEI1 0x02 /* enable ALM1 IRQ */ | |
72 | # define DS1305_AEI0 0x01 /* enable ALM0 IRQ */ | |
73 | #define DS1305_STATUS 0x10 | |
74 | /* status has just AEIx bits, mirrored as IRQFx */ | |
75 | #define DS1305_TRICKLE 0x11 | |
76 | /* trickle bits are defined in <linux/spi/ds1305.h> */ | |
77 | ||
78 | /* a bunch of NVRAM */ | |
79 | #define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */ | |
80 | ||
81 | #define DS1305_NVRAM 0x20 /* register addresses */ | |
82 | ||
83 | ||
84 | struct ds1305 { | |
85 | struct spi_device *spi; | |
86 | struct rtc_device *rtc; | |
87 | ||
88 | struct work_struct work; | |
89 | ||
90 | unsigned long flags; | |
91 | #define FLAG_EXITING 0 | |
92 | ||
93 | bool hr12; | |
94 | u8 ctrl[DS1305_CONTROL_LEN]; | |
95 | }; | |
96 | ||
97 | ||
98 | /*----------------------------------------------------------------------*/ | |
99 | ||
100 | /* | |
101 | * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux | |
102 | * software (like a bootloader) which may require it. | |
103 | */ | |
104 | ||
105 | static unsigned bcd2hour(u8 bcd) | |
106 | { | |
107 | if (bcd & DS1305_HR_12) { | |
108 | unsigned hour = 0; | |
109 | ||
110 | bcd &= ~DS1305_HR_12; | |
111 | if (bcd & DS1305_HR_PM) { | |
112 | hour = 12; | |
113 | bcd &= ~DS1305_HR_PM; | |
114 | } | |
fe20ba70 | 115 | hour += bcd2bin(bcd); |
53e84b67 DB |
116 | return hour - 1; |
117 | } | |
fe20ba70 | 118 | return bcd2bin(bcd); |
53e84b67 DB |
119 | } |
120 | ||
121 | static u8 hour2bcd(bool hr12, int hour) | |
122 | { | |
123 | if (hr12) { | |
124 | hour++; | |
125 | if (hour <= 12) | |
fe20ba70 | 126 | return DS1305_HR_12 | bin2bcd(hour); |
53e84b67 | 127 | hour -= 12; |
fe20ba70 | 128 | return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour); |
53e84b67 | 129 | } |
fe20ba70 | 130 | return bin2bcd(hour); |
53e84b67 DB |
131 | } |
132 | ||
133 | /*----------------------------------------------------------------------*/ | |
134 | ||
135 | /* | |
136 | * Interface to RTC framework | |
137 | */ | |
138 | ||
16380c15 | 139 | static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled) |
53e84b67 DB |
140 | { |
141 | struct ds1305 *ds1305 = dev_get_drvdata(dev); | |
142 | u8 buf[2]; | |
16380c15 | 143 | long err = -EINVAL; |
53e84b67 DB |
144 | |
145 | buf[0] = DS1305_WRITE | DS1305_CONTROL; | |
146 | buf[1] = ds1305->ctrl[0]; | |
147 | ||
16380c15 | 148 | if (enabled) { |
53e84b67 DB |
149 | if (ds1305->ctrl[0] & DS1305_AEI0) |
150 | goto done; | |
151 | buf[1] |= DS1305_AEI0; | |
16380c15 JS |
152 | } else { |
153 | if (!(buf[1] & DS1305_AEI0)) | |
154 | goto done; | |
155 | buf[1] &= ~DS1305_AEI0; | |
53e84b67 | 156 | } |
465008fa | 157 | err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0); |
16380c15 JS |
158 | if (err >= 0) |
159 | ds1305->ctrl[0] = buf[1]; | |
53e84b67 | 160 | done: |
16380c15 JS |
161 | return err; |
162 | ||
53e84b67 DB |
163 | } |
164 | ||
53e84b67 DB |
165 | |
166 | /* | |
167 | * Get/set of date and time is pretty normal. | |
168 | */ | |
169 | ||
170 | static int ds1305_get_time(struct device *dev, struct rtc_time *time) | |
171 | { | |
172 | struct ds1305 *ds1305 = dev_get_drvdata(dev); | |
173 | u8 addr = DS1305_SEC; | |
174 | u8 buf[DS1305_RTC_LEN]; | |
175 | int status; | |
176 | ||
177 | /* Use write-then-read to get all the date/time registers | |
178 | * since dma from stack is nonportable | |
179 | */ | |
465008fa SK |
180 | status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr), |
181 | buf, sizeof(buf)); | |
53e84b67 DB |
182 | if (status < 0) |
183 | return status; | |
184 | ||
ff67abd2 | 185 | dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]); |
53e84b67 DB |
186 | |
187 | /* Decode the registers */ | |
fe20ba70 AB |
188 | time->tm_sec = bcd2bin(buf[DS1305_SEC]); |
189 | time->tm_min = bcd2bin(buf[DS1305_MIN]); | |
53e84b67 DB |
190 | time->tm_hour = bcd2hour(buf[DS1305_HOUR]); |
191 | time->tm_wday = buf[DS1305_WDAY] - 1; | |
fe20ba70 AB |
192 | time->tm_mday = bcd2bin(buf[DS1305_MDAY]); |
193 | time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1; | |
194 | time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100; | |
53e84b67 DB |
195 | |
196 | dev_vdbg(dev, "%s secs=%d, mins=%d, " | |
197 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
198 | "read", time->tm_sec, time->tm_min, | |
199 | time->tm_hour, time->tm_mday, | |
200 | time->tm_mon, time->tm_year, time->tm_wday); | |
201 | ||
22652ba7 | 202 | return 0; |
53e84b67 DB |
203 | } |
204 | ||
205 | static int ds1305_set_time(struct device *dev, struct rtc_time *time) | |
206 | { | |
207 | struct ds1305 *ds1305 = dev_get_drvdata(dev); | |
208 | u8 buf[1 + DS1305_RTC_LEN]; | |
209 | u8 *bp = buf; | |
210 | ||
211 | dev_vdbg(dev, "%s secs=%d, mins=%d, " | |
212 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
213 | "write", time->tm_sec, time->tm_min, | |
214 | time->tm_hour, time->tm_mday, | |
215 | time->tm_mon, time->tm_year, time->tm_wday); | |
216 | ||
217 | /* Write registers starting at the first time/date address. */ | |
218 | *bp++ = DS1305_WRITE | DS1305_SEC; | |
219 | ||
fe20ba70 AB |
220 | *bp++ = bin2bcd(time->tm_sec); |
221 | *bp++ = bin2bcd(time->tm_min); | |
53e84b67 DB |
222 | *bp++ = hour2bcd(ds1305->hr12, time->tm_hour); |
223 | *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1; | |
fe20ba70 AB |
224 | *bp++ = bin2bcd(time->tm_mday); |
225 | *bp++ = bin2bcd(time->tm_mon + 1); | |
226 | *bp++ = bin2bcd(time->tm_year - 100); | |
53e84b67 | 227 | |
ff67abd2 | 228 | dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]); |
53e84b67 DB |
229 | |
230 | /* use write-then-read since dma from stack is nonportable */ | |
465008fa | 231 | return spi_write_then_read(ds1305->spi, buf, sizeof(buf), |
53e84b67 DB |
232 | NULL, 0); |
233 | } | |
234 | ||
235 | /* | |
236 | * Get/set of alarm is a bit funky: | |
237 | * | |
238 | * - First there's the inherent raciness of getting the (partitioned) | |
239 | * status of an alarm that could trigger while we're reading parts | |
240 | * of that status. | |
241 | * | |
242 | * - Second there's its limited range (we could increase it a bit by | |
243 | * relying on WDAY), which means it will easily roll over. | |
244 | * | |
245 | * - Third there's the choice of two alarms and alarm signals. | |
246 | * Here we use ALM0 and expect that nINT0 (open drain) is used; | |
247 | * that's the only real option for DS1306 runtime alarms, and is | |
248 | * natural on DS1305. | |
249 | * | |
250 | * - Fourth, there's also ALM1, and a second interrupt signal: | |
251 | * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0; | |
252 | * + On DS1306 ALM1 only uses INT1 (an active high pulse) | |
253 | * and it won't work when VCC1 is active. | |
254 | * | |
255 | * So to be most general, we should probably set both alarms to the | |
256 | * same value, letting ALM1 be the wakeup event source on DS1306 | |
257 | * and handling several wiring options on DS1305. | |
258 | * | |
259 | * - Fifth, we support the polled mode (as well as possible; why not?) | |
260 | * even when no interrupt line is wired to an IRQ. | |
261 | */ | |
262 | ||
263 | /* | |
264 | * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl) | |
265 | */ | |
266 | static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
267 | { | |
268 | struct ds1305 *ds1305 = dev_get_drvdata(dev); | |
269 | struct spi_device *spi = ds1305->spi; | |
270 | u8 addr; | |
271 | int status; | |
272 | u8 buf[DS1305_ALM_LEN]; | |
273 | ||
274 | /* Refresh control register cache BEFORE reading ALM0 registers, | |
275 | * since reading alarm registers acks any pending IRQ. That | |
276 | * makes returning "pending" status a bit of a lie, but that bit | |
277 | * of EFI status is at best fragile anyway (given IRQ handlers). | |
278 | */ | |
279 | addr = DS1305_CONTROL; | |
465008fa SK |
280 | status = spi_write_then_read(spi, &addr, sizeof(addr), |
281 | ds1305->ctrl, sizeof(ds1305->ctrl)); | |
53e84b67 DB |
282 | if (status < 0) |
283 | return status; | |
284 | ||
285 | alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0); | |
286 | alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0); | |
287 | ||
288 | /* get and check ALM0 registers */ | |
289 | addr = DS1305_ALM0(DS1305_SEC); | |
465008fa SK |
290 | status = spi_write_then_read(spi, &addr, sizeof(addr), |
291 | buf, sizeof(buf)); | |
53e84b67 DB |
292 | if (status < 0) |
293 | return status; | |
294 | ||
295 | dev_vdbg(dev, "%s: %02x %02x %02x %02x\n", | |
296 | "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN], | |
297 | buf[DS1305_HOUR], buf[DS1305_WDAY]); | |
298 | ||
299 | if ((DS1305_ALM_DISABLE & buf[DS1305_SEC]) | |
300 | || (DS1305_ALM_DISABLE & buf[DS1305_MIN]) | |
301 | || (DS1305_ALM_DISABLE & buf[DS1305_HOUR])) | |
302 | return -EIO; | |
303 | ||
304 | /* Stuff these values into alm->time and let RTC framework code | |
305 | * fill in the rest ... and also handle rollover to tomorrow when | |
306 | * that's needed. | |
307 | */ | |
fe20ba70 AB |
308 | alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]); |
309 | alm->time.tm_min = bcd2bin(buf[DS1305_MIN]); | |
53e84b67 | 310 | alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]); |
53e84b67 DB |
311 | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /* | |
316 | * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl) | |
317 | */ | |
318 | static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
319 | { | |
320 | struct ds1305 *ds1305 = dev_get_drvdata(dev); | |
321 | struct spi_device *spi = ds1305->spi; | |
322 | unsigned long now, later; | |
323 | struct rtc_time tm; | |
324 | int status; | |
325 | u8 buf[1 + DS1305_ALM_LEN]; | |
326 | ||
327 | /* convert desired alarm to time_t */ | |
f2adcb9c | 328 | later = rtc_tm_to_time64(&alm->time); |
53e84b67 DB |
329 | |
330 | /* Read current time as time_t */ | |
331 | status = ds1305_get_time(dev, &tm); | |
332 | if (status < 0) | |
333 | return status; | |
f2adcb9c | 334 | now = rtc_tm_to_time64(&tm); |
53e84b67 DB |
335 | |
336 | /* make sure alarm fires within the next 24 hours */ | |
337 | if (later <= now) | |
338 | return -EINVAL; | |
339 | if ((later - now) > 24 * 60 * 60) | |
340 | return -EDOM; | |
341 | ||
342 | /* disable alarm if needed */ | |
343 | if (ds1305->ctrl[0] & DS1305_AEI0) { | |
344 | ds1305->ctrl[0] &= ~DS1305_AEI0; | |
345 | ||
346 | buf[0] = DS1305_WRITE | DS1305_CONTROL; | |
347 | buf[1] = ds1305->ctrl[0]; | |
348 | status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0); | |
349 | if (status < 0) | |
350 | return status; | |
351 | } | |
352 | ||
353 | /* write alarm */ | |
354 | buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC); | |
fe20ba70 AB |
355 | buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec); |
356 | buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min); | |
53e84b67 DB |
357 | buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour); |
358 | buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE; | |
359 | ||
360 | dev_dbg(dev, "%s: %02x %02x %02x %02x\n", | |
361 | "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN], | |
362 | buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]); | |
363 | ||
465008fa | 364 | status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); |
53e84b67 DB |
365 | if (status < 0) |
366 | return status; | |
367 | ||
368 | /* enable alarm if requested */ | |
369 | if (alm->enabled) { | |
370 | ds1305->ctrl[0] |= DS1305_AEI0; | |
371 | ||
372 | buf[0] = DS1305_WRITE | DS1305_CONTROL; | |
373 | buf[1] = ds1305->ctrl[0]; | |
374 | status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0); | |
375 | } | |
376 | ||
377 | return status; | |
378 | } | |
379 | ||
380 | #ifdef CONFIG_PROC_FS | |
381 | ||
382 | static int ds1305_proc(struct device *dev, struct seq_file *seq) | |
383 | { | |
384 | struct ds1305 *ds1305 = dev_get_drvdata(dev); | |
385 | char *diodes = "no"; | |
386 | char *resistors = ""; | |
387 | ||
388 | /* ctrl[2] is treated as read-only; no locking needed */ | |
389 | if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) { | |
390 | switch (ds1305->ctrl[2] & 0x0c) { | |
391 | case DS1305_TRICKLE_DS2: | |
392 | diodes = "2 diodes, "; | |
393 | break; | |
394 | case DS1305_TRICKLE_DS1: | |
395 | diodes = "1 diode, "; | |
396 | break; | |
397 | default: | |
398 | goto done; | |
399 | } | |
400 | switch (ds1305->ctrl[2] & 0x03) { | |
401 | case DS1305_TRICKLE_2K: | |
402 | resistors = "2k Ohm"; | |
403 | break; | |
404 | case DS1305_TRICKLE_4K: | |
405 | resistors = "4k Ohm"; | |
406 | break; | |
407 | case DS1305_TRICKLE_8K: | |
408 | resistors = "8k Ohm"; | |
409 | break; | |
410 | default: | |
411 | diodes = "no"; | |
412 | break; | |
413 | } | |
414 | } | |
415 | ||
416 | done: | |
4395eb1f JP |
417 | seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors); |
418 | ||
419 | return 0; | |
53e84b67 DB |
420 | } |
421 | ||
422 | #else | |
423 | #define ds1305_proc NULL | |
424 | #endif | |
425 | ||
426 | static const struct rtc_class_ops ds1305_ops = { | |
53e84b67 DB |
427 | .read_time = ds1305_get_time, |
428 | .set_time = ds1305_set_time, | |
429 | .read_alarm = ds1305_get_alarm, | |
430 | .set_alarm = ds1305_set_alarm, | |
431 | .proc = ds1305_proc, | |
16380c15 | 432 | .alarm_irq_enable = ds1305_alarm_irq_enable, |
53e84b67 DB |
433 | }; |
434 | ||
435 | static void ds1305_work(struct work_struct *work) | |
436 | { | |
437 | struct ds1305 *ds1305 = container_of(work, struct ds1305, work); | |
438 | struct mutex *lock = &ds1305->rtc->ops_lock; | |
439 | struct spi_device *spi = ds1305->spi; | |
440 | u8 buf[3]; | |
441 | int status; | |
442 | ||
443 | /* lock to protect ds1305->ctrl */ | |
444 | mutex_lock(lock); | |
445 | ||
446 | /* Disable the IRQ, and clear its status ... for now, we "know" | |
447 | * that if more than one alarm is active, they're in sync. | |
448 | * Note that reading ALM data registers also clears IRQ status. | |
449 | */ | |
450 | ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0); | |
451 | ds1305->ctrl[1] = 0; | |
452 | ||
453 | buf[0] = DS1305_WRITE | DS1305_CONTROL; | |
454 | buf[1] = ds1305->ctrl[0]; | |
455 | buf[2] = 0; | |
456 | ||
465008fa | 457 | status = spi_write_then_read(spi, buf, sizeof(buf), |
53e84b67 DB |
458 | NULL, 0); |
459 | if (status < 0) | |
460 | dev_dbg(&spi->dev, "clear irq --> %d\n", status); | |
461 | ||
462 | mutex_unlock(lock); | |
463 | ||
464 | if (!test_bit(FLAG_EXITING, &ds1305->flags)) | |
465 | enable_irq(spi->irq); | |
466 | ||
53e84b67 | 467 | rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF); |
53e84b67 DB |
468 | } |
469 | ||
470 | /* | |
471 | * This "real" IRQ handler hands off to a workqueue mostly to allow | |
472 | * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async | |
473 | * I/O requests in IRQ context (to clear the IRQ status). | |
474 | */ | |
475 | static irqreturn_t ds1305_irq(int irq, void *p) | |
476 | { | |
477 | struct ds1305 *ds1305 = p; | |
478 | ||
479 | disable_irq(irq); | |
480 | schedule_work(&ds1305->work); | |
481 | return IRQ_HANDLED; | |
482 | } | |
483 | ||
484 | /*----------------------------------------------------------------------*/ | |
485 | ||
486 | /* | |
487 | * Interface for NVRAM | |
488 | */ | |
489 | ||
490 | static void msg_init(struct spi_message *m, struct spi_transfer *x, | |
491 | u8 *addr, size_t count, char *tx, char *rx) | |
492 | { | |
493 | spi_message_init(m); | |
494 | memset(x, 0, 2 * sizeof(*x)); | |
495 | ||
496 | x->tx_buf = addr; | |
497 | x->len = 1; | |
498 | spi_message_add_tail(x, m); | |
499 | ||
500 | x++; | |
501 | ||
502 | x->tx_buf = tx; | |
503 | x->rx_buf = rx; | |
504 | x->len = count; | |
505 | spi_message_add_tail(x, m); | |
506 | } | |
507 | ||
41e607f2 AB |
508 | static int ds1305_nvram_read(void *priv, unsigned int off, void *buf, |
509 | size_t count) | |
53e84b67 | 510 | { |
41e607f2 AB |
511 | struct ds1305 *ds1305 = priv; |
512 | struct spi_device *spi = ds1305->spi; | |
53e84b67 DB |
513 | u8 addr; |
514 | struct spi_message m; | |
515 | struct spi_transfer x[2]; | |
53e84b67 | 516 | |
53e84b67 DB |
517 | addr = DS1305_NVRAM + off; |
518 | msg_init(&m, x, &addr, count, NULL, buf); | |
519 | ||
41e607f2 | 520 | return spi_sync(spi, &m); |
53e84b67 DB |
521 | } |
522 | ||
41e607f2 AB |
523 | static int ds1305_nvram_write(void *priv, unsigned int off, void *buf, |
524 | size_t count) | |
53e84b67 | 525 | { |
41e607f2 AB |
526 | struct ds1305 *ds1305 = priv; |
527 | struct spi_device *spi = ds1305->spi; | |
53e84b67 DB |
528 | u8 addr; |
529 | struct spi_message m; | |
530 | struct spi_transfer x[2]; | |
53e84b67 | 531 | |
53e84b67 DB |
532 | addr = (DS1305_WRITE | DS1305_NVRAM) + off; |
533 | msg_init(&m, x, &addr, count, buf, NULL); | |
534 | ||
41e607f2 | 535 | return spi_sync(spi, &m); |
53e84b67 DB |
536 | } |
537 | ||
53e84b67 DB |
538 | /*----------------------------------------------------------------------*/ |
539 | ||
540 | /* | |
541 | * Interface to SPI stack | |
542 | */ | |
543 | ||
5a167f45 | 544 | static int ds1305_probe(struct spi_device *spi) |
53e84b67 DB |
545 | { |
546 | struct ds1305 *ds1305; | |
53e84b67 DB |
547 | int status; |
548 | u8 addr, value; | |
cfa13b24 | 549 | struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev); |
53e84b67 | 550 | bool write_ctrl = false; |
eed9d7a3 AB |
551 | struct nvmem_config ds1305_nvmem_cfg = { |
552 | .name = "ds1305_nvram", | |
553 | .word_size = 1, | |
554 | .stride = 1, | |
555 | .size = DS1305_NVRAM_LEN, | |
556 | .reg_read = ds1305_nvram_read, | |
557 | .reg_write = ds1305_nvram_write, | |
558 | }; | |
53e84b67 DB |
559 | |
560 | /* Sanity check board setup data. This may be hooked up | |
561 | * in 3wire mode, but we don't care. Note that unless | |
562 | * there's an inverter in place, this needs SPI_CS_HIGH! | |
563 | */ | |
564 | if ((spi->bits_per_word && spi->bits_per_word != 8) | |
565 | || (spi->max_speed_hz > 2000000) | |
566 | || !(spi->mode & SPI_CPHA)) | |
567 | return -EINVAL; | |
568 | ||
569 | /* set up driver data */ | |
0529bf46 | 570 | ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL); |
53e84b67 DB |
571 | if (!ds1305) |
572 | return -ENOMEM; | |
573 | ds1305->spi = spi; | |
574 | spi_set_drvdata(spi, ds1305); | |
575 | ||
576 | /* read and cache control registers */ | |
577 | addr = DS1305_CONTROL; | |
465008fa SK |
578 | status = spi_write_then_read(spi, &addr, sizeof(addr), |
579 | ds1305->ctrl, sizeof(ds1305->ctrl)); | |
53e84b67 DB |
580 | if (status < 0) { |
581 | dev_dbg(&spi->dev, "can't %s, %d\n", | |
582 | "read", status); | |
0529bf46 | 583 | return status; |
53e84b67 DB |
584 | } |
585 | ||
01a4ca16 | 586 | dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl); |
53e84b67 DB |
587 | |
588 | /* Sanity check register values ... partially compensating for the | |
589 | * fact that SPI has no device handshake. A pullup on MISO would | |
590 | * make these tests fail; but not all systems will have one. If | |
591 | * some register is neither 0x00 nor 0xff, a chip is likely there. | |
592 | */ | |
593 | if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) { | |
594 | dev_dbg(&spi->dev, "RTC chip is not present\n"); | |
0529bf46 | 595 | return -ENODEV; |
53e84b67 DB |
596 | } |
597 | if (ds1305->ctrl[2] == 0) | |
598 | dev_dbg(&spi->dev, "chip may not be present\n"); | |
599 | ||
600 | /* enable writes if needed ... if we were paranoid it would | |
601 | * make sense to enable them only when absolutely necessary. | |
602 | */ | |
603 | if (ds1305->ctrl[0] & DS1305_WP) { | |
604 | u8 buf[2]; | |
605 | ||
606 | ds1305->ctrl[0] &= ~DS1305_WP; | |
607 | ||
608 | buf[0] = DS1305_WRITE | DS1305_CONTROL; | |
609 | buf[1] = ds1305->ctrl[0]; | |
465008fa | 610 | status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); |
53e84b67 DB |
611 | |
612 | dev_dbg(&spi->dev, "clear WP --> %d\n", status); | |
613 | if (status < 0) | |
0529bf46 | 614 | return status; |
53e84b67 DB |
615 | } |
616 | ||
617 | /* on DS1305, maybe start oscillator; like most low power | |
618 | * oscillators, it may take a second to stabilize | |
619 | */ | |
620 | if (ds1305->ctrl[0] & DS1305_nEOSC) { | |
621 | ds1305->ctrl[0] &= ~DS1305_nEOSC; | |
622 | write_ctrl = true; | |
623 | dev_warn(&spi->dev, "SET TIME!\n"); | |
624 | } | |
625 | ||
626 | /* ack any pending IRQs */ | |
627 | if (ds1305->ctrl[1]) { | |
628 | ds1305->ctrl[1] = 0; | |
629 | write_ctrl = true; | |
630 | } | |
631 | ||
632 | /* this may need one-time (re)init */ | |
633 | if (pdata) { | |
634 | /* maybe enable trickle charge */ | |
635 | if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) { | |
636 | ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC | |
637 | | pdata->trickle; | |
638 | write_ctrl = true; | |
639 | } | |
640 | ||
641 | /* on DS1306, configure 1 Hz signal */ | |
642 | if (pdata->is_ds1306) { | |
643 | if (pdata->en_1hz) { | |
644 | if (!(ds1305->ctrl[0] & DS1306_1HZ)) { | |
645 | ds1305->ctrl[0] |= DS1306_1HZ; | |
646 | write_ctrl = true; | |
647 | } | |
648 | } else { | |
649 | if (ds1305->ctrl[0] & DS1306_1HZ) { | |
650 | ds1305->ctrl[0] &= ~DS1306_1HZ; | |
651 | write_ctrl = true; | |
652 | } | |
653 | } | |
654 | } | |
655 | } | |
656 | ||
657 | if (write_ctrl) { | |
658 | u8 buf[4]; | |
659 | ||
660 | buf[0] = DS1305_WRITE | DS1305_CONTROL; | |
661 | buf[1] = ds1305->ctrl[0]; | |
662 | buf[2] = ds1305->ctrl[1]; | |
663 | buf[3] = ds1305->ctrl[2]; | |
465008fa | 664 | status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); |
53e84b67 DB |
665 | if (status < 0) { |
666 | dev_dbg(&spi->dev, "can't %s, %d\n", | |
667 | "write", status); | |
0529bf46 | 668 | return status; |
53e84b67 DB |
669 | } |
670 | ||
01a4ca16 | 671 | dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl); |
53e84b67 DB |
672 | } |
673 | ||
674 | /* see if non-Linux software set up AM/PM mode */ | |
675 | addr = DS1305_HOUR; | |
465008fa SK |
676 | status = spi_write_then_read(spi, &addr, sizeof(addr), |
677 | &value, sizeof(value)); | |
53e84b67 DB |
678 | if (status < 0) { |
679 | dev_dbg(&spi->dev, "read HOUR --> %d\n", status); | |
0529bf46 | 680 | return status; |
53e84b67 DB |
681 | } |
682 | ||
683 | ds1305->hr12 = (DS1305_HR_12 & value) != 0; | |
684 | if (ds1305->hr12) | |
685 | dev_dbg(&spi->dev, "AM/PM\n"); | |
686 | ||
687 | /* register RTC ... from here on, ds1305->ctrl needs locking */ | |
6a4e8916 | 688 | ds1305->rtc = devm_rtc_allocate_device(&spi->dev); |
44c638ce | 689 | if (IS_ERR(ds1305->rtc)) |
6a4e8916 | 690 | return PTR_ERR(ds1305->rtc); |
6a4e8916 AB |
691 | |
692 | ds1305->rtc->ops = &ds1305_ops; | |
9869a93c AB |
693 | ds1305->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; |
694 | ds1305->rtc->range_max = RTC_TIMESTAMP_END_2099; | |
6a4e8916 | 695 | |
41e607f2 | 696 | ds1305_nvmem_cfg.priv = ds1305; |
fdcfd854 | 697 | status = devm_rtc_register_device(ds1305->rtc); |
44c638ce | 698 | if (status) |
0529bf46 | 699 | return status; |
53e84b67 | 700 | |
3a905c2d | 701 | devm_rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg); |
6910614f | 702 | |
53e84b67 DB |
703 | /* Maybe set up alarm IRQ; be ready to handle it triggering right |
704 | * away. NOTE that we don't share this. The signal is active low, | |
705 | * and we can't ack it before a SPI message delay. We temporarily | |
706 | * disable the IRQ until it's acked, which lets us work with more | |
707 | * IRQ trigger modes (not all IRQ controllers can do falling edge). | |
708 | */ | |
709 | if (spi->irq) { | |
710 | INIT_WORK(&ds1305->work, ds1305_work); | |
0529bf46 | 711 | status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq, |
b74d2caa | 712 | 0, dev_name(&ds1305->rtc->dev), ds1305); |
53e84b67 | 713 | if (status < 0) { |
4071ea25 | 714 | dev_err(&spi->dev, "request_irq %d --> %d\n", |
53e84b67 | 715 | spi->irq, status); |
4071ea25 AZ |
716 | } else { |
717 | device_set_wakeup_capable(&spi->dev, 1); | |
53e84b67 DB |
718 | } |
719 | } | |
720 | ||
53e84b67 | 721 | return 0; |
53e84b67 DB |
722 | } |
723 | ||
5a167f45 | 724 | static int ds1305_remove(struct spi_device *spi) |
53e84b67 | 725 | { |
b74d2caa | 726 | struct ds1305 *ds1305 = spi_get_drvdata(spi); |
53e84b67 | 727 | |
53e84b67 DB |
728 | /* carefully shut down irq and workqueue, if present */ |
729 | if (spi->irq) { | |
730 | set_bit(FLAG_EXITING, &ds1305->flags); | |
0529bf46 | 731 | devm_free_irq(&spi->dev, spi->irq, ds1305); |
9db8995b | 732 | cancel_work_sync(&ds1305->work); |
53e84b67 DB |
733 | } |
734 | ||
53e84b67 DB |
735 | return 0; |
736 | } | |
737 | ||
738 | static struct spi_driver ds1305_driver = { | |
739 | .driver.name = "rtc-ds1305", | |
53e84b67 | 740 | .probe = ds1305_probe, |
5a167f45 | 741 | .remove = ds1305_remove, |
53e84b67 DB |
742 | /* REVISIT add suspend/resume */ |
743 | }; | |
744 | ||
109e9418 | 745 | module_spi_driver(ds1305_driver); |
53e84b67 DB |
746 | |
747 | MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips"); | |
748 | MODULE_LICENSE("GPL"); | |
e0626e38 | 749 | MODULE_ALIAS("spi:rtc-ds1305"); |