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[mirror_ubuntu-hirsute-kernel.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
1abb0dc9
DB
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
eb86c306 20#include <linux/rtc/ds1307.h>
1abb0dc9 21
40ce972d
DA
22/*
23 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB
24 * to have set the chip up as a clock (turning on the oscillator and
25 * setting the date and time), Linux can ignore the non-clock features.
26 * That's a natural job for a factory or repair bench.
1abb0dc9
DB
27 */
28enum ds_type {
045e0e85
DB
29 ds_1307,
30 ds_1337,
31 ds_1338,
32 ds_1339,
33 ds_1340,
33df2ee1 34 ds_1388,
97f902b7 35 ds_3231,
045e0e85 36 m41t00,
43fcb815 37 mcp7941x,
a2166858 38 rx_8025,
32d322bc 39 last_ds_type /* always last */
40ce972d 40 /* rs5c372 too? different address... */
1abb0dc9
DB
41};
42
1abb0dc9
DB
43
44/* RTC registers don't differ much, except for the century flag */
45#define DS1307_REG_SECS 0x00 /* 00-59 */
46# define DS1307_BIT_CH 0x80
be5f59f4 47# define DS1340_BIT_nEOSC 0x80
43fcb815 48# define MCP7941X_BIT_ST 0x80
1abb0dc9
DB
49#define DS1307_REG_MIN 0x01 /* 00-59 */
50#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB
51# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
52# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB
53# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
54# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
55#define DS1307_REG_WDAY 0x03 /* 01-07 */
43fcb815 56# define MCP7941X_BIT_VBATEN 0x08
1abb0dc9
DB
57#define DS1307_REG_MDAY 0x04 /* 01-31 */
58#define DS1307_REG_MONTH 0x05 /* 01-12 */
59# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
60#define DS1307_REG_YEAR 0x06 /* 00-99 */
61
40ce972d
DA
62/*
63 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB
64 * start at 7, and they differ a LOT. Only control and status matter for
65 * basic RTC date and time functionality; be careful using them.
1abb0dc9 66 */
045e0e85 67#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 68# define DS1307_BIT_OUT 0x80
be5f59f4 69# define DS1338_BIT_OSF 0x20
1abb0dc9
DB
70# define DS1307_BIT_SQWE 0x10
71# define DS1307_BIT_RS1 0x02
72# define DS1307_BIT_RS0 0x01
73#define DS1337_REG_CONTROL 0x0e
74# define DS1337_BIT_nEOSC 0x80
cb49a5e9 75# define DS1339_BIT_BBSQI 0x20
97f902b7 76# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB
77# define DS1337_BIT_RS2 0x10
78# define DS1337_BIT_RS1 0x08
79# define DS1337_BIT_INTCN 0x04
80# define DS1337_BIT_A2IE 0x02
81# define DS1337_BIT_A1IE 0x01
045e0e85
DB
82#define DS1340_REG_CONTROL 0x07
83# define DS1340_BIT_OUT 0x80
84# define DS1340_BIT_FT 0x40
85# define DS1340_BIT_CALIB_SIGN 0x20
86# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG
87#define DS1340_REG_FLAG 0x09
88# define DS1340_BIT_OSF 0x80
1abb0dc9
DB
89#define DS1337_REG_STATUS 0x0f
90# define DS1337_BIT_OSF 0x80
91# define DS1337_BIT_A2I 0x02
92# define DS1337_BIT_A1I 0x01
cb49a5e9 93#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS
94
95#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 96
a2166858
MF
97#define RX8025_REG_CTRL1 0x0e
98# define RX8025_BIT_2412 0x20
99#define RX8025_REG_CTRL2 0x0f
100# define RX8025_BIT_PON 0x10
101# define RX8025_BIT_VDET 0x40
102# define RX8025_BIT_XST 0x20
1abb0dc9
DB
103
104
105struct ds1307 {
33df2ee1 106 u8 offset; /* register's offset */
cb49a5e9 107 u8 regs[11];
9eab0a78
AB
108 u16 nvram_offset;
109 struct bin_attribute *nvram;
1abb0dc9 110 enum ds_type type;
cb49a5e9
RG
111 unsigned long flags;
112#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
113#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 114 struct i2c_client *client;
1abb0dc9 115 struct rtc_device *rtc;
cb49a5e9 116 struct work_struct work;
0cc43a18 117 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
30e7b039 118 u8 length, u8 *values);
0cc43a18 119 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
30e7b039 120 u8 length, const u8 *values);
1abb0dc9
DB
121};
122
045e0e85 123struct chip_desc {
045e0e85 124 unsigned alarm:1;
9eab0a78
AB
125 u16 nvram_offset;
126 u16 nvram_size;
eb86c306 127 u16 trickle_charger_reg;
045e0e85
DB
128};
129
32d322bc
WS
130static const struct chip_desc chips[last_ds_type] = {
131 [ds_1307] = {
9eab0a78
AB
132 .nvram_offset = 8,
133 .nvram_size = 56,
32d322bc
WS
134 },
135 [ds_1337] = {
136 .alarm = 1,
137 },
138 [ds_1338] = {
9eab0a78
AB
139 .nvram_offset = 8,
140 .nvram_size = 56,
32d322bc
WS
141 },
142 [ds_1339] = {
143 .alarm = 1,
eb86c306
WS
144 .trickle_charger_reg = 0x10,
145 },
146 [ds_1340] = {
147 .trickle_charger_reg = 0x08,
148 },
149 [ds_1388] = {
150 .trickle_charger_reg = 0x0a,
32d322bc
WS
151 },
152 [ds_3231] = {
153 .alarm = 1,
154 },
9eab0a78
AB
155 [mcp7941x] = {
156 /* this is battery backed SRAM */
157 .nvram_offset = 0x20,
158 .nvram_size = 0x40,
159 },
32d322bc 160};
045e0e85 161
3760f736
JD
162static const struct i2c_device_id ds1307_id[] = {
163 { "ds1307", ds_1307 },
164 { "ds1337", ds_1337 },
165 { "ds1338", ds_1338 },
166 { "ds1339", ds_1339 },
33df2ee1 167 { "ds1388", ds_1388 },
3760f736 168 { "ds1340", ds_1340 },
97f902b7 169 { "ds3231", ds_3231 },
3760f736 170 { "m41t00", m41t00 },
43fcb815 171 { "mcp7941x", mcp7941x },
31c1771c 172 { "pt7c4338", ds_1307 },
a2166858 173 { "rx8025", rx_8025 },
3760f736
JD
174 { }
175};
176MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 177
cb49a5e9
RG
178/*----------------------------------------------------------------------*/
179
30e7b039
ES
180#define BLOCK_DATA_MAX_TRIES 10
181
0cc43a18
JD
182static s32 ds1307_read_block_data_once(const struct i2c_client *client,
183 u8 command, u8 length, u8 *values)
30e7b039
ES
184{
185 s32 i, data;
186
187 for (i = 0; i < length; i++) {
188 data = i2c_smbus_read_byte_data(client, command + i);
189 if (data < 0)
190 return data;
191 values[i] = data;
192 }
193 return i;
194}
195
0cc43a18 196static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
197 u8 length, u8 *values)
198{
199 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
200 s32 ret;
201 int tries = 0;
202
203 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
204 ret = ds1307_read_block_data_once(client, command, length, values);
205 if (ret < 0)
206 return ret;
207 do {
208 if (++tries > BLOCK_DATA_MAX_TRIES) {
209 dev_err(&client->dev,
210 "ds1307_read_block_data failed\n");
211 return -EIO;
212 }
213 memcpy(oldvalues, values, length);
214 ret = ds1307_read_block_data_once(client, command, length,
215 values);
216 if (ret < 0)
217 return ret;
218 } while (memcmp(oldvalues, values, length));
219 return length;
220}
221
0cc43a18 222static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
223 u8 length, const u8 *values)
224{
225 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
226 int tries = 0;
227
228 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
229 do {
230 s32 i, ret;
231
232 if (++tries > BLOCK_DATA_MAX_TRIES) {
233 dev_err(&client->dev,
234 "ds1307_write_block_data failed\n");
235 return -EIO;
236 }
237 for (i = 0; i < length; i++) {
238 ret = i2c_smbus_write_byte_data(client, command + i,
239 values[i]);
240 if (ret < 0)
241 return ret;
242 }
243 ret = ds1307_read_block_data_once(client, command, length,
244 currvalues);
245 if (ret < 0)
246 return ret;
247 } while (memcmp(currvalues, values, length));
248 return length;
249}
250
251/*----------------------------------------------------------------------*/
252
cb49a5e9
RG
253/*
254 * The IRQ logic includes a "real" handler running in IRQ context just
255 * long enough to schedule this workqueue entry. We need a task context
256 * to talk to the RTC, since I2C I/O calls require that; and disable the
257 * IRQ until we clear its status on the chip, so that this handler can
258 * work with any type of triggering (not just falling edge).
259 *
260 * The ds1337 and ds1339 both have two alarms, but we only use the first
261 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
262 * signal; ds1339 chips have only one alarm signal.
263 */
264static void ds1307_work(struct work_struct *work)
265{
266 struct ds1307 *ds1307;
267 struct i2c_client *client;
268 struct mutex *lock;
269 int stat, control;
270
271 ds1307 = container_of(work, struct ds1307, work);
272 client = ds1307->client;
273 lock = &ds1307->rtc->ops_lock;
274
275 mutex_lock(lock);
276 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
277 if (stat < 0)
278 goto out;
279
280 if (stat & DS1337_BIT_A1I) {
281 stat &= ~DS1337_BIT_A1I;
282 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
283
284 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
285 if (control < 0)
286 goto out;
287
288 control &= ~DS1337_BIT_A1IE;
289 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
290
cb49a5e9 291 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG
292 }
293
294out:
295 if (test_bit(HAS_ALARM, &ds1307->flags))
296 enable_irq(client->irq);
297 mutex_unlock(lock);
298}
299
300static irqreturn_t ds1307_irq(int irq, void *dev_id)
301{
302 struct i2c_client *client = dev_id;
303 struct ds1307 *ds1307 = i2c_get_clientdata(client);
304
305 disable_irq_nosync(irq);
306 schedule_work(&ds1307->work);
307 return IRQ_HANDLED;
308}
309
310/*----------------------------------------------------------------------*/
311
1abb0dc9
DB
312static int ds1307_get_time(struct device *dev, struct rtc_time *t)
313{
314 struct ds1307 *ds1307 = dev_get_drvdata(dev);
315 int tmp;
316
045e0e85 317 /* read the RTC date and time registers all at once */
30e7b039 318 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 319 ds1307->offset, 7, ds1307->regs);
fed40b73 320 if (tmp != 7) {
1abb0dc9
DB
321 dev_err(dev, "%s error %d\n", "read", tmp);
322 return -EIO;
323 }
324
325 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
326 "read",
327 ds1307->regs[0], ds1307->regs[1],
328 ds1307->regs[2], ds1307->regs[3],
329 ds1307->regs[4], ds1307->regs[5],
330 ds1307->regs[6]);
331
fe20ba70
AB
332 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
333 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 334 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB
335 t->tm_hour = bcd2bin(tmp);
336 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
337 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 338 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 339 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB
340
341 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 342 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB
343
344 dev_dbg(dev, "%s secs=%d, mins=%d, "
345 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
346 "read", t->tm_sec, t->tm_min,
347 t->tm_hour, t->tm_mday,
348 t->tm_mon, t->tm_year, t->tm_wday);
349
045e0e85
DB
350 /* initial clock setting can be undefined */
351 return rtc_valid_tm(t);
1abb0dc9
DB
352}
353
354static int ds1307_set_time(struct device *dev, struct rtc_time *t)
355{
356 struct ds1307 *ds1307 = dev_get_drvdata(dev);
357 int result;
358 int tmp;
359 u8 *buf = ds1307->regs;
360
361 dev_dbg(dev, "%s secs=%d, mins=%d, "
362 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG
363 "write", t->tm_sec, t->tm_min,
364 t->tm_hour, t->tm_mday,
365 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 366
fe20ba70
AB
367 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
368 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
369 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
370 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
371 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
372 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB
373
374 /* assume 20YY not 19YY */
375 tmp = t->tm_year - 100;
fe20ba70 376 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 377
be5f59f4
RG
378 switch (ds1307->type) {
379 case ds_1337:
380 case ds_1339:
97f902b7 381 case ds_3231:
1abb0dc9 382 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG
383 break;
384 case ds_1340:
1abb0dc9
DB
385 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
386 | DS1340_BIT_CENTURY;
be5f59f4 387 break;
43fcb815 388 case mcp7941x:
40ce972d
DA
389 /*
390 * these bits were cleared when preparing the date/time
391 * values and need to be set again before writing the
392 * buffer out to the device.
393 */
43fcb815
DA
394 buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
395 buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
396 break;
be5f59f4
RG
397 default:
398 break;
399 }
1abb0dc9 400
1abb0dc9
DB
401 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
402 "write", buf[0], buf[1], buf[2], buf[3],
403 buf[4], buf[5], buf[6]);
404
33df2ee1
JT
405 result = ds1307->write_block_data(ds1307->client,
406 ds1307->offset, 7, buf);
fed40b73
BS
407 if (result < 0) {
408 dev_err(dev, "%s error %d\n", "write", result);
409 return result;
1abb0dc9
DB
410 }
411 return 0;
412}
413
74d88eb2 414static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
415{
416 struct i2c_client *client = to_i2c_client(dev);
417 struct ds1307 *ds1307 = i2c_get_clientdata(client);
418 int ret;
419
420 if (!test_bit(HAS_ALARM, &ds1307->flags))
421 return -EINVAL;
422
423 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 424 ret = ds1307->read_block_data(client,
fed40b73
BS
425 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
426 if (ret != 9) {
cb49a5e9
RG
427 dev_err(dev, "%s error %d\n", "alarm read", ret);
428 return -EIO;
429 }
430
431 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
432 "alarm read",
433 ds1307->regs[0], ds1307->regs[1],
434 ds1307->regs[2], ds1307->regs[3],
435 ds1307->regs[4], ds1307->regs[5],
436 ds1307->regs[6], ds1307->regs[7],
437 ds1307->regs[8]);
438
40ce972d
DA
439 /*
440 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG
441 * and that all four fields are checked matches
442 */
443 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
444 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
445 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
446 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
447 t->time.tm_mon = -1;
448 t->time.tm_year = -1;
449 t->time.tm_wday = -1;
450 t->time.tm_yday = -1;
451 t->time.tm_isdst = -1;
452
453 /* ... and status */
454 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
455 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
456
457 dev_dbg(dev, "%s secs=%d, mins=%d, "
458 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
459 "alarm read", t->time.tm_sec, t->time.tm_min,
460 t->time.tm_hour, t->time.tm_mday,
461 t->enabled, t->pending);
462
463 return 0;
464}
465
74d88eb2 466static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 467{
40ce972d 468 struct i2c_client *client = to_i2c_client(dev);
cb49a5e9
RG
469 struct ds1307 *ds1307 = i2c_get_clientdata(client);
470 unsigned char *buf = ds1307->regs;
471 u8 control, status;
472 int ret;
473
474 if (!test_bit(HAS_ALARM, &ds1307->flags))
475 return -EINVAL;
476
477 dev_dbg(dev, "%s secs=%d, mins=%d, "
478 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
479 "alarm set", t->time.tm_sec, t->time.tm_min,
480 t->time.tm_hour, t->time.tm_mday,
481 t->enabled, t->pending);
482
483 /* read current status of both alarms and the chip */
30e7b039 484 ret = ds1307->read_block_data(client,
fed40b73
BS
485 DS1339_REG_ALARM1_SECS, 9, buf);
486 if (ret != 9) {
cb49a5e9
RG
487 dev_err(dev, "%s error %d\n", "alarm write", ret);
488 return -EIO;
489 }
490 control = ds1307->regs[7];
491 status = ds1307->regs[8];
492
493 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
494 "alarm set (old status)",
495 ds1307->regs[0], ds1307->regs[1],
496 ds1307->regs[2], ds1307->regs[3],
497 ds1307->regs[4], ds1307->regs[5],
498 ds1307->regs[6], control, status);
499
500 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG
501 buf[0] = bin2bcd(t->time.tm_sec);
502 buf[1] = bin2bcd(t->time.tm_min);
503 buf[2] = bin2bcd(t->time.tm_hour);
504 buf[3] = bin2bcd(t->time.tm_mday);
505
506 /* set ALARM2 to non-garbage */
507 buf[4] = 0;
508 buf[5] = 0;
509 buf[6] = 0;
510
511 /* optionally enable ALARM1 */
512 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
513 if (t->enabled) {
514 dev_dbg(dev, "alarm IRQ armed\n");
515 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
516 }
517 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
518
30e7b039 519 ret = ds1307->write_block_data(client,
fed40b73
BS
520 DS1339_REG_ALARM1_SECS, 9, buf);
521 if (ret < 0) {
cb49a5e9 522 dev_err(dev, "can't set alarm time\n");
fed40b73 523 return ret;
cb49a5e9
RG
524 }
525
526 return 0;
527}
528
16380c15 529static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9
RG
530{
531 struct i2c_client *client = to_i2c_client(dev);
532 struct ds1307 *ds1307 = i2c_get_clientdata(client);
533 int ret;
534
16380c15
JS
535 if (!test_bit(HAS_ALARM, &ds1307->flags))
536 return -ENOTTY;
cb49a5e9 537
16380c15
JS
538 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
539 if (ret < 0)
540 return ret;
cb49a5e9 541
16380c15 542 if (enabled)
cb49a5e9 543 ret |= DS1337_BIT_A1IE;
16380c15
JS
544 else
545 ret &= ~DS1337_BIT_A1IE;
cb49a5e9 546
16380c15
JS
547 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
548 if (ret < 0)
549 return ret;
cb49a5e9
RG
550
551 return 0;
552}
553
ff8371ac 554static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB
555 .read_time = ds1307_get_time,
556 .set_time = ds1307_set_time,
74d88eb2
JR
557 .read_alarm = ds1337_read_alarm,
558 .set_alarm = ds1337_set_alarm,
16380c15 559 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB
560};
561
682d73f6
DB
562/*----------------------------------------------------------------------*/
563
682d73f6 564static ssize_t
2c3c8bea
CW
565ds1307_nvram_read(struct file *filp, struct kobject *kobj,
566 struct bin_attribute *attr,
682d73f6
DB
567 char *buf, loff_t off, size_t count)
568{
569 struct i2c_client *client;
570 struct ds1307 *ds1307;
682d73f6
DB
571 int result;
572
fcd8db00 573 client = kobj_to_i2c_client(kobj);
682d73f6
DB
574 ds1307 = i2c_get_clientdata(client);
575
9eab0a78 576 if (unlikely(off >= ds1307->nvram->size))
682d73f6 577 return 0;
9eab0a78
AB
578 if ((off + count) > ds1307->nvram->size)
579 count = ds1307->nvram->size - off;
682d73f6
DB
580 if (unlikely(!count))
581 return count;
582
9eab0a78
AB
583 result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
584 count, buf);
fed40b73 585 if (result < 0)
682d73f6 586 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 587 return result;
682d73f6
DB
588}
589
590static ssize_t
2c3c8bea
CW
591ds1307_nvram_write(struct file *filp, struct kobject *kobj,
592 struct bin_attribute *attr,
682d73f6
DB
593 char *buf, loff_t off, size_t count)
594{
595 struct i2c_client *client;
30e7b039 596 struct ds1307 *ds1307;
fed40b73 597 int result;
682d73f6 598
fcd8db00 599 client = kobj_to_i2c_client(kobj);
30e7b039 600 ds1307 = i2c_get_clientdata(client);
682d73f6 601
9eab0a78 602 if (unlikely(off >= ds1307->nvram->size))
682d73f6 603 return -EFBIG;
9eab0a78
AB
604 if ((off + count) > ds1307->nvram->size)
605 count = ds1307->nvram->size - off;
682d73f6
DB
606 if (unlikely(!count))
607 return count;
608
9eab0a78
AB
609 result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
610 count, buf);
fed40b73
BS
611 if (result < 0) {
612 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
613 return result;
614 }
615 return count;
682d73f6
DB
616}
617
682d73f6
DB
618/*----------------------------------------------------------------------*/
619
d2653e92
JD
620static int __devinit ds1307_probe(struct i2c_client *client,
621 const struct i2c_device_id *id)
1abb0dc9
DB
622{
623 struct ds1307 *ds1307;
624 int err = -ENODEV;
1abb0dc9 625 int tmp;
3760f736 626 const struct chip_desc *chip = &chips[id->driver_data];
c065f35c 627 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
cb49a5e9 628 int want_irq = false;
fed40b73 629 unsigned char *buf;
eb86c306 630 struct ds1307_platform_data *pdata = client->dev.platform_data;
97f902b7
WS
631 static const int bbsqi_bitpos[] = {
632 [ds_1337] = 0,
633 [ds_1339] = DS1339_BIT_BBSQI,
634 [ds_3231] = DS3231_BIT_BBSQW,
635 };
1abb0dc9 636
30e7b039
ES
637 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
638 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB
639 return -EIO;
640
40ce972d
DA
641 ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL);
642 if (!ds1307)
c065f35c 643 return -ENOMEM;
045e0e85 644
1abb0dc9 645 i2c_set_clientdata(client, ds1307);
33df2ee1
JT
646
647 ds1307->client = client;
648 ds1307->type = id->driver_data;
33df2ee1 649
eb86c306
WS
650 if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg)
651 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
652 DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup);
653
fed40b73 654 buf = ds1307->regs;
30e7b039
ES
655 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
656 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
657 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
658 } else {
659 ds1307->read_block_data = ds1307_read_block_data;
660 ds1307->write_block_data = ds1307_write_block_data;
661 }
045e0e85
DB
662
663 switch (ds1307->type) {
664 case ds_1337:
665 case ds_1339:
97f902b7 666 case ds_3231:
be5f59f4 667 /* get registers that the "rtc" read below won't read... */
30e7b039 668 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 669 DS1337_REG_CONTROL, 2, buf);
1abb0dc9
DB
670 if (tmp != 2) {
671 pr_debug("read error %d\n", tmp);
672 err = -EIO;
673 goto exit_free;
674 }
675
be5f59f4
RG
676 /* oscillator off? turn it on, so clock can tick. */
677 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG
678 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
679
40ce972d
DA
680 /*
681 * Using IRQ? Disable the square wave and both alarms.
97f902b7
WS
682 * For some variants, be sure alarms can trigger when we're
683 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 684 */
b24a7267
WS
685 if (ds1307->client->irq > 0 && chip->alarm) {
686 INIT_WORK(&ds1307->work, ds1307_work);
687
97f902b7
WS
688 ds1307->regs[0] |= DS1337_BIT_INTCN
689 | bbsqi_bitpos[ds1307->type];
cb49a5e9 690 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
b24a7267
WS
691
692 want_irq = true;
cb49a5e9
RG
693 }
694
695 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
696 ds1307->regs[0]);
be5f59f4
RG
697
698 /* oscillator fault? clear flag, and warn */
699 if (ds1307->regs[1] & DS1337_BIT_OSF) {
700 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
701 ds1307->regs[1] & ~DS1337_BIT_OSF);
702 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 703 }
045e0e85 704 break;
a2166858
MF
705
706 case rx_8025:
707 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
708 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
709 if (tmp != 2) {
710 pr_debug("read error %d\n", tmp);
711 err = -EIO;
712 goto exit_free;
713 }
714
715 /* oscillator off? turn it on, so clock can tick. */
716 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
717 ds1307->regs[1] |= RX8025_BIT_XST;
718 i2c_smbus_write_byte_data(client,
719 RX8025_REG_CTRL2 << 4 | 0x08,
720 ds1307->regs[1]);
721 dev_warn(&client->dev,
722 "oscillator stop detected - SET TIME!\n");
723 }
724
725 if (ds1307->regs[1] & RX8025_BIT_PON) {
726 ds1307->regs[1] &= ~RX8025_BIT_PON;
727 i2c_smbus_write_byte_data(client,
728 RX8025_REG_CTRL2 << 4 | 0x08,
729 ds1307->regs[1]);
730 dev_warn(&client->dev, "power-on detected\n");
731 }
732
733 if (ds1307->regs[1] & RX8025_BIT_VDET) {
734 ds1307->regs[1] &= ~RX8025_BIT_VDET;
735 i2c_smbus_write_byte_data(client,
736 RX8025_REG_CTRL2 << 4 | 0x08,
737 ds1307->regs[1]);
738 dev_warn(&client->dev, "voltage drop detected\n");
739 }
740
741 /* make sure we are running in 24hour mode */
742 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
743 u8 hour;
744
745 /* switch to 24 hour mode */
746 i2c_smbus_write_byte_data(client,
747 RX8025_REG_CTRL1 << 4 | 0x08,
748 ds1307->regs[0] |
749 RX8025_BIT_2412);
750
751 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
752 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
753 if (tmp != 2) {
754 pr_debug("read error %d\n", tmp);
755 err = -EIO;
756 goto exit_free;
757 }
758
759 /* correct hour */
760 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
761 if (hour == 12)
762 hour = 0;
763 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
764 hour += 12;
765
766 i2c_smbus_write_byte_data(client,
767 DS1307_REG_HOUR << 4 | 0x08,
768 hour);
769 }
770 break;
33df2ee1
JT
771 case ds_1388:
772 ds1307->offset = 1; /* Seconds starts at 1 */
773 break;
045e0e85
DB
774 default:
775 break;
776 }
1abb0dc9
DB
777
778read_rtc:
779 /* read RTC registers */
96fc3a45 780 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
fed40b73 781 if (tmp != 8) {
1abb0dc9
DB
782 pr_debug("read error %d\n", tmp);
783 err = -EIO;
784 goto exit_free;
785 }
786
40ce972d
DA
787 /*
788 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB
789 * specify the extra bits as must-be-zero, but there are
790 * still a few values that are clearly out-of-range.
791 */
792 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB
793 switch (ds1307->type) {
794 case ds_1307:
045e0e85 795 case m41t00:
be5f59f4 796 /* clock halted? turn it on, so clock can tick. */
045e0e85 797 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG
798 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
799 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 800 goto read_rtc;
1abb0dc9 801 }
045e0e85 802 break;
be5f59f4
RG
803 case ds_1338:
804 /* clock halted? turn it on, so clock can tick. */
045e0e85 805 if (tmp & DS1307_BIT_CH)
be5f59f4
RG
806 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
807
808 /* oscillator fault? clear flag, and warn */
809 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
810 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 811 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG
812 & ~DS1338_BIT_OSF);
813 dev_warn(&client->dev, "SET TIME!\n");
814 goto read_rtc;
815 }
045e0e85 816 break;
fcd8db00
R
817 case ds_1340:
818 /* clock halted? turn it on, so clock can tick. */
819 if (tmp & DS1340_BIT_nEOSC)
820 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
821
822 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
823 if (tmp < 0) {
824 pr_debug("read error %d\n", tmp);
825 err = -EIO;
826 goto exit_free;
827 }
828
829 /* oscillator fault? clear flag, and warn */
830 if (tmp & DS1340_BIT_OSF) {
831 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
832 dev_warn(&client->dev, "SET TIME!\n");
833 }
43fcb815
DA
834 break;
835 case mcp7941x:
836 /* make sure that the backup battery is enabled */
837 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
838 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
839 ds1307->regs[DS1307_REG_WDAY]
840 | MCP7941X_BIT_VBATEN);
841 }
842
843 /* clock halted? turn it on, so clock can tick. */
844 if (!(tmp & MCP7941X_BIT_ST)) {
845 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
846 MCP7941X_BIT_ST);
847 dev_warn(&client->dev, "SET TIME!\n");
848 goto read_rtc;
849 }
850
fcd8db00 851 break;
32d322bc 852 default:
045e0e85 853 break;
1abb0dc9 854 }
045e0e85 855
1abb0dc9 856 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB
857 switch (ds1307->type) {
858 case ds_1340:
859 case m41t00:
40ce972d
DA
860 /*
861 * NOTE: ignores century bits; fix before deploying
c065f35c
DB
862 * systems that will run through year 2100.
863 */
864 break;
a2166858
MF
865 case rx_8025:
866 break;
c065f35c
DB
867 default:
868 if (!(tmp & DS1307_BIT_12HR))
869 break;
870
40ce972d
DA
871 /*
872 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB
873 * take note...
874 */
fe20ba70 875 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB
876 if (tmp == 12)
877 tmp = 0;
878 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
879 tmp += 12;
1abb0dc9 880 i2c_smbus_write_byte_data(client,
96fc3a45 881 ds1307->offset + DS1307_REG_HOUR,
fe20ba70 882 bin2bcd(tmp));
1abb0dc9
DB
883 }
884
1abb0dc9
DB
885 ds1307->rtc = rtc_device_register(client->name, &client->dev,
886 &ds13xx_rtc_ops, THIS_MODULE);
887 if (IS_ERR(ds1307->rtc)) {
888 err = PTR_ERR(ds1307->rtc);
889 dev_err(&client->dev,
890 "unable to register the class device\n");
c065f35c 891 goto exit_free;
1abb0dc9
DB
892 }
893
cb49a5e9 894 if (want_irq) {
43d15bcd 895 err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
cb49a5e9
RG
896 ds1307->rtc->name, client);
897 if (err) {
898 dev_err(&client->dev,
899 "unable to request IRQ!\n");
900 goto exit_irq;
901 }
26b3c01f
AV
902
903 device_set_wakeup_capable(&client->dev, 1);
cb49a5e9
RG
904 set_bit(HAS_ALARM, &ds1307->flags);
905 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
906 }
907
9eab0a78
AB
908 if (chip->nvram_size) {
909 ds1307->nvram = kzalloc(sizeof(struct bin_attribute),
910 GFP_KERNEL);
911 if (!ds1307->nvram) {
912 err = -ENOMEM;
913 goto exit_nvram;
914 }
915 ds1307->nvram->attr.name = "nvram";
916 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
3f5ec5e0 917 sysfs_bin_attr_init(ds1307->nvram);
9eab0a78
AB
918 ds1307->nvram->read = ds1307_nvram_read,
919 ds1307->nvram->write = ds1307_nvram_write,
920 ds1307->nvram->size = chip->nvram_size;
921 ds1307->nvram_offset = chip->nvram_offset;
922 err = sysfs_create_bin_file(&client->dev.kobj, ds1307->nvram);
923 if (err) {
924 kfree(ds1307->nvram);
925 goto exit_nvram;
682d73f6 926 }
9eab0a78
AB
927 set_bit(HAS_NVRAM, &ds1307->flags);
928 dev_info(&client->dev, "%zu bytes nvram\n", ds1307->nvram->size);
682d73f6
DB
929 }
930
1abb0dc9
DB
931 return 0;
932
9eab0a78 933exit_nvram:
cb49a5e9 934exit_irq:
72445af8 935 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
936exit_free:
937 kfree(ds1307);
1abb0dc9
DB
938 return err;
939}
940
c065f35c 941static int __devexit ds1307_remove(struct i2c_client *client)
1abb0dc9 942{
40ce972d 943 struct ds1307 *ds1307 = i2c_get_clientdata(client);
cb49a5e9
RG
944
945 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
946 free_irq(client->irq, client);
947 cancel_work_sync(&ds1307->work);
948 }
1abb0dc9 949
9eab0a78
AB
950 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) {
951 sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
952 kfree(ds1307->nvram);
953 }
682d73f6 954
1abb0dc9 955 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
956 kfree(ds1307);
957 return 0;
958}
959
960static struct i2c_driver ds1307_driver = {
961 .driver = {
c065f35c 962 .name = "rtc-ds1307",
1abb0dc9
DB
963 .owner = THIS_MODULE,
964 },
c065f35c
DB
965 .probe = ds1307_probe,
966 .remove = __devexit_p(ds1307_remove),
3760f736 967 .id_table = ds1307_id,
1abb0dc9
DB
968};
969
0abc9201 970module_i2c_driver(ds1307_driver);
1abb0dc9
DB
971
972MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
973MODULE_LICENSE("GPL");