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rtc: ds1307: convert driver to regmap
[mirror_ubuntu-artful-kernel.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB		 1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
9c19b893 14#include <linux/acpi.h>
eac7237f
NM		 15#include <linux/bcd.h>
16#include <linux/i2c.h>
1abb0dc9 17#include <linux/init.h>
eac7237f 18#include <linux/module.h>
7ef6d2c2 19#include <linux/of_device.h>
eac7237f
NM		 20#include <linux/rtc/ds1307.h>
21#include <linux/rtc.h>
1abb0dc9 22#include <linux/slab.h>
1abb0dc9 23#include <linux/string.h>
445c0207
AM		 24#include <linux/hwmon.h>
25#include <linux/hwmon-sysfs.h>
6c6ff145 26#include <linux/clk-provider.h>
11e5890b 27#include <linux/regmap.h>
1abb0dc9 28
40ce972d
DA		 29/*
30 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 31 * to have set the chip up as a clock (turning on the oscillator and
32 * setting the date and time), Linux can ignore the non-clock features.
33 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 34 */
35enum ds_type {
045e0e85
DB		 36 ds_1307,
37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
33df2ee1 41 ds_1388,
97f902b7 42 ds_3231,
8566f70c 43 m41t0,
045e0e85 44 m41t00,
f4199f85 45 mcp794xx,
a2166858 46 rx_8025,
32d322bc 47 last_ds_type /* always last */
40ce972d 48 /* rs5c372 too? different address... */
1abb0dc9
DB		 49};
50
1abb0dc9
DB		 51
52/* RTC registers don't differ much, except for the century flag */
53#define DS1307_REG_SECS 0x00 /* 00-59 */
54# define DS1307_BIT_CH 0x80
be5f59f4 55# define DS1340_BIT_nEOSC 0x80
f4199f85 56# define MCP794XX_BIT_ST 0x80
1abb0dc9 57#define DS1307_REG_MIN 0x01 /* 00-59 */
8566f70c 58# define M41T0_BIT_OF 0x80
1abb0dc9 59#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 60# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
61# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 62# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
63# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
64#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 65# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 66#define DS1307_REG_MDAY 0x04 /* 01-31 */
67#define DS1307_REG_MONTH 0x05 /* 01-12 */
68# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
69#define DS1307_REG_YEAR 0x06 /* 00-99 */
70
40ce972d
DA		 71/*
72 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 73 * start at 7, and they differ a LOT. Only control and status matter for
74 * basic RTC date and time functionality; be careful using them.
1abb0dc9 75 */
045e0e85 76#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 77# define DS1307_BIT_OUT 0x80
be5f59f4 78# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 79# define DS1307_BIT_SQWE 0x10
80# define DS1307_BIT_RS1 0x02
81# define DS1307_BIT_RS0 0x01
82#define DS1337_REG_CONTROL 0x0e
83# define DS1337_BIT_nEOSC 0x80
cb49a5e9 84# define DS1339_BIT_BBSQI 0x20
97f902b7 85# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 86# define DS1337_BIT_RS2 0x10
87# define DS1337_BIT_RS1 0x08
88# define DS1337_BIT_INTCN 0x04
89# define DS1337_BIT_A2IE 0x02
90# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 91#define DS1340_REG_CONTROL 0x07
92# define DS1340_BIT_OUT 0x80
93# define DS1340_BIT_FT 0x40
94# define DS1340_BIT_CALIB_SIGN 0x20
95# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 96#define DS1340_REG_FLAG 0x09
97# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 98#define DS1337_REG_STATUS 0x0f
99# define DS1337_BIT_OSF 0x80
6c6ff145 100# define DS3231_BIT_EN32KHZ 0x08
1abb0dc9
DB		 101# define DS1337_BIT_A2I 0x02
102# define DS1337_BIT_A1I 0x01
cb49a5e9 103#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 104
105#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 106
a2166858
MF		 107#define RX8025_REG_CTRL1 0x0e
108# define RX8025_BIT_2412 0x20
109#define RX8025_REG_CTRL2 0x0f
110# define RX8025_BIT_PON 0x10
111# define RX8025_BIT_VDET 0x40
112# define RX8025_BIT_XST 0x20
1abb0dc9
DB		 113
114
115struct ds1307 {
33df2ee1 116 u8 offset; /* register's offset */
cb49a5e9 117 u8 regs[11];
9eab0a78
AB		 118 u16 nvram_offset;
119 struct bin_attribute *nvram;
1abb0dc9 120 enum ds_type type;
cb49a5e9
RG		 121 unsigned long flags;
122#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
123#define HAS_ALARM 1 /* bit 1 == irq claimed */
11e5890b
HK		 124 struct device *dev;
125 struct regmap *regmap;
126 const char *name;
127 int irq;
1abb0dc9 128 struct rtc_device *rtc;
6c6ff145
AM		 129#ifdef CONFIG_COMMON_CLK
130 struct clk_hw clks[2];
131#endif
1abb0dc9
DB		 132};
133
045e0e85 134struct chip_desc {
045e0e85 135 unsigned alarm:1;
9eab0a78
AB		 136 u16 nvram_offset;
137 u16 nvram_size;
eb86c306 138 u16 trickle_charger_reg;
33b04b7b 139 u8 trickle_charger_setup;
11e5890b
HK		 140 u8 (*do_trickle_setup)(struct ds1307 *, uint32_t,
141 bool);
045e0e85
DB		 142};
143
11e5890b 144static u8 do_trickle_setup_ds1339(struct ds1307 *, uint32_t ohms, bool diode);
33b04b7b
MV		 145
146static struct chip_desc chips[last_ds_type] = {
32d322bc 147 [ds_1307] = {
9eab0a78
AB		 148 .nvram_offset = 8,
149 .nvram_size = 56,
32d322bc
WS		 150 },
151 [ds_1337] = {
152 .alarm = 1,
153 },
154 [ds_1338] = {
9eab0a78
AB		 155 .nvram_offset = 8,
156 .nvram_size = 56,
32d322bc
WS		 157 },
158 [ds_1339] = {
159 .alarm = 1,
eb86c306 160 .trickle_charger_reg = 0x10,
33b04b7b 161 .do_trickle_setup = &do_trickle_setup_ds1339,
eb86c306
WS		 162 },
163 [ds_1340] = {
164 .trickle_charger_reg = 0x08,
165 },
166 [ds_1388] = {
167 .trickle_charger_reg = 0x0a,
32d322bc
WS		 168 },
169 [ds_3231] = {
170 .alarm = 1,
171 },
f4199f85 172 [mcp794xx] = {
1d1945d2 173 .alarm = 1,
9eab0a78
AB		 174 /* this is battery backed SRAM */
175 .nvram_offset = 0x20,
176 .nvram_size = 0x40,
177 },
32d322bc 178};
045e0e85 179
3760f736
JD		 180static const struct i2c_device_id ds1307_id[] = {
181 { "ds1307", ds_1307 },
182 { "ds1337", ds_1337 },
183 { "ds1338", ds_1338 },
184 { "ds1339", ds_1339 },
33df2ee1 185 { "ds1388", ds_1388 },
3760f736 186 { "ds1340", ds_1340 },
97f902b7 187 { "ds3231", ds_3231 },
8566f70c 188 { "m41t0", m41t0 },
3760f736 189 { "m41t00", m41t00 },
f4199f85
TN		 190 { "mcp7940x", mcp794xx },
191 { "mcp7941x", mcp794xx },
31c1771c 192 { "pt7c4338", ds_1307 },
a2166858 193 { "rx8025", rx_8025 },
78aaa06d 194 { "isl12057", ds_1337 },
3760f736
JD		 195 { }
196};
197MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 198
7ef6d2c2
JMC		 199#ifdef CONFIG_OF
200static const struct of_device_id ds1307_of_match[] = {
201 {
202 .compatible = "dallas,ds1307",
203 .data = (void *)ds_1307
204 },
205 {
206 .compatible = "dallas,ds1337",
207 .data = (void *)ds_1337
208 },
209 {
210 .compatible = "dallas,ds1338",
211 .data = (void *)ds_1338
212 },
213 {
214 .compatible = "dallas,ds1339",
215 .data = (void *)ds_1339
216 },
217 {
218 .compatible = "dallas,ds1388",
219 .data = (void *)ds_1388
220 },
221 {
222 .compatible = "dallas,ds1340",
223 .data = (void *)ds_1340
224 },
225 {
226 .compatible = "maxim,ds3231",
227 .data = (void *)ds_3231
228 },
db2f8141
AB		 229 {
230 .compatible = "st,m41t0",
231 .data = (void *)m41t00
232 },
7ef6d2c2
JMC		 233 {
234 .compatible = "st,m41t00",
235 .data = (void *)m41t00
236 },
237 {
238 .compatible = "microchip,mcp7940x",
239 .data = (void *)mcp794xx
240 },
241 {
242 .compatible = "microchip,mcp7941x",
243 .data = (void *)mcp794xx
244 },
245 {
246 .compatible = "pericom,pt7c4338",
247 .data = (void *)ds_1307
248 },
249 {
250 .compatible = "epson,rx8025",
251 .data = (void *)rx_8025
252 },
253 {
254 .compatible = "isil,isl12057",
255 .data = (void *)ds_1337
256 },
257 { }
258};
259MODULE_DEVICE_TABLE(of, ds1307_of_match);
260#endif
261
9c19b893
TH		 262#ifdef CONFIG_ACPI
263static const struct acpi_device_id ds1307_acpi_ids[] = {
264 { .id = "DS1307", .driver_data = ds_1307 },
265 { .id = "DS1337", .driver_data = ds_1337 },
266 { .id = "DS1338", .driver_data = ds_1338 },
267 { .id = "DS1339", .driver_data = ds_1339 },
268 { .id = "DS1388", .driver_data = ds_1388 },
269 { .id = "DS1340", .driver_data = ds_1340 },
270 { .id = "DS3231", .driver_data = ds_3231 },
8566f70c 271 { .id = "M41T0", .driver_data = m41t0 },
9c19b893
TH		 272 { .id = "M41T00", .driver_data = m41t00 },
273 { .id = "MCP7940X", .driver_data = mcp794xx },
274 { .id = "MCP7941X", .driver_data = mcp794xx },
275 { .id = "PT7C4338", .driver_data = ds_1307 },
276 { .id = "RX8025", .driver_data = rx_8025 },
277 { .id = "ISL12057", .driver_data = ds_1337 },
278 { }
279};
280MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
281#endif
282
cb49a5e9 283/*
cb49a5e9
RG		 284 * The ds1337 and ds1339 both have two alarms, but we only use the first
285 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
286 * signal; ds1339 chips have only one alarm signal.
287 */
2fb07a10 288static irqreturn_t ds1307_irq(int irq, void *dev_id)
cb49a5e9 289{
11e5890b 290 struct ds1307 *ds1307 = dev_id;
2fb07a10 291 struct mutex *lock = &ds1307->rtc->ops_lock;
11e5890b 292 int stat, control, ret;
cb49a5e9 293
cb49a5e9 294 mutex_lock(lock);
11e5890b
HK		 295 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
296 if (ret)
cb49a5e9
RG		 297 goto out;
298
299 if (stat & DS1337_BIT_A1I) {
300 stat &= ~DS1337_BIT_A1I;
11e5890b 301 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
cb49a5e9 302
11e5890b
HK		 303 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
304 if (ret)
cb49a5e9
RG		 305 goto out;
306
307 control &= ~DS1337_BIT_A1IE;
11e5890b 308 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, control);
cb49a5e9 309
cb49a5e9 310 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG		 311 }
312
313out:
cb49a5e9 314 mutex_unlock(lock);
cb49a5e9 315
cb49a5e9
RG		 316 return IRQ_HANDLED;
317}
318
319/*----------------------------------------------------------------------*/
320
1abb0dc9
DB		 321static int ds1307_get_time(struct device *dev, struct rtc_time *t)
322{
323 struct ds1307 *ds1307 = dev_get_drvdata(dev);
11e5890b 324 int tmp, ret;
1abb0dc9 325
045e0e85 326 /* read the RTC date and time registers all at once */
11e5890b
HK		 327 ret = regmap_bulk_read(ds1307->regmap, ds1307->offset, ds1307->regs, 7);
328 if (ret) {
329 dev_err(dev, "%s error %d\n", "read", ret);
330 return ret;
1abb0dc9
DB		 331 }
332
01a4ca16 333 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
1abb0dc9 334
8566f70c
SA		 335 /* if oscillator fail bit is set, no data can be trusted */
336 if (ds1307->type == m41t0 &&
337 ds1307->regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
338 dev_warn_once(dev, "oscillator failed, set time!\n");
339 return -EINVAL;
340 }
341
fe20ba70
AB		 342 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
343 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 344 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB		 345 t->tm_hour = bcd2bin(tmp);
346 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
347 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 348 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 349 t->tm_mon = bcd2bin(tmp) - 1;
fe20ba70 350 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9 351
50d6c0ea
AB		 352#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
353 switch (ds1307->type) {
354 case ds_1337:
355 case ds_1339:
356 case ds_3231:
357 if (ds1307->regs[DS1307_REG_MONTH] & DS1337_BIT_CENTURY)
358 t->tm_year += 100;
359 break;
360 case ds_1340:
361 if (ds1307->regs[DS1307_REG_HOUR] & DS1340_BIT_CENTURY)
362 t->tm_year += 100;
363 break;
364 default:
365 break;
366 }
367#endif
368
1abb0dc9
DB		 369 dev_dbg(dev, "%s secs=%d, mins=%d, "
370 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
371 "read", t->tm_sec, t->tm_min,
372 t->tm_hour, t->tm_mday,
373 t->tm_mon, t->tm_year, t->tm_wday);
374
045e0e85
DB		 375 /* initial clock setting can be undefined */
376 return rtc_valid_tm(t);
1abb0dc9
DB		 377}
378
379static int ds1307_set_time(struct device *dev, struct rtc_time *t)
380{
381 struct ds1307 *ds1307 = dev_get_drvdata(dev);
382 int result;
383 int tmp;
384 u8 *buf = ds1307->regs;
385
386 dev_dbg(dev, "%s secs=%d, mins=%d, "
387 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 388 "write", t->tm_sec, t->tm_min,
389 t->tm_hour, t->tm_mday,
390 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 391
50d6c0ea
AB		 392#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
393 if (t->tm_year < 100)
394 return -EINVAL;
395
396 switch (ds1307->type) {
397 case ds_1337:
398 case ds_1339:
399 case ds_3231:
400 case ds_1340:
401 if (t->tm_year > 299)
402 return -EINVAL;
403 default:
404 if (t->tm_year > 199)
405 return -EINVAL;
406 break;
407 }
408#else
409 if (t->tm_year < 100 || t->tm_year > 199)
410 return -EINVAL;
411#endif
412
fe20ba70
AB		 413 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
414 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
415 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
416 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
417 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
418 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 419
420 /* assume 20YY not 19YY */
421 tmp = t->tm_year - 100;
fe20ba70 422 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 423
be5f59f4
RG		 424 switch (ds1307->type) {
425 case ds_1337:
426 case ds_1339:
97f902b7 427 case ds_3231:
50d6c0ea
AB		 428 if (t->tm_year > 199)
429 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG		 430 break;
431 case ds_1340:
50d6c0ea
AB		 432 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN;
433 if (t->tm_year > 199)
434 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY;
be5f59f4 435 break;
f4199f85 436 case mcp794xx:
40ce972d
DA		 437 /*
438 * these bits were cleared when preparing the date/time
439 * values and need to be set again before writing the
440 * buffer out to the device.
441 */
f4199f85
TN		 442 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
443 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
43fcb815 444 break;
be5f59f4
RG		 445 default:
446 break;
447 }
1abb0dc9 448
01a4ca16 449 dev_dbg(dev, "%s: %7ph\n", "write", buf);
1abb0dc9 450
11e5890b
HK		 451 result = regmap_bulk_write(ds1307->regmap, ds1307->offset, buf, 7);
452 if (result) {
fed40b73
BS		 453 dev_err(dev, "%s error %d\n", "write", result);
454 return result;
1abb0dc9
DB		 455 }
456 return 0;
457}
458
74d88eb2 459static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 460{
11e5890b 461 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9
RG		 462 int ret;
463
464 if (!test_bit(HAS_ALARM, &ds1307->flags))
465 return -EINVAL;
466
467 /* read all ALARM1, ALARM2, and status registers at once */
11e5890b
HK		 468 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
469 ds1307->regs, 9);
470 if (ret) {
cb49a5e9 471 dev_err(dev, "%s error %d\n", "alarm read", ret);
11e5890b 472 return ret;
cb49a5e9
RG		 473 }
474
ff67abd2
RV		 475 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
476 &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]);
cb49a5e9 477
40ce972d
DA		 478 /*
479 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 480 * and that all four fields are checked matches
481 */
482 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
483 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
484 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
485 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
cb49a5e9
RG		 486
487 /* ... and status */
488 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
489 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
490
491 dev_dbg(dev, "%s secs=%d, mins=%d, "
492 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
493 "alarm read", t->time.tm_sec, t->time.tm_min,
494 t->time.tm_hour, t->time.tm_mday,
495 t->enabled, t->pending);
496
497 return 0;
498}
499
74d88eb2 500static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 501{
11e5890b 502 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9
RG		 503 unsigned char *buf = ds1307->regs;
504 u8 control, status;
505 int ret;
506
507 if (!test_bit(HAS_ALARM, &ds1307->flags))
508 return -EINVAL;
509
510 dev_dbg(dev, "%s secs=%d, mins=%d, "
511 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
512 "alarm set", t->time.tm_sec, t->time.tm_min,
513 t->time.tm_hour, t->time.tm_mday,
514 t->enabled, t->pending);
515
516 /* read current status of both alarms and the chip */
11e5890b
HK		 517 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
518 if (ret) {
cb49a5e9 519 dev_err(dev, "%s error %d\n", "alarm write", ret);
11e5890b 520 return ret;
cb49a5e9
RG		 521 }
522 control = ds1307->regs[7];
523 status = ds1307->regs[8];
524
ff67abd2
RV		 525 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
526 &ds1307->regs[0], &ds1307->regs[4], control, status);
cb49a5e9
RG		 527
528 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG		 529 buf[0] = bin2bcd(t->time.tm_sec);
530 buf[1] = bin2bcd(t->time.tm_min);
531 buf[2] = bin2bcd(t->time.tm_hour);
532 buf[3] = bin2bcd(t->time.tm_mday);
533
534 /* set ALARM2 to non-garbage */
535 buf[4] = 0;
536 buf[5] = 0;
537 buf[6] = 0;
538
5919fb97 539 /* disable alarms */
cb49a5e9 540 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
cb49a5e9
RG		 541 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
542
11e5890b
HK		 543 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
544 if (ret) {
cb49a5e9 545 dev_err(dev, "can't set alarm time\n");
fed40b73 546 return ret;
cb49a5e9
RG		 547 }
548
5919fb97
NB		 549 /* optionally enable ALARM1 */
550 if (t->enabled) {
551 dev_dbg(dev, "alarm IRQ armed\n");
552 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
11e5890b 553 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, buf[7]);
5919fb97
NB		 554 }
555
cb49a5e9
RG		 556 return 0;
557}
558
16380c15 559static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9 560{
11e5890b
HK		 561 struct ds1307 *ds1307 = dev_get_drvdata(dev);
562 int control, ret;
cb49a5e9 563
16380c15
JS		 564 if (!test_bit(HAS_ALARM, &ds1307->flags))
565 return -ENOTTY;
cb49a5e9 566
11e5890b
HK		 567 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
568 if (ret)
16380c15 569 return ret;
cb49a5e9 570
16380c15 571 if (enabled)
11e5890b 572 control |= DS1337_BIT_A1IE;
16380c15 573 else
11e5890b 574 control &= ~DS1337_BIT_A1IE;
cb49a5e9 575
11e5890b 576 return regmap_write(ds1307->regmap, DS1337_REG_CONTROL, control);
cb49a5e9
RG		 577}
578
ff8371ac 579static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB		 580 .read_time = ds1307_get_time,
581 .set_time = ds1307_set_time,
74d88eb2
JR		 582 .read_alarm = ds1337_read_alarm,
583 .set_alarm = ds1337_set_alarm,
16380c15 584 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB		 585};
586
682d73f6
DB		 587/*----------------------------------------------------------------------*/
588
1d1945d2 589/*
f4199f85 590 * Alarm support for mcp794xx devices.
1d1945d2
SG		 591 */
592
e29385fa
K		 593#define MCP794XX_REG_WEEKDAY 0x3
594#define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
f4199f85
TN		 595#define MCP794XX_REG_CONTROL 0x07
596# define MCP794XX_BIT_ALM0_EN 0x10
597# define MCP794XX_BIT_ALM1_EN 0x20
598#define MCP794XX_REG_ALARM0_BASE 0x0a
599#define MCP794XX_REG_ALARM0_CTRL 0x0d
600#define MCP794XX_REG_ALARM1_BASE 0x11
601#define MCP794XX_REG_ALARM1_CTRL 0x14
602# define MCP794XX_BIT_ALMX_IF (1 << 3)
603# define MCP794XX_BIT_ALMX_C0 (1 << 4)
604# define MCP794XX_BIT_ALMX_C1 (1 << 5)
605# define MCP794XX_BIT_ALMX_C2 (1 << 6)
606# define MCP794XX_BIT_ALMX_POL (1 << 7)
607# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
608 MCP794XX_BIT_ALMX_C1 | \
609 MCP794XX_BIT_ALMX_C2)
610
2fb07a10 611static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
1d1945d2 612{
11e5890b 613 struct ds1307 *ds1307 = dev_id;
2fb07a10 614 struct mutex *lock = &ds1307->rtc->ops_lock;
1d1945d2
SG		 615 int reg, ret;
616
2fb07a10 617 mutex_lock(lock);
1d1945d2
SG		 618
619 /* Check and clear alarm 0 interrupt flag. */
11e5890b
HK		 620 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
621 if (ret)
1d1945d2 622 goto out;
f4199f85 623 if (!(reg & MCP794XX_BIT_ALMX_IF))
1d1945d2 624 goto out;
f4199f85 625 reg &= ~MCP794XX_BIT_ALMX_IF;
11e5890b
HK		 626 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
627 if (ret)
1d1945d2
SG		 628 goto out;
629
630 /* Disable alarm 0. */
11e5890b
HK		 631 ret = regmap_read(ds1307->regmap, MCP794XX_REG_CONTROL, &reg);
632 if (ret)
1d1945d2 633 goto out;
f4199f85 634 reg &= ~MCP794XX_BIT_ALM0_EN;
11e5890b
HK		 635 ret = regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, reg);
636 if (ret)
1d1945d2
SG		 637 goto out;
638
639 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
640
641out:
2fb07a10
FB		 642 mutex_unlock(lock);
643
644 return IRQ_HANDLED;
1d1945d2
SG		 645}
646
f4199f85 647static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2 648{
11e5890b 649 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1d1945d2
SG		 650 u8 *regs = ds1307->regs;
651 int ret;
652
653 if (!test_bit(HAS_ALARM, &ds1307->flags))
654 return -EINVAL;
655
656 /* Read control and alarm 0 registers. */
11e5890b
HK		 657 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
658 if (ret)
1d1945d2
SG		 659 return ret;
660
f4199f85 661 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
1d1945d2
SG		 662
663 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
664 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
665 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
666 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
667 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
668 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
669 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
670 t->time.tm_year = -1;
671 t->time.tm_yday = -1;
672 t->time.tm_isdst = -1;
673
674 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
675 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
676 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
677 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
f4199f85
TN		 678 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
679 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
680 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
1d1945d2
SG		 681
682 return 0;
683}
684
f4199f85 685static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2 686{
11e5890b 687 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1d1945d2
SG		 688 unsigned char *regs = ds1307->regs;
689 int ret;
690
691 if (!test_bit(HAS_ALARM, &ds1307->flags))
692 return -EINVAL;
693
694 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
695 "enabled=%d pending=%d\n", __func__,
696 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
697 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
698 t->enabled, t->pending);
699
700 /* Read control and alarm 0 registers. */
11e5890b
HK		 701 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
702 if (ret)
1d1945d2
SG		 703 return ret;
704
705 /* Set alarm 0, using 24-hour and day-of-month modes. */
706 regs[3] = bin2bcd(t->time.tm_sec);
707 regs[4] = bin2bcd(t->time.tm_min);
708 regs[5] = bin2bcd(t->time.tm_hour);
62c8c20a 709 regs[6] = bin2bcd(t->time.tm_wday + 1);
1d1945d2 710 regs[7] = bin2bcd(t->time.tm_mday);
62c8c20a 711 regs[8] = bin2bcd(t->time.tm_mon + 1);
1d1945d2
SG		 712
713 /* Clear the alarm 0 interrupt flag. */
f4199f85 714 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
1d1945d2 715 /* Set alarm match: second, minute, hour, day, date, month. */
f4199f85 716 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
e3edd671
NM		 717 /* Disable interrupt. We will not enable until completely programmed */
718 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 719
11e5890b
HK		 720 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
721 if (ret)
1d1945d2
SG		 722 return ret;
723
e3edd671
NM		 724 if (!t->enabled)
725 return 0;
726 regs[0] |= MCP794XX_BIT_ALM0_EN;
11e5890b 727 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
1d1945d2
SG		 728}
729
f4199f85 730static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
1d1945d2 731{
11e5890b
HK		 732 struct ds1307 *ds1307 = dev_get_drvdata(dev);
733 int reg, ret;
1d1945d2
SG		 734
735 if (!test_bit(HAS_ALARM, &ds1307->flags))
736 return -EINVAL;
737
11e5890b
HK		 738 ret = regmap_read(ds1307->regmap, MCP794XX_REG_CONTROL, &reg);
739 if (ret)
740 return ret;
1d1945d2
SG		 741
742 if (enabled)
f4199f85 743 reg |= MCP794XX_BIT_ALM0_EN;
1d1945d2 744 else
f4199f85 745 reg &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 746
11e5890b 747 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, reg);
1d1945d2
SG		 748}
749
f4199f85 750static const struct rtc_class_ops mcp794xx_rtc_ops = {
1d1945d2
SG		 751 .read_time = ds1307_get_time,
752 .set_time = ds1307_set_time,
f4199f85
TN		 753 .read_alarm = mcp794xx_read_alarm,
754 .set_alarm = mcp794xx_set_alarm,
755 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
1d1945d2
SG		 756};
757
758/*----------------------------------------------------------------------*/
759
682d73f6 760static ssize_t
2c3c8bea
CW		 761ds1307_nvram_read(struct file *filp, struct kobject *kobj,
762 struct bin_attribute *attr,
682d73f6
DB		 763 char *buf, loff_t off, size_t count)
764{
682d73f6 765 struct ds1307 *ds1307;
682d73f6
DB		 766 int result;
767
11e5890b 768 ds1307 = dev_get_drvdata(kobj_to_dev(kobj));
682d73f6 769
11e5890b
HK		 770 result = regmap_bulk_read(ds1307->regmap, ds1307->nvram_offset + off,
771 buf, count);
772 if (result)
773 dev_err(ds1307->dev, "%s error %d\n", "nvram read", result);
fed40b73 774 return result;
682d73f6
DB		 775}
776
777static ssize_t
2c3c8bea
CW		 778ds1307_nvram_write(struct file *filp, struct kobject *kobj,
779 struct bin_attribute *attr,
682d73f6
DB		 780 char *buf, loff_t off, size_t count)
781{
30e7b039 782 struct ds1307 *ds1307;
fed40b73 783 int result;
682d73f6 784
11e5890b 785 ds1307 = dev_get_drvdata(kobj_to_dev(kobj));
682d73f6 786
11e5890b
HK		 787 result = regmap_bulk_write(ds1307->regmap, ds1307->nvram_offset + off,
788 buf, count);
789 if (result) {
790 dev_err(ds1307->dev, "%s error %d\n", "nvram write", result);
fed40b73
BS		 791 return result;
792 }
793 return count;
682d73f6
DB		 794}
795
33b04b7b 796
682d73f6
DB		 797/*----------------------------------------------------------------------*/
798
11e5890b 799static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
33b04b7b
MV		 800 uint32_t ohms, bool diode)
801{
802 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
803 DS1307_TRICKLE_CHARGER_NO_DIODE;
804
805 switch (ohms) {
806 case 250:
807 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
808 break;
809 case 2000:
810 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
811 break;
812 case 4000:
813 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
814 break;
815 default:
11e5890b 816 dev_warn(ds1307->dev,
33b04b7b
MV		 817 "Unsupported ohm value %u in dt\n", ohms);
818 return 0;
819 }
820 return setup;
821}
822
11e5890b 823static void ds1307_trickle_init(struct ds1307 *ds1307,
9c19b893 824 struct chip_desc *chip)
33b04b7b
MV		 825{
826 uint32_t ohms = 0;
827 bool diode = true;
828
829 if (!chip->do_trickle_setup)
830 goto out;
11e5890b
HK		 831 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
832 &ohms))
33b04b7b 833 goto out;
11e5890b 834 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
33b04b7b 835 diode = false;
11e5890b 836 chip->trickle_charger_setup = chip->do_trickle_setup(ds1307,
33b04b7b
MV		 837 ohms, diode);
838out:
839 return;
840}
841
445c0207
AM		 842/*----------------------------------------------------------------------*/
843
844#ifdef CONFIG_RTC_DRV_DS1307_HWMON
845
846/*
847 * Temperature sensor support for ds3231 devices.
848 */
849
850#define DS3231_REG_TEMPERATURE 0x11
851
852/*
853 * A user-initiated temperature conversion is not started by this function,
854 * so the temperature is updated once every 64 seconds.
855 */
9a3dce62 856static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
445c0207
AM		 857{
858 struct ds1307 *ds1307 = dev_get_drvdata(dev);
859 u8 temp_buf[2];
860 s16 temp;
861 int ret;
862
11e5890b
HK		 863 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
864 temp_buf, sizeof(temp_buf));
865 if (ret)
445c0207 866 return ret;
445c0207
AM		 867 /*
868 * Temperature is represented as a 10-bit code with a resolution of
869 * 0.25 degree celsius and encoded in two's complement format.
870 */
871 temp = (temp_buf[0] << 8) | temp_buf[1];
872 temp >>= 6;
873 *mC = temp * 250;
874
875 return 0;
876}
877
878static ssize_t ds3231_hwmon_show_temp(struct device *dev,
879 struct device_attribute *attr, char *buf)
880{
881 int ret;
9a3dce62 882 s32 temp;
445c0207
AM		 883
884 ret = ds3231_hwmon_read_temp(dev, &temp);
885 if (ret)
886 return ret;
887
888 return sprintf(buf, "%d\n", temp);
889}
890static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, ds3231_hwmon_show_temp,
891 NULL, 0);
892
893static struct attribute *ds3231_hwmon_attrs[] = {
894 &sensor_dev_attr_temp1_input.dev_attr.attr,
895 NULL,
896};
897ATTRIBUTE_GROUPS(ds3231_hwmon);
898
899static void ds1307_hwmon_register(struct ds1307 *ds1307)
900{
901 struct device *dev;
902
903 if (ds1307->type != ds_3231)
904 return;
905
11e5890b 906 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
445c0207
AM		 907 ds1307, ds3231_hwmon_groups);
908 if (IS_ERR(dev)) {
11e5890b
HK		 909 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
910 PTR_ERR(dev));
445c0207
AM		 911 }
912}
913
914#else
915
916static void ds1307_hwmon_register(struct ds1307 *ds1307)
917{
918}
919
6c6ff145
AM		 920#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
921
922/*----------------------------------------------------------------------*/
923
924/*
925 * Square-wave output support for DS3231
926 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
927 */
928#ifdef CONFIG_COMMON_CLK
929
930enum {
931 DS3231_CLK_SQW = 0,
932 DS3231_CLK_32KHZ,
933};
934
935#define clk_sqw_to_ds1307(clk) \
936 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
937#define clk_32khz_to_ds1307(clk) \
938 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
939
940static int ds3231_clk_sqw_rates[] = {
941 1,
942 1024,
943 4096,
944 8192,
945};
946
947static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
948{
6c6ff145
AM		 949 struct mutex *lock = &ds1307->rtc->ops_lock;
950 int control;
951 int ret;
952
953 mutex_lock(lock);
954
11e5890b
HK		 955 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
956 if (ret)
6c6ff145 957 goto out;
6c6ff145
AM		 958
959 control &= ~mask;
960 control |= value;
961
11e5890b 962 ret = regmap_write(ds1307->regmap, DS1337_REG_CONTROL, control);
6c6ff145
AM		 963out:
964 mutex_unlock(lock);
965
966 return ret;
967}
968
969static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
970 unsigned long parent_rate)
971{
972 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 973 int control, ret;
6c6ff145
AM		 974 int rate_sel = 0;
975
11e5890b
HK		 976 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
977 if (ret)
978 return ret;
6c6ff145
AM		 979 if (control & DS1337_BIT_RS1)
980 rate_sel += 1;
981 if (control & DS1337_BIT_RS2)
982 rate_sel += 2;
983
984 return ds3231_clk_sqw_rates[rate_sel];
985}
986
987static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
988 unsigned long *prate)
989{
990 int i;
991
992 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
993 if (ds3231_clk_sqw_rates[i] <= rate)
994 return ds3231_clk_sqw_rates[i];
995 }
996
997 return 0;
998}
999
1000static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1001 unsigned long parent_rate)
1002{
1003 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1004 int control = 0;
1005 int rate_sel;
1006
1007 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1008 rate_sel++) {
1009 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1010 break;
1011 }
1012
1013 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1014 return -EINVAL;
1015
1016 if (rate_sel & 1)
1017 control |= DS1337_BIT_RS1;
1018 if (rate_sel & 2)
1019 control |= DS1337_BIT_RS2;
1020
1021 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1022 control);
1023}
1024
1025static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1026{
1027 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1028
1029 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1030}
1031
1032static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1033{
1034 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1035
1036 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1037}
1038
1039static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1040{
1041 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1042 int control, ret;
6c6ff145 1043
11e5890b
HK		 1044 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1045 if (ret)
1046 return ret;
6c6ff145
AM		 1047
1048 return !(control & DS1337_BIT_INTCN);
1049}
1050
1051static const struct clk_ops ds3231_clk_sqw_ops = {
1052 .prepare = ds3231_clk_sqw_prepare,
1053 .unprepare = ds3231_clk_sqw_unprepare,
1054 .is_prepared = ds3231_clk_sqw_is_prepared,
1055 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1056 .round_rate = ds3231_clk_sqw_round_rate,
1057 .set_rate = ds3231_clk_sqw_set_rate,
1058};
1059
1060static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1061 unsigned long parent_rate)
1062{
1063 return 32768;
1064}
1065
1066static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1067{
6c6ff145
AM		 1068 struct mutex *lock = &ds1307->rtc->ops_lock;
1069 int status;
1070 int ret;
1071
1072 mutex_lock(lock);
1073
11e5890b
HK		 1074 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1075 if (ret)
6c6ff145 1076 goto out;
6c6ff145
AM		 1077
1078 if (enable)
1079 status |= DS3231_BIT_EN32KHZ;
1080 else
1081 status &= ~DS3231_BIT_EN32KHZ;
1082
11e5890b 1083 ret = regmap_write(ds1307->regmap, DS1337_REG_STATUS, status);
6c6ff145
AM		 1084out:
1085 mutex_unlock(lock);
1086
1087 return ret;
1088}
1089
1090static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1091{
1092 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1093
1094 return ds3231_clk_32khz_control(ds1307, true);
1095}
1096
1097static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1098{
1099 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1100
1101 ds3231_clk_32khz_control(ds1307, false);
1102}
1103
1104static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1105{
1106 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
11e5890b 1107 int status, ret;
6c6ff145 1108
11e5890b
HK		 1109 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1110 if (ret)
1111 return ret;
6c6ff145
AM		 1112
1113 return !!(status & DS3231_BIT_EN32KHZ);
1114}
1115
1116static const struct clk_ops ds3231_clk_32khz_ops = {
1117 .prepare = ds3231_clk_32khz_prepare,
1118 .unprepare = ds3231_clk_32khz_unprepare,
1119 .is_prepared = ds3231_clk_32khz_is_prepared,
1120 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1121};
1122
1123static struct clk_init_data ds3231_clks_init[] = {
1124 [DS3231_CLK_SQW] = {
1125 .name = "ds3231_clk_sqw",
1126 .ops = &ds3231_clk_sqw_ops,
6c6ff145
AM		 1127 },
1128 [DS3231_CLK_32KHZ] = {
1129 .name = "ds3231_clk_32khz",
1130 .ops = &ds3231_clk_32khz_ops,
6c6ff145
AM		 1131 },
1132};
1133
1134static int ds3231_clks_register(struct ds1307 *ds1307)
1135{
11e5890b 1136 struct device_node *node = ds1307->dev->of_node;
6c6ff145
AM		 1137 struct clk_onecell_data *onecell;
1138 int i;
1139
11e5890b 1140 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
6c6ff145
AM		 1141 if (!onecell)
1142 return -ENOMEM;
1143
1144 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
11e5890b
HK		 1145 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1146 sizeof(onecell->clks[0]), GFP_KERNEL);
6c6ff145
AM		 1147 if (!onecell->clks)
1148 return -ENOMEM;
1149
1150 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1151 struct clk_init_data init = ds3231_clks_init[i];
1152
1153 /*
1154 * Interrupt signal due to alarm conditions and square-wave
1155 * output share same pin, so don't initialize both.
1156 */
1157 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1158 continue;
1159
1160 /* optional override of the clockname */
1161 of_property_read_string_index(node, "clock-output-names", i,
1162 &init.name);
1163 ds1307->clks[i].init = &init;
1164
11e5890b
HK		 1165 onecell->clks[i] = devm_clk_register(ds1307->dev,
1166 &ds1307->clks[i]);
6c6ff145
AM		 1167 if (IS_ERR(onecell->clks[i]))
1168 return PTR_ERR(onecell->clks[i]);
1169 }
1170
1171 if (!node)
1172 return 0;
1173
1174 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1175
1176 return 0;
1177}
1178
1179static void ds1307_clks_register(struct ds1307 *ds1307)
1180{
1181 int ret;
1182
1183 if (ds1307->type != ds_3231)
1184 return;
1185
1186 ret = ds3231_clks_register(ds1307);
1187 if (ret) {
11e5890b
HK		 1188 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1189 ret);
6c6ff145
AM		 1190 }
1191}
1192
1193#else
1194
1195static void ds1307_clks_register(struct ds1307 *ds1307)
1196{
1197}
1198
1199#endif /* CONFIG_COMMON_CLK */
445c0207 1200
11e5890b
HK		 1201static const struct regmap_config regmap_config = {
1202 .reg_bits = 8,
1203 .val_bits = 8,
1204 .max_register = 0x12,
1205};
1206
5a167f45
GKH		 1207static int ds1307_probe(struct i2c_client *client,
1208 const struct i2c_device_id *id)
1abb0dc9
DB		 1209{
1210 struct ds1307 *ds1307;
1211 int err = -ENODEV;
e29385fa 1212 int tmp, wday;
9c19b893 1213 struct chip_desc *chip;
c8b18da7 1214 bool want_irq = false;
8bc2a407 1215 bool ds1307_can_wakeup_device = false;
fed40b73 1216 unsigned char *buf;
01ce893d 1217 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
e29385fa
K		 1218 struct rtc_time tm;
1219 unsigned long timestamp;
1220
2fb07a10
FB		 1221 irq_handler_t irq_handler = ds1307_irq;
1222
97f902b7
WS		 1223 static const int bbsqi_bitpos[] = {
1224 [ds_1337] = 0,
1225 [ds_1339] = DS1339_BIT_BBSQI,
1226 [ds_3231] = DS3231_BIT_BBSQW,
1227 };
1d1945d2 1228 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1abb0dc9 1229
edca66d2 1230 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 1231 if (!ds1307)
c065f35c 1232 return -ENOMEM;
045e0e85 1233
11e5890b
HK		 1234 dev_set_drvdata(&client->dev, ds1307);
1235 ds1307->dev = &client->dev;
1236 ds1307->name = client->name;
1237 ds1307->irq = client->irq;
1238
1239 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1240 if (IS_ERR(ds1307->regmap)) {
1241 dev_err(ds1307->dev, "regmap allocation failed\n");
1242 return PTR_ERR(ds1307->regmap);
1243 }
33df2ee1 1244
11e5890b 1245 i2c_set_clientdata(client, ds1307);
7ef6d2c2
JMC		 1246
1247 if (client->dev.of_node) {
1248 ds1307->type = (enum ds_type)
1249 of_device_get_match_data(&client->dev);
1250 chip = &chips[ds1307->type];
1251 } else if (id) {
9c19b893
TH		 1252 chip = &chips[id->driver_data];
1253 ds1307->type = id->driver_data;
1254 } else {
1255 const struct acpi_device_id *acpi_id;
1256
1257 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
11e5890b 1258 ds1307->dev);
9c19b893
TH		 1259 if (!acpi_id)
1260 return -ENODEV;
1261 chip = &chips[acpi_id->driver_data];
1262 ds1307->type = acpi_id->driver_data;
1263 }
33df2ee1 1264
9c19b893 1265 if (!pdata)
11e5890b 1266 ds1307_trickle_init(ds1307, chip);
9c19b893 1267 else if (pdata->trickle_charger_setup)
33b04b7b
MV		 1268 chip->trickle_charger_setup = pdata->trickle_charger_setup;
1269
1270 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
11e5890b
HK		 1271 dev_dbg(ds1307->dev,
1272 "writing trickle charger info 0x%x to 0x%x\n",
33b04b7b
MV		 1273 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
1274 chip->trickle_charger_reg);
11e5890b 1275 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
33b04b7b
MV		 1276 DS13XX_TRICKLE_CHARGER_MAGIC |
1277 chip->trickle_charger_setup);
1278 }
eb86c306 1279
fed40b73 1280 buf = ds1307->regs;
045e0e85 1281
8bc2a407
ML		 1282#ifdef CONFIG_OF
1283/*
1284 * For devices with no IRQ directly connected to the SoC, the RTC chip
1285 * can be forced as a wakeup source by stating that explicitly in
1286 * the device's .dts file using the "wakeup-source" boolean property.
1287 * If the "wakeup-source" property is set, don't request an IRQ.
1288 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1289 * if supported by the RTC.
1290 */
1291 if (of_property_read_bool(client->dev.of_node, "wakeup-source")) {
1292 ds1307_can_wakeup_device = true;
1293 }
78aaa06d
AB		 1294 /* Intersil ISL12057 DT backward compatibility */
1295 if (of_property_read_bool(client->dev.of_node,
1296 "isil,irq2-can-wakeup-machine")) {
1297 ds1307_can_wakeup_device = true;
1298 }
8bc2a407
ML		 1299#endif
1300
045e0e85
DB		 1301 switch (ds1307->type) {
1302 case ds_1337:
1303 case ds_1339:
97f902b7 1304 case ds_3231:
be5f59f4 1305 /* get registers that the "rtc" read below won't read... */
11e5890b
HK		 1306 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1307 buf, 2);
1308 if (err) {
1309 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1310 goto exit;
1abb0dc9
DB		 1311 }
1312
be5f59f4
RG		 1313 /* oscillator off? turn it on, so clock can tick. */
1314 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG		 1315 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
1316
40ce972d 1317 /*
8bc2a407
ML		 1318 * Using IRQ or defined as wakeup-source?
1319 * Disable the square wave and both alarms.
97f902b7
WS		 1320 * For some variants, be sure alarms can trigger when we're
1321 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 1322 */
11e5890b
HK		 1323 if (chip->alarm && (ds1307->irq > 0 ||
1324 ds1307_can_wakeup_device)) {
97f902b7
WS		 1325 ds1307->regs[0] |= DS1337_BIT_INTCN
1326 | bbsqi_bitpos[ds1307->type];
cb49a5e9 1327 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
b24a7267
WS		 1328
1329 want_irq = true;
cb49a5e9
RG		 1330 }
1331
11e5890b
HK		 1332 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1333 ds1307->regs[0]);
be5f59f4
RG		 1334
1335 /* oscillator fault? clear flag, and warn */
1336 if (ds1307->regs[1] & DS1337_BIT_OSF) {
11e5890b
HK		 1337 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1338 ds1307->regs[1] & ~DS1337_BIT_OSF);
1339 dev_warn(ds1307->dev, "SET TIME!\n");
1abb0dc9 1340 }
045e0e85 1341 break;
a2166858
MF		 1342
1343 case rx_8025:
11e5890b
HK		 1344 err = regmap_bulk_read(ds1307->regmap,
1345 RX8025_REG_CTRL1 << 4 | 0x08, buf, 2);
1346 if (err) {
1347 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1348 goto exit;
a2166858
MF		 1349 }
1350
1351 /* oscillator off? turn it on, so clock can tick. */
1352 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
1353 ds1307->regs[1] |= RX8025_BIT_XST;
11e5890b
HK		 1354 regmap_write(ds1307->regmap,
1355 RX8025_REG_CTRL2 << 4 | 0x08,
1356 ds1307->regs[1]);
1357 dev_warn(ds1307->dev,
a2166858
MF		 1358 "oscillator stop detected - SET TIME!\n");
1359 }
1360
1361 if (ds1307->regs[1] & RX8025_BIT_PON) {
1362 ds1307->regs[1] &= ~RX8025_BIT_PON;
11e5890b
HK		 1363 regmap_write(ds1307->regmap,
1364 RX8025_REG_CTRL2 << 4 | 0x08,
1365 ds1307->regs[1]);
1366 dev_warn(ds1307->dev, "power-on detected\n");
a2166858
MF		 1367 }
1368
1369 if (ds1307->regs[1] & RX8025_BIT_VDET) {
1370 ds1307->regs[1] &= ~RX8025_BIT_VDET;
11e5890b
HK		 1371 regmap_write(ds1307->regmap,
1372 RX8025_REG_CTRL2 << 4 | 0x08,
1373 ds1307->regs[1]);
1374 dev_warn(ds1307->dev, "voltage drop detected\n");
a2166858
MF		 1375 }
1376
1377 /* make sure we are running in 24hour mode */
1378 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
1379 u8 hour;
1380
1381 /* switch to 24 hour mode */
11e5890b
HK		 1382 regmap_write(ds1307->regmap,
1383 RX8025_REG_CTRL1 << 4 | 0x08,
1384 ds1307->regs[0] | RX8025_BIT_2412);
1385
1386 err = regmap_bulk_read(ds1307->regmap,
1387 RX8025_REG_CTRL1 << 4 | 0x08,
1388 buf, 2);
1389 if (err) {
1390 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1391 goto exit;
a2166858
MF		 1392 }
1393
1394 /* correct hour */
1395 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1396 if (hour == 12)
1397 hour = 0;
1398 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1399 hour += 12;
1400
11e5890b
HK		 1401 regmap_write(ds1307->regmap,
1402 DS1307_REG_HOUR << 4 | 0x08, hour);
a2166858
MF		 1403 }
1404 break;
33df2ee1
JT		 1405 case ds_1388:
1406 ds1307->offset = 1; /* Seconds starts at 1 */
1407 break;
f4199f85
TN		 1408 case mcp794xx:
1409 rtc_ops = &mcp794xx_rtc_ops;
11e5890b 1410 if (ds1307->irq > 0 && chip->alarm) {
2fb07a10 1411 irq_handler = mcp794xx_irq;
1d1945d2
SG		 1412 want_irq = true;
1413 }
1414 break;
045e0e85
DB		 1415 default:
1416 break;
1417 }
1abb0dc9
DB		 1418
1419read_rtc:
1420 /* read RTC registers */
11e5890b
HK		 1421 err = regmap_bulk_read(ds1307->regmap, ds1307->offset, buf, 8);
1422 if (err) {
1423 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1424 goto exit;
1abb0dc9
DB		 1425 }
1426
40ce972d
DA		 1427 /*
1428 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB		 1429 * specify the extra bits as must-be-zero, but there are
1430 * still a few values that are clearly out-of-range.
1431 */
1432 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB		 1433 switch (ds1307->type) {
1434 case ds_1307:
8566f70c 1435 case m41t0:
045e0e85 1436 case m41t00:
be5f59f4 1437 /* clock halted? turn it on, so clock can tick. */
045e0e85 1438 if (tmp & DS1307_BIT_CH) {
11e5890b
HK		 1439 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1440 dev_warn(ds1307->dev, "SET TIME!\n");
045e0e85 1441 goto read_rtc;
1abb0dc9 1442 }
045e0e85 1443 break;
be5f59f4
RG		 1444 case ds_1338:
1445 /* clock halted? turn it on, so clock can tick. */
045e0e85 1446 if (tmp & DS1307_BIT_CH)
11e5890b 1447 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
be5f59f4
RG		 1448
1449 /* oscillator fault? clear flag, and warn */
1450 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
11e5890b
HK		 1451 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1452 ds1307->regs[DS1307_REG_CONTROL] &
1453 ~DS1338_BIT_OSF);
1454 dev_warn(ds1307->dev, "SET TIME!\n");
be5f59f4
RG		 1455 goto read_rtc;
1456 }
045e0e85 1457 break;
fcd8db00
R		 1458 case ds_1340:
1459 /* clock halted? turn it on, so clock can tick. */
1460 if (tmp & DS1340_BIT_nEOSC)
11e5890b 1461 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
fcd8db00 1462
11e5890b
HK		 1463 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1464 if (err) {
1465 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1466 goto exit;
fcd8db00
R		 1467 }
1468
1469 /* oscillator fault? clear flag, and warn */
1470 if (tmp & DS1340_BIT_OSF) {
11e5890b
HK		 1471 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1472 dev_warn(ds1307->dev, "SET TIME!\n");
fcd8db00 1473 }
43fcb815 1474 break;
f4199f85 1475 case mcp794xx:
43fcb815 1476 /* make sure that the backup battery is enabled */
f4199f85 1477 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
11e5890b
HK		 1478 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1479 ds1307->regs[DS1307_REG_WDAY] |
1480 MCP794XX_BIT_VBATEN);
43fcb815
DA		 1481 }
1482
1483 /* clock halted? turn it on, so clock can tick. */
f4199f85 1484 if (!(tmp & MCP794XX_BIT_ST)) {
11e5890b
HK		 1485 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1486 MCP794XX_BIT_ST);
1487 dev_warn(ds1307->dev, "SET TIME!\n");
43fcb815
DA		 1488 goto read_rtc;
1489 }
1490
fcd8db00 1491 break;
32d322bc 1492 default:
045e0e85 1493 break;
1abb0dc9 1494 }
045e0e85 1495
1abb0dc9 1496 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB		 1497 switch (ds1307->type) {
1498 case ds_1340:
8566f70c 1499 case m41t0:
c065f35c 1500 case m41t00:
40ce972d
DA		 1501 /*
1502 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1503 * systems that will run through year 2100.
1504 */
1505 break;
a2166858
MF		 1506 case rx_8025:
1507 break;
c065f35c
DB		 1508 default:
1509 if (!(tmp & DS1307_BIT_12HR))
1510 break;
1511
40ce972d
DA		 1512 /*
1513 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1514 * take note...
1515 */
fe20ba70 1516 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1517 if (tmp == 12)
1518 tmp = 0;
1519 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1520 tmp += 12;
11e5890b
HK		 1521 regmap_write(ds1307->regmap, ds1307->offset + DS1307_REG_HOUR,
1522 bin2bcd(tmp));
1abb0dc9
DB		 1523 }
1524
e29385fa
K		 1525 /*
1526 * Some IPs have weekday reset value = 0x1 which might not correct
1527 * hence compute the wday using the current date/month/year values
1528 */
11e5890b 1529 ds1307_get_time(ds1307->dev, &tm);
e29385fa
K		 1530 wday = tm.tm_wday;
1531 timestamp = rtc_tm_to_time64(&tm);
1532 rtc_time64_to_tm(timestamp, &tm);
1533
1534 /*
1535 * Check if reset wday is different from the computed wday
1536 * If different then set the wday which we computed using
1537 * timestamp
1538 */
1539 if (wday != tm.tm_wday) {
11e5890b 1540 regmap_read(ds1307->regmap, MCP794XX_REG_WEEKDAY, &wday);
e29385fa
K		 1541 wday = wday & ~MCP794XX_REG_WEEKDAY_WDAY_MASK;
1542 wday = wday | (tm.tm_wday + 1);
11e5890b 1543 regmap_write(ds1307->regmap, MCP794XX_REG_WEEKDAY, wday);
e29385fa
K		 1544 }
1545
3abb1ada 1546 if (want_irq) {
11e5890b 1547 device_set_wakeup_capable(ds1307->dev, true);
3abb1ada
SG		 1548 set_bit(HAS_ALARM, &ds1307->flags);
1549 }
11e5890b 1550 ds1307->rtc = devm_rtc_device_register(ds1307->dev, ds1307->name,
1d1945d2 1551 rtc_ops, THIS_MODULE);
1abb0dc9 1552 if (IS_ERR(ds1307->rtc)) {
4071ea25 1553 return PTR_ERR(ds1307->rtc);
1abb0dc9
DB		 1554 }
1555
11e5890b 1556 if (ds1307_can_wakeup_device && ds1307->irq <= 0) {
8bc2a407
ML		 1557 /* Disable request for an IRQ */
1558 want_irq = false;
11e5890b
HK		 1559 dev_info(ds1307->dev,
1560 "'wakeup-source' is set, request for an IRQ is disabled!\n");
8bc2a407
ML		 1561 /* We cannot support UIE mode if we do not have an IRQ line */
1562 ds1307->rtc->uie_unsupported = 1;
1563 }
1564
cb49a5e9 1565 if (want_irq) {
11e5890b
HK		 1566 err = devm_request_threaded_irq(ds1307->dev,
1567 ds1307->irq, NULL, irq_handler,
c5983191 1568 IRQF_SHARED | IRQF_ONESHOT,
11e5890b 1569 ds1307->rtc->name, ds1307);
cb49a5e9 1570 if (err) {
4071ea25 1571 client->irq = 0;
11e5890b 1572 device_set_wakeup_capable(ds1307->dev, false);
3abb1ada 1573 clear_bit(HAS_ALARM, &ds1307->flags);
11e5890b 1574 dev_err(ds1307->dev, "unable to request IRQ!\n");
3abb1ada 1575 } else
11e5890b 1576 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
cb49a5e9
RG		 1577 }
1578
9eab0a78 1579 if (chip->nvram_size) {
4071ea25 1580
11e5890b 1581 ds1307->nvram = devm_kzalloc(ds1307->dev,
edca66d2
JH		 1582 sizeof(struct bin_attribute),
1583 GFP_KERNEL);
9eab0a78 1584 if (!ds1307->nvram) {
11e5890b
HK		 1585 dev_err(ds1307->dev,
1586 "cannot allocate memory for nvram sysfs\n");
4071ea25
AZ		 1587 } else {
1588
1589 ds1307->nvram->attr.name = "nvram";
1590 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
1591
1592 sysfs_bin_attr_init(ds1307->nvram);
1593
1594 ds1307->nvram->read = ds1307_nvram_read;
1595 ds1307->nvram->write = ds1307_nvram_write;
1596 ds1307->nvram->size = chip->nvram_size;
1597 ds1307->nvram_offset = chip->nvram_offset;
1598
11e5890b 1599 err = sysfs_create_bin_file(&ds1307->dev->kobj,
4071ea25
AZ		 1600 ds1307->nvram);
1601 if (err) {
11e5890b 1602 dev_err(ds1307->dev,
4071ea25
AZ		 1603 "unable to create sysfs file: %s\n",
1604 ds1307->nvram->attr.name);
1605 } else {
1606 set_bit(HAS_NVRAM, &ds1307->flags);
11e5890b 1607 dev_info(ds1307->dev, "%zu bytes nvram\n",
4071ea25
AZ		 1608 ds1307->nvram->size);
1609 }
9eab0a78 1610 }
682d73f6
DB		 1611 }
1612
445c0207 1613 ds1307_hwmon_register(ds1307);
6c6ff145 1614 ds1307_clks_register(ds1307);
445c0207 1615
1abb0dc9
DB		 1616 return 0;
1617
edca66d2 1618exit:
1abb0dc9
DB		 1619 return err;
1620}
1621
5a167f45 1622static int ds1307_remove(struct i2c_client *client)
1abb0dc9 1623{
40ce972d 1624 struct ds1307 *ds1307 = i2c_get_clientdata(client);
cb49a5e9 1625
edca66d2 1626 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
11e5890b 1627 sysfs_remove_bin_file(&ds1307->dev->kobj, ds1307->nvram);
682d73f6 1628
1abb0dc9
DB		 1629 return 0;
1630}
1631
1632static struct i2c_driver ds1307_driver = {
1633 .driver = {
c065f35c 1634 .name = "rtc-ds1307",
7ef6d2c2 1635 .of_match_table = of_match_ptr(ds1307_of_match),
9c19b893 1636 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1abb0dc9 1637 },
c065f35c 1638 .probe = ds1307_probe,
5a167f45 1639 .remove = ds1307_remove,
3760f736 1640 .id_table = ds1307_id,
1abb0dc9
DB		 1641};
1642
0abc9201 1643module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 1644
1645MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1646MODULE_LICENSE("GPL");
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