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CommitLineData
1abb0dc9
DB
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
1abb0dc9
DB
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20
21
22
23/* We can't determine type by probing, but if we expect pre-Linux code
24 * to have set the chip up as a clock (turning on the oscillator and
25 * setting the date and time), Linux can ignore the non-clock features.
26 * That's a natural job for a factory or repair bench.
1abb0dc9
DB
27 */
28enum ds_type {
045e0e85
DB
29 ds_1307,
30 ds_1337,
31 ds_1338,
32 ds_1339,
33 ds_1340,
33df2ee1 34 ds_1388,
045e0e85 35 m41t00,
a2166858 36 rx_8025,
1abb0dc9
DB
37 // rs5c372 too? different address...
38};
39
1abb0dc9
DB
40
41/* RTC registers don't differ much, except for the century flag */
42#define DS1307_REG_SECS 0x00 /* 00-59 */
43# define DS1307_BIT_CH 0x80
be5f59f4 44# define DS1340_BIT_nEOSC 0x80
1abb0dc9
DB
45#define DS1307_REG_MIN 0x01 /* 00-59 */
46#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB
47# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
48# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB
49# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
50# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
51#define DS1307_REG_WDAY 0x03 /* 01-07 */
52#define DS1307_REG_MDAY 0x04 /* 01-31 */
53#define DS1307_REG_MONTH 0x05 /* 01-12 */
54# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
55#define DS1307_REG_YEAR 0x06 /* 00-99 */
56
57/* Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB
58 * start at 7, and they differ a LOT. Only control and status matter for
59 * basic RTC date and time functionality; be careful using them.
1abb0dc9 60 */
045e0e85 61#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 62# define DS1307_BIT_OUT 0x80
be5f59f4 63# define DS1338_BIT_OSF 0x20
1abb0dc9
DB
64# define DS1307_BIT_SQWE 0x10
65# define DS1307_BIT_RS1 0x02
66# define DS1307_BIT_RS0 0x01
67#define DS1337_REG_CONTROL 0x0e
68# define DS1337_BIT_nEOSC 0x80
cb49a5e9 69# define DS1339_BIT_BBSQI 0x20
1abb0dc9
DB
70# define DS1337_BIT_RS2 0x10
71# define DS1337_BIT_RS1 0x08
72# define DS1337_BIT_INTCN 0x04
73# define DS1337_BIT_A2IE 0x02
74# define DS1337_BIT_A1IE 0x01
045e0e85
DB
75#define DS1340_REG_CONTROL 0x07
76# define DS1340_BIT_OUT 0x80
77# define DS1340_BIT_FT 0x40
78# define DS1340_BIT_CALIB_SIGN 0x20
79# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG
80#define DS1340_REG_FLAG 0x09
81# define DS1340_BIT_OSF 0x80
1abb0dc9
DB
82#define DS1337_REG_STATUS 0x0f
83# define DS1337_BIT_OSF 0x80
84# define DS1337_BIT_A2I 0x02
85# define DS1337_BIT_A1I 0x01
cb49a5e9 86#define DS1339_REG_ALARM1_SECS 0x07
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DB
87#define DS1339_REG_TRICKLE 0x10
88
a2166858
MF
89#define RX8025_REG_CTRL1 0x0e
90# define RX8025_BIT_2412 0x20
91#define RX8025_REG_CTRL2 0x0f
92# define RX8025_BIT_PON 0x10
93# define RX8025_BIT_VDET 0x40
94# define RX8025_BIT_XST 0x20
1abb0dc9
DB
95
96
97struct ds1307 {
33df2ee1 98 u8 offset; /* register's offset */
cb49a5e9 99 u8 regs[11];
1abb0dc9 100 enum ds_type type;
cb49a5e9
RG
101 unsigned long flags;
102#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
103#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 104 struct i2c_client *client;
1abb0dc9 105 struct rtc_device *rtc;
cb49a5e9 106 struct work_struct work;
30e7b039
ES
107 s32 (*read_block_data)(struct i2c_client *client, u8 command,
108 u8 length, u8 *values);
109 s32 (*write_block_data)(struct i2c_client *client, u8 command,
110 u8 length, const u8 *values);
1abb0dc9
DB
111};
112
045e0e85 113struct chip_desc {
045e0e85
DB
114 unsigned nvram56:1;
115 unsigned alarm:1;
045e0e85
DB
116};
117
3760f736
JD
118static const struct chip_desc chips[] = {
119[ds_1307] = {
045e0e85 120 .nvram56 = 1,
3760f736
JD
121},
122[ds_1337] = {
045e0e85 123 .alarm = 1,
3760f736
JD
124},
125[ds_1338] = {
045e0e85 126 .nvram56 = 1,
3760f736
JD
127},
128[ds_1339] = {
045e0e85 129 .alarm = 1,
3760f736
JD
130},
131[ds_1340] = {
132},
133[m41t00] = {
a2166858
MF
134},
135[rx_8025] = {
045e0e85
DB
136}, };
137
3760f736
JD
138static const struct i2c_device_id ds1307_id[] = {
139 { "ds1307", ds_1307 },
140 { "ds1337", ds_1337 },
141 { "ds1338", ds_1338 },
142 { "ds1339", ds_1339 },
33df2ee1 143 { "ds1388", ds_1388 },
3760f736
JD
144 { "ds1340", ds_1340 },
145 { "m41t00", m41t00 },
a2166858 146 { "rx8025", rx_8025 },
3760f736
JD
147 { }
148};
149MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 150
cb49a5e9
RG
151/*----------------------------------------------------------------------*/
152
30e7b039
ES
153#define BLOCK_DATA_MAX_TRIES 10
154
155static s32 ds1307_read_block_data_once(struct i2c_client *client, u8 command,
156 u8 length, u8 *values)
157{
158 s32 i, data;
159
160 for (i = 0; i < length; i++) {
161 data = i2c_smbus_read_byte_data(client, command + i);
162 if (data < 0)
163 return data;
164 values[i] = data;
165 }
166 return i;
167}
168
169static s32 ds1307_read_block_data(struct i2c_client *client, u8 command,
170 u8 length, u8 *values)
171{
172 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
173 s32 ret;
174 int tries = 0;
175
176 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
177 ret = ds1307_read_block_data_once(client, command, length, values);
178 if (ret < 0)
179 return ret;
180 do {
181 if (++tries > BLOCK_DATA_MAX_TRIES) {
182 dev_err(&client->dev,
183 "ds1307_read_block_data failed\n");
184 return -EIO;
185 }
186 memcpy(oldvalues, values, length);
187 ret = ds1307_read_block_data_once(client, command, length,
188 values);
189 if (ret < 0)
190 return ret;
191 } while (memcmp(oldvalues, values, length));
192 return length;
193}
194
195static s32 ds1307_write_block_data(struct i2c_client *client, u8 command,
196 u8 length, const u8 *values)
197{
198 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
199 int tries = 0;
200
201 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
202 do {
203 s32 i, ret;
204
205 if (++tries > BLOCK_DATA_MAX_TRIES) {
206 dev_err(&client->dev,
207 "ds1307_write_block_data failed\n");
208 return -EIO;
209 }
210 for (i = 0; i < length; i++) {
211 ret = i2c_smbus_write_byte_data(client, command + i,
212 values[i]);
213 if (ret < 0)
214 return ret;
215 }
216 ret = ds1307_read_block_data_once(client, command, length,
217 currvalues);
218 if (ret < 0)
219 return ret;
220 } while (memcmp(currvalues, values, length));
221 return length;
222}
223
224/*----------------------------------------------------------------------*/
225
cb49a5e9
RG
226/*
227 * The IRQ logic includes a "real" handler running in IRQ context just
228 * long enough to schedule this workqueue entry. We need a task context
229 * to talk to the RTC, since I2C I/O calls require that; and disable the
230 * IRQ until we clear its status on the chip, so that this handler can
231 * work with any type of triggering (not just falling edge).
232 *
233 * The ds1337 and ds1339 both have two alarms, but we only use the first
234 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
235 * signal; ds1339 chips have only one alarm signal.
236 */
237static void ds1307_work(struct work_struct *work)
238{
239 struct ds1307 *ds1307;
240 struct i2c_client *client;
241 struct mutex *lock;
242 int stat, control;
243
244 ds1307 = container_of(work, struct ds1307, work);
245 client = ds1307->client;
246 lock = &ds1307->rtc->ops_lock;
247
248 mutex_lock(lock);
249 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
250 if (stat < 0)
251 goto out;
252
253 if (stat & DS1337_BIT_A1I) {
254 stat &= ~DS1337_BIT_A1I;
255 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
256
257 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
258 if (control < 0)
259 goto out;
260
261 control &= ~DS1337_BIT_A1IE;
262 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
263
264 /* rtc_update_irq() assumes that it is called
265 * from IRQ-disabled context.
266 */
267 local_irq_disable();
268 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
269 local_irq_enable();
270 }
271
272out:
273 if (test_bit(HAS_ALARM, &ds1307->flags))
274 enable_irq(client->irq);
275 mutex_unlock(lock);
276}
277
278static irqreturn_t ds1307_irq(int irq, void *dev_id)
279{
280 struct i2c_client *client = dev_id;
281 struct ds1307 *ds1307 = i2c_get_clientdata(client);
282
283 disable_irq_nosync(irq);
284 schedule_work(&ds1307->work);
285 return IRQ_HANDLED;
286}
287
288/*----------------------------------------------------------------------*/
289
1abb0dc9
DB
290static int ds1307_get_time(struct device *dev, struct rtc_time *t)
291{
292 struct ds1307 *ds1307 = dev_get_drvdata(dev);
293 int tmp;
294
045e0e85 295 /* read the RTC date and time registers all at once */
30e7b039 296 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 297 ds1307->offset, 7, ds1307->regs);
fed40b73 298 if (tmp != 7) {
1abb0dc9
DB
299 dev_err(dev, "%s error %d\n", "read", tmp);
300 return -EIO;
301 }
302
303 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
304 "read",
305 ds1307->regs[0], ds1307->regs[1],
306 ds1307->regs[2], ds1307->regs[3],
307 ds1307->regs[4], ds1307->regs[5],
308 ds1307->regs[6]);
309
fe20ba70
AB
310 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
311 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 312 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB
313 t->tm_hour = bcd2bin(tmp);
314 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
315 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 316 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 317 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB
318
319 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 320 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB
321
322 dev_dbg(dev, "%s secs=%d, mins=%d, "
323 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
324 "read", t->tm_sec, t->tm_min,
325 t->tm_hour, t->tm_mday,
326 t->tm_mon, t->tm_year, t->tm_wday);
327
045e0e85
DB
328 /* initial clock setting can be undefined */
329 return rtc_valid_tm(t);
1abb0dc9
DB
330}
331
332static int ds1307_set_time(struct device *dev, struct rtc_time *t)
333{
334 struct ds1307 *ds1307 = dev_get_drvdata(dev);
335 int result;
336 int tmp;
337 u8 *buf = ds1307->regs;
338
339 dev_dbg(dev, "%s secs=%d, mins=%d, "
340 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG
341 "write", t->tm_sec, t->tm_min,
342 t->tm_hour, t->tm_mday,
343 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 344
fe20ba70
AB
345 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
346 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
347 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
348 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
349 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
350 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB
351
352 /* assume 20YY not 19YY */
353 tmp = t->tm_year - 100;
fe20ba70 354 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 355
be5f59f4
RG
356 switch (ds1307->type) {
357 case ds_1337:
358 case ds_1339:
1abb0dc9 359 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG
360 break;
361 case ds_1340:
1abb0dc9
DB
362 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
363 | DS1340_BIT_CENTURY;
be5f59f4
RG
364 break;
365 default:
366 break;
367 }
1abb0dc9 368
1abb0dc9
DB
369 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
370 "write", buf[0], buf[1], buf[2], buf[3],
371 buf[4], buf[5], buf[6]);
372
33df2ee1
JT
373 result = ds1307->write_block_data(ds1307->client,
374 ds1307->offset, 7, buf);
fed40b73
BS
375 if (result < 0) {
376 dev_err(dev, "%s error %d\n", "write", result);
377 return result;
1abb0dc9
DB
378 }
379 return 0;
380}
381
74d88eb2 382static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
383{
384 struct i2c_client *client = to_i2c_client(dev);
385 struct ds1307 *ds1307 = i2c_get_clientdata(client);
386 int ret;
387
388 if (!test_bit(HAS_ALARM, &ds1307->flags))
389 return -EINVAL;
390
391 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 392 ret = ds1307->read_block_data(client,
fed40b73
BS
393 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
394 if (ret != 9) {
cb49a5e9
RG
395 dev_err(dev, "%s error %d\n", "alarm read", ret);
396 return -EIO;
397 }
398
399 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
400 "alarm read",
401 ds1307->regs[0], ds1307->regs[1],
402 ds1307->regs[2], ds1307->regs[3],
403 ds1307->regs[4], ds1307->regs[5],
404 ds1307->regs[6], ds1307->regs[7],
405 ds1307->regs[8]);
406
407 /* report alarm time (ALARM1); assume 24 hour and day-of-month modes,
408 * and that all four fields are checked matches
409 */
410 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
411 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
412 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
413 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
414 t->time.tm_mon = -1;
415 t->time.tm_year = -1;
416 t->time.tm_wday = -1;
417 t->time.tm_yday = -1;
418 t->time.tm_isdst = -1;
419
420 /* ... and status */
421 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
422 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
423
424 dev_dbg(dev, "%s secs=%d, mins=%d, "
425 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
426 "alarm read", t->time.tm_sec, t->time.tm_min,
427 t->time.tm_hour, t->time.tm_mday,
428 t->enabled, t->pending);
429
430 return 0;
431}
432
74d88eb2 433static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
434{
435 struct i2c_client *client = to_i2c_client(dev);
436 struct ds1307 *ds1307 = i2c_get_clientdata(client);
437 unsigned char *buf = ds1307->regs;
438 u8 control, status;
439 int ret;
440
441 if (!test_bit(HAS_ALARM, &ds1307->flags))
442 return -EINVAL;
443
444 dev_dbg(dev, "%s secs=%d, mins=%d, "
445 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
446 "alarm set", t->time.tm_sec, t->time.tm_min,
447 t->time.tm_hour, t->time.tm_mday,
448 t->enabled, t->pending);
449
450 /* read current status of both alarms and the chip */
30e7b039 451 ret = ds1307->read_block_data(client,
fed40b73
BS
452 DS1339_REG_ALARM1_SECS, 9, buf);
453 if (ret != 9) {
cb49a5e9
RG
454 dev_err(dev, "%s error %d\n", "alarm write", ret);
455 return -EIO;
456 }
457 control = ds1307->regs[7];
458 status = ds1307->regs[8];
459
460 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
461 "alarm set (old status)",
462 ds1307->regs[0], ds1307->regs[1],
463 ds1307->regs[2], ds1307->regs[3],
464 ds1307->regs[4], ds1307->regs[5],
465 ds1307->regs[6], control, status);
466
467 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG
468 buf[0] = bin2bcd(t->time.tm_sec);
469 buf[1] = bin2bcd(t->time.tm_min);
470 buf[2] = bin2bcd(t->time.tm_hour);
471 buf[3] = bin2bcd(t->time.tm_mday);
472
473 /* set ALARM2 to non-garbage */
474 buf[4] = 0;
475 buf[5] = 0;
476 buf[6] = 0;
477
478 /* optionally enable ALARM1 */
479 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
480 if (t->enabled) {
481 dev_dbg(dev, "alarm IRQ armed\n");
482 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
483 }
484 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
485
30e7b039 486 ret = ds1307->write_block_data(client,
fed40b73
BS
487 DS1339_REG_ALARM1_SECS, 9, buf);
488 if (ret < 0) {
cb49a5e9 489 dev_err(dev, "can't set alarm time\n");
fed40b73 490 return ret;
cb49a5e9
RG
491 }
492
493 return 0;
494}
495
496static int ds1307_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
497{
498 struct i2c_client *client = to_i2c_client(dev);
499 struct ds1307 *ds1307 = i2c_get_clientdata(client);
500 int ret;
501
502 switch (cmd) {
503 case RTC_AIE_OFF:
504 if (!test_bit(HAS_ALARM, &ds1307->flags))
505 return -ENOTTY;
506
507 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
508 if (ret < 0)
509 return ret;
510
511 ret &= ~DS1337_BIT_A1IE;
512
513 ret = i2c_smbus_write_byte_data(client,
514 DS1337_REG_CONTROL, ret);
515 if (ret < 0)
516 return ret;
517
518 break;
519
520 case RTC_AIE_ON:
521 if (!test_bit(HAS_ALARM, &ds1307->flags))
522 return -ENOTTY;
523
524 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
525 if (ret < 0)
526 return ret;
527
528 ret |= DS1337_BIT_A1IE;
529
530 ret = i2c_smbus_write_byte_data(client,
531 DS1337_REG_CONTROL, ret);
532 if (ret < 0)
533 return ret;
534
535 break;
536
537 default:
538 return -ENOIOCTLCMD;
539 }
540
541 return 0;
542}
543
ff8371ac 544static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB
545 .read_time = ds1307_get_time,
546 .set_time = ds1307_set_time,
74d88eb2
JR
547 .read_alarm = ds1337_read_alarm,
548 .set_alarm = ds1337_set_alarm,
cb49a5e9 549 .ioctl = ds1307_ioctl,
1abb0dc9
DB
550};
551
682d73f6
DB
552/*----------------------------------------------------------------------*/
553
554#define NVRAM_SIZE 56
555
556static ssize_t
557ds1307_nvram_read(struct kobject *kobj, struct bin_attribute *attr,
558 char *buf, loff_t off, size_t count)
559{
560 struct i2c_client *client;
561 struct ds1307 *ds1307;
682d73f6
DB
562 int result;
563
fcd8db00 564 client = kobj_to_i2c_client(kobj);
682d73f6
DB
565 ds1307 = i2c_get_clientdata(client);
566
567 if (unlikely(off >= NVRAM_SIZE))
568 return 0;
569 if ((off + count) > NVRAM_SIZE)
570 count = NVRAM_SIZE - off;
571 if (unlikely(!count))
572 return count;
573
30e7b039 574 result = ds1307->read_block_data(client, 8 + off, count, buf);
fed40b73 575 if (result < 0)
682d73f6 576 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 577 return result;
682d73f6
DB
578}
579
580static ssize_t
581ds1307_nvram_write(struct kobject *kobj, struct bin_attribute *attr,
582 char *buf, loff_t off, size_t count)
583{
584 struct i2c_client *client;
30e7b039 585 struct ds1307 *ds1307;
fed40b73 586 int result;
682d73f6 587
fcd8db00 588 client = kobj_to_i2c_client(kobj);
30e7b039 589 ds1307 = i2c_get_clientdata(client);
682d73f6
DB
590
591 if (unlikely(off >= NVRAM_SIZE))
592 return -EFBIG;
593 if ((off + count) > NVRAM_SIZE)
594 count = NVRAM_SIZE - off;
595 if (unlikely(!count))
596 return count;
597
30e7b039 598 result = ds1307->write_block_data(client, 8 + off, count, buf);
fed40b73
BS
599 if (result < 0) {
600 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
601 return result;
602 }
603 return count;
682d73f6
DB
604}
605
606static struct bin_attribute nvram = {
607 .attr = {
608 .name = "nvram",
609 .mode = S_IRUGO | S_IWUSR,
682d73f6
DB
610 },
611
612 .read = ds1307_nvram_read,
613 .write = ds1307_nvram_write,
614 .size = NVRAM_SIZE,
615};
616
617/*----------------------------------------------------------------------*/
618
1abb0dc9
DB
619static struct i2c_driver ds1307_driver;
620
d2653e92
JD
621static int __devinit ds1307_probe(struct i2c_client *client,
622 const struct i2c_device_id *id)
1abb0dc9
DB
623{
624 struct ds1307 *ds1307;
625 int err = -ENODEV;
1abb0dc9 626 int tmp;
3760f736 627 const struct chip_desc *chip = &chips[id->driver_data];
c065f35c 628 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
cb49a5e9 629 int want_irq = false;
fed40b73 630 unsigned char *buf;
1abb0dc9 631
30e7b039
ES
632 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
633 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB
634 return -EIO;
635
636 if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL)))
637 return -ENOMEM;
045e0e85 638
1abb0dc9 639 i2c_set_clientdata(client, ds1307);
33df2ee1
JT
640
641 ds1307->client = client;
642 ds1307->type = id->driver_data;
643 ds1307->offset = 0;
644
fed40b73 645 buf = ds1307->regs;
30e7b039
ES
646 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
647 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
648 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
649 } else {
650 ds1307->read_block_data = ds1307_read_block_data;
651 ds1307->write_block_data = ds1307_write_block_data;
652 }
045e0e85
DB
653
654 switch (ds1307->type) {
655 case ds_1337:
656 case ds_1339:
cb49a5e9
RG
657 /* has IRQ? */
658 if (ds1307->client->irq > 0 && chip->alarm) {
659 INIT_WORK(&ds1307->work, ds1307_work);
660 want_irq = true;
661 }
be5f59f4 662 /* get registers that the "rtc" read below won't read... */
30e7b039 663 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 664 DS1337_REG_CONTROL, 2, buf);
1abb0dc9
DB
665 if (tmp != 2) {
666 pr_debug("read error %d\n", tmp);
667 err = -EIO;
668 goto exit_free;
669 }
670
be5f59f4
RG
671 /* oscillator off? turn it on, so clock can tick. */
672 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG
673 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
674
675 /* Using IRQ? Disable the square wave and both alarms.
676 * For ds1339, be sure alarms can trigger when we're
677 * running on Vbackup (BBSQI); we assume ds1337 will
678 * ignore that bit
679 */
680 if (want_irq) {
681 ds1307->regs[0] |= DS1337_BIT_INTCN | DS1339_BIT_BBSQI;
682 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
683 }
684
685 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
686 ds1307->regs[0]);
be5f59f4
RG
687
688 /* oscillator fault? clear flag, and warn */
689 if (ds1307->regs[1] & DS1337_BIT_OSF) {
690 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
691 ds1307->regs[1] & ~DS1337_BIT_OSF);
692 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 693 }
045e0e85 694 break;
a2166858
MF
695
696 case rx_8025:
697 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
698 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
699 if (tmp != 2) {
700 pr_debug("read error %d\n", tmp);
701 err = -EIO;
702 goto exit_free;
703 }
704
705 /* oscillator off? turn it on, so clock can tick. */
706 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
707 ds1307->regs[1] |= RX8025_BIT_XST;
708 i2c_smbus_write_byte_data(client,
709 RX8025_REG_CTRL2 << 4 | 0x08,
710 ds1307->regs[1]);
711 dev_warn(&client->dev,
712 "oscillator stop detected - SET TIME!\n");
713 }
714
715 if (ds1307->regs[1] & RX8025_BIT_PON) {
716 ds1307->regs[1] &= ~RX8025_BIT_PON;
717 i2c_smbus_write_byte_data(client,
718 RX8025_REG_CTRL2 << 4 | 0x08,
719 ds1307->regs[1]);
720 dev_warn(&client->dev, "power-on detected\n");
721 }
722
723 if (ds1307->regs[1] & RX8025_BIT_VDET) {
724 ds1307->regs[1] &= ~RX8025_BIT_VDET;
725 i2c_smbus_write_byte_data(client,
726 RX8025_REG_CTRL2 << 4 | 0x08,
727 ds1307->regs[1]);
728 dev_warn(&client->dev, "voltage drop detected\n");
729 }
730
731 /* make sure we are running in 24hour mode */
732 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
733 u8 hour;
734
735 /* switch to 24 hour mode */
736 i2c_smbus_write_byte_data(client,
737 RX8025_REG_CTRL1 << 4 | 0x08,
738 ds1307->regs[0] |
739 RX8025_BIT_2412);
740
741 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
742 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
743 if (tmp != 2) {
744 pr_debug("read error %d\n", tmp);
745 err = -EIO;
746 goto exit_free;
747 }
748
749 /* correct hour */
750 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
751 if (hour == 12)
752 hour = 0;
753 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
754 hour += 12;
755
756 i2c_smbus_write_byte_data(client,
757 DS1307_REG_HOUR << 4 | 0x08,
758 hour);
759 }
760 break;
33df2ee1
JT
761 case ds_1388:
762 ds1307->offset = 1; /* Seconds starts at 1 */
763 break;
045e0e85
DB
764 default:
765 break;
766 }
1abb0dc9
DB
767
768read_rtc:
769 /* read RTC registers */
30e7b039 770 tmp = ds1307->read_block_data(ds1307->client, 0, 8, buf);
fed40b73 771 if (tmp != 8) {
1abb0dc9
DB
772 pr_debug("read error %d\n", tmp);
773 err = -EIO;
774 goto exit_free;
775 }
776
777 /* minimal sanity checking; some chips (like DS1340) don't
778 * specify the extra bits as must-be-zero, but there are
779 * still a few values that are clearly out-of-range.
780 */
781 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB
782 switch (ds1307->type) {
783 case ds_1307:
045e0e85 784 case m41t00:
be5f59f4 785 /* clock halted? turn it on, so clock can tick. */
045e0e85 786 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG
787 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
788 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 789 goto read_rtc;
1abb0dc9 790 }
045e0e85 791 break;
be5f59f4
RG
792 case ds_1338:
793 /* clock halted? turn it on, so clock can tick. */
045e0e85 794 if (tmp & DS1307_BIT_CH)
be5f59f4
RG
795 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
796
797 /* oscillator fault? clear flag, and warn */
798 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
799 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 800 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG
801 & ~DS1338_BIT_OSF);
802 dev_warn(&client->dev, "SET TIME!\n");
803 goto read_rtc;
804 }
045e0e85 805 break;
fcd8db00
R
806 case ds_1340:
807 /* clock halted? turn it on, so clock can tick. */
808 if (tmp & DS1340_BIT_nEOSC)
809 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
810
811 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
812 if (tmp < 0) {
813 pr_debug("read error %d\n", tmp);
814 err = -EIO;
815 goto exit_free;
816 }
817
818 /* oscillator fault? clear flag, and warn */
819 if (tmp & DS1340_BIT_OSF) {
820 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
821 dev_warn(&client->dev, "SET TIME!\n");
822 }
823 break;
a2166858 824 case rx_8025:
c065f35c
DB
825 case ds_1337:
826 case ds_1339:
33df2ee1 827 case ds_1388:
045e0e85 828 break;
1abb0dc9 829 }
045e0e85 830
1abb0dc9 831 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB
832 switch (ds1307->type) {
833 case ds_1340:
834 case m41t00:
835 /* NOTE: ignores century bits; fix before deploying
836 * systems that will run through year 2100.
837 */
838 break;
a2166858
MF
839 case rx_8025:
840 break;
c065f35c
DB
841 default:
842 if (!(tmp & DS1307_BIT_12HR))
843 break;
844
845 /* Be sure we're in 24 hour mode. Multi-master systems
846 * take note...
847 */
fe20ba70 848 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB
849 if (tmp == 12)
850 tmp = 0;
851 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
852 tmp += 12;
1abb0dc9
DB
853 i2c_smbus_write_byte_data(client,
854 DS1307_REG_HOUR,
fe20ba70 855 bin2bcd(tmp));
1abb0dc9
DB
856 }
857
1abb0dc9
DB
858 ds1307->rtc = rtc_device_register(client->name, &client->dev,
859 &ds13xx_rtc_ops, THIS_MODULE);
860 if (IS_ERR(ds1307->rtc)) {
861 err = PTR_ERR(ds1307->rtc);
862 dev_err(&client->dev,
863 "unable to register the class device\n");
c065f35c 864 goto exit_free;
1abb0dc9
DB
865 }
866
cb49a5e9
RG
867 if (want_irq) {
868 err = request_irq(client->irq, ds1307_irq, 0,
869 ds1307->rtc->name, client);
870 if (err) {
871 dev_err(&client->dev,
872 "unable to request IRQ!\n");
873 goto exit_irq;
874 }
875 set_bit(HAS_ALARM, &ds1307->flags);
876 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
877 }
878
682d73f6
DB
879 if (chip->nvram56) {
880 err = sysfs_create_bin_file(&client->dev.kobj, &nvram);
881 if (err == 0) {
cb49a5e9 882 set_bit(HAS_NVRAM, &ds1307->flags);
682d73f6
DB
883 dev_info(&client->dev, "56 bytes nvram\n");
884 }
885 }
886
1abb0dc9
DB
887 return 0;
888
cb49a5e9
RG
889exit_irq:
890 if (ds1307->rtc)
891 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
892exit_free:
893 kfree(ds1307);
1abb0dc9
DB
894 return err;
895}
896
c065f35c 897static int __devexit ds1307_remove(struct i2c_client *client)
1abb0dc9 898{
cb49a5e9
RG
899 struct ds1307 *ds1307 = i2c_get_clientdata(client);
900
901 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
902 free_irq(client->irq, client);
903 cancel_work_sync(&ds1307->work);
904 }
1abb0dc9 905
cb49a5e9 906 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
682d73f6
DB
907 sysfs_remove_bin_file(&client->dev.kobj, &nvram);
908
1abb0dc9 909 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
910 kfree(ds1307);
911 return 0;
912}
913
914static struct i2c_driver ds1307_driver = {
915 .driver = {
c065f35c 916 .name = "rtc-ds1307",
1abb0dc9
DB
917 .owner = THIS_MODULE,
918 },
c065f35c
DB
919 .probe = ds1307_probe,
920 .remove = __devexit_p(ds1307_remove),
3760f736 921 .id_table = ds1307_id,
1abb0dc9
DB
922};
923
924static int __init ds1307_init(void)
925{
926 return i2c_add_driver(&ds1307_driver);
927}
928module_init(ds1307_init);
929
930static void __exit ds1307_exit(void)
931{
932 i2c_del_driver(&ds1307_driver);
933}
934module_exit(ds1307_exit);
935
936MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
937MODULE_LICENSE("GPL");