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rtc: ds1307: factor out irq_handler to struct chip_desc
[mirror_ubuntu-jammy-kernel.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB		 1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
9c19b893 14#include <linux/acpi.h>
eac7237f
NM		 15#include <linux/bcd.h>
16#include <linux/i2c.h>
1abb0dc9 17#include <linux/init.h>
eac7237f 18#include <linux/module.h>
7ef6d2c2 19#include <linux/of_device.h>
eac7237f
NM		 20#include <linux/rtc/ds1307.h>
21#include <linux/rtc.h>
1abb0dc9 22#include <linux/slab.h>
1abb0dc9 23#include <linux/string.h>
445c0207
AM		 24#include <linux/hwmon.h>
25#include <linux/hwmon-sysfs.h>
6c6ff145 26#include <linux/clk-provider.h>
11e5890b 27#include <linux/regmap.h>
1abb0dc9 28
40ce972d
DA		 29/*
30 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 31 * to have set the chip up as a clock (turning on the oscillator and
32 * setting the date and time), Linux can ignore the non-clock features.
33 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 34 */
35enum ds_type {
045e0e85 36 ds_1307,
300a7735 37 ds_1308,
045e0e85
DB		 38 ds_1337,
39 ds_1338,
40 ds_1339,
41 ds_1340,
33df2ee1 42 ds_1388,
97f902b7 43 ds_3231,
8566f70c 44 m41t0,
045e0e85 45 m41t00,
f4199f85 46 mcp794xx,
a2166858 47 rx_8025,
ee0981be 48 rx_8130,
32d322bc 49 last_ds_type /* always last */
40ce972d 50 /* rs5c372 too? different address... */
1abb0dc9
DB		 51};
52
1abb0dc9
DB		 53
54/* RTC registers don't differ much, except for the century flag */
55#define DS1307_REG_SECS 0x00 /* 00-59 */
56# define DS1307_BIT_CH 0x80
be5f59f4 57# define DS1340_BIT_nEOSC 0x80
f4199f85 58# define MCP794XX_BIT_ST 0x80
1abb0dc9 59#define DS1307_REG_MIN 0x01 /* 00-59 */
8566f70c 60# define M41T0_BIT_OF 0x80
1abb0dc9 61#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 62# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 64# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 67# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 68#define DS1307_REG_MDAY 0x04 /* 01-31 */
69#define DS1307_REG_MONTH 0x05 /* 01-12 */
70# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71#define DS1307_REG_YEAR 0x06 /* 00-99 */
72
40ce972d
DA		 73/*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
1abb0dc9 77 */
045e0e85 78#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 79# define DS1307_BIT_OUT 0x80
be5f59f4 80# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 81# define DS1307_BIT_SQWE 0x10
82# define DS1307_BIT_RS1 0x02
83# define DS1307_BIT_RS0 0x01
84#define DS1337_REG_CONTROL 0x0e
85# define DS1337_BIT_nEOSC 0x80
cb49a5e9 86# define DS1339_BIT_BBSQI 0x20
97f902b7 87# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 88# define DS1337_BIT_RS2 0x10
89# define DS1337_BIT_RS1 0x08
90# define DS1337_BIT_INTCN 0x04
91# define DS1337_BIT_A2IE 0x02
92# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 93#define DS1340_REG_CONTROL 0x07
94# define DS1340_BIT_OUT 0x80
95# define DS1340_BIT_FT 0x40
96# define DS1340_BIT_CALIB_SIGN 0x20
97# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 98#define DS1340_REG_FLAG 0x09
99# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 100#define DS1337_REG_STATUS 0x0f
101# define DS1337_BIT_OSF 0x80
6c6ff145 102# define DS3231_BIT_EN32KHZ 0x08
1abb0dc9
DB		 103# define DS1337_BIT_A2I 0x02
104# define DS1337_BIT_A1I 0x01
cb49a5e9 105#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 106
107#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 108
a2166858
MF		 109#define RX8025_REG_CTRL1 0x0e
110# define RX8025_BIT_2412 0x20
111#define RX8025_REG_CTRL2 0x0f
112# define RX8025_BIT_PON 0x10
113# define RX8025_BIT_VDET 0x40
114# define RX8025_BIT_XST 0x20
1abb0dc9
DB		 115
116
117struct ds1307 {
33df2ee1 118 u8 offset; /* register's offset */
cb49a5e9 119 u8 regs[11];
9eab0a78 120 u16 nvram_offset;
abc925f7 121 struct nvmem_config nvmem_cfg;
1abb0dc9 122 enum ds_type type;
cb49a5e9
RG		 123 unsigned long flags;
124#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
125#define HAS_ALARM 1 /* bit 1 == irq claimed */
11e5890b
HK		 126 struct device *dev;
127 struct regmap *regmap;
128 const char *name;
1abb0dc9 129 struct rtc_device *rtc;
6c6ff145
AM		 130#ifdef CONFIG_COMMON_CLK
131 struct clk_hw clks[2];
132#endif
1abb0dc9
DB		 133};
134
045e0e85 135struct chip_desc {
045e0e85 136 unsigned alarm:1;
9eab0a78
AB		 137 u16 nvram_offset;
138 u16 nvram_size;
e48585de
HK		 139 u8 century_reg;
140 u8 century_enable_bit;
141 u8 century_bit;
0b6ee805 142 u8 bbsqi_bit;
45947127 143 irq_handler_t irq_handler;
eb86c306 144 u16 trickle_charger_reg;
11e5890b
HK		 145 u8 (*do_trickle_setup)(struct ds1307 *, uint32_t,
146 bool);
045e0e85
DB		 147};
148
11e5890b 149static u8 do_trickle_setup_ds1339(struct ds1307 *, uint32_t ohms, bool diode);
45947127
HK		 150static irqreturn_t rx8130_irq(int irq, void *dev_id);
151static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
33b04b7b 152
7624df48 153static const struct chip_desc chips[last_ds_type] = {
32d322bc 154 [ds_1307] = {
9eab0a78
AB		 155 .nvram_offset = 8,
156 .nvram_size = 56,
32d322bc 157 },
300a7735
SN		 158 [ds_1308] = {
159 .nvram_offset = 8,
160 .nvram_size = 56,
161 },
32d322bc
WS		 162 [ds_1337] = {
163 .alarm = 1,
e48585de
HK		 164 .century_reg = DS1307_REG_MONTH,
165 .century_bit = DS1337_BIT_CENTURY,
32d322bc
WS		 166 },
167 [ds_1338] = {
9eab0a78
AB		 168 .nvram_offset = 8,
169 .nvram_size = 56,
32d322bc
WS		 170 },
171 [ds_1339] = {
172 .alarm = 1,
e48585de
HK		 173 .century_reg = DS1307_REG_MONTH,
174 .century_bit = DS1337_BIT_CENTURY,
0b6ee805 175 .bbsqi_bit = DS1339_BIT_BBSQI,
eb86c306 176 .trickle_charger_reg = 0x10,
33b04b7b 177 .do_trickle_setup = &do_trickle_setup_ds1339,
eb86c306
WS		 178 },
179 [ds_1340] = {
e48585de
HK		 180 .century_reg = DS1307_REG_HOUR,
181 .century_enable_bit = DS1340_BIT_CENTURY_EN,
182 .century_bit = DS1340_BIT_CENTURY,
eb86c306
WS		 183 .trickle_charger_reg = 0x08,
184 },
185 [ds_1388] = {
186 .trickle_charger_reg = 0x0a,
32d322bc
WS		 187 },
188 [ds_3231] = {
189 .alarm = 1,
e48585de
HK		 190 .century_reg = DS1307_REG_MONTH,
191 .century_bit = DS1337_BIT_CENTURY,
0b6ee805 192 .bbsqi_bit = DS3231_BIT_BBSQW,
32d322bc 193 },
ee0981be
MV		 194 [rx_8130] = {
195 .alarm = 1,
196 /* this is battery backed SRAM */
197 .nvram_offset = 0x20,
198 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
45947127 199 .irq_handler = rx8130_irq,
ee0981be 200 },
f4199f85 201 [mcp794xx] = {
1d1945d2 202 .alarm = 1,
9eab0a78
AB		 203 /* this is battery backed SRAM */
204 .nvram_offset = 0x20,
205 .nvram_size = 0x40,
45947127 206 .irq_handler = mcp794xx_irq,
9eab0a78 207 },
32d322bc 208};
045e0e85 209
3760f736
JD		 210static const struct i2c_device_id ds1307_id[] = {
211 { "ds1307", ds_1307 },
300a7735 212 { "ds1308", ds_1308 },
3760f736
JD		 213 { "ds1337", ds_1337 },
214 { "ds1338", ds_1338 },
215 { "ds1339", ds_1339 },
33df2ee1 216 { "ds1388", ds_1388 },
3760f736 217 { "ds1340", ds_1340 },
97f902b7 218 { "ds3231", ds_3231 },
8566f70c 219 { "m41t0", m41t0 },
3760f736 220 { "m41t00", m41t00 },
f4199f85
TN		 221 { "mcp7940x", mcp794xx },
222 { "mcp7941x", mcp794xx },
31c1771c 223 { "pt7c4338", ds_1307 },
a2166858 224 { "rx8025", rx_8025 },
78aaa06d 225 { "isl12057", ds_1337 },
ee0981be 226 { "rx8130", rx_8130 },
3760f736
JD		 227 { }
228};
229MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 230
7ef6d2c2
JMC		 231#ifdef CONFIG_OF
232static const struct of_device_id ds1307_of_match[] = {
233 {
234 .compatible = "dallas,ds1307",
235 .data = (void *)ds_1307
236 },
300a7735
SN		 237 {
238 .compatible = "dallas,ds1308",
239 .data = (void *)ds_1308
240 },
7ef6d2c2
JMC		 241 {
242 .compatible = "dallas,ds1337",
243 .data = (void *)ds_1337
244 },
245 {
246 .compatible = "dallas,ds1338",
247 .data = (void *)ds_1338
248 },
249 {
250 .compatible = "dallas,ds1339",
251 .data = (void *)ds_1339
252 },
253 {
254 .compatible = "dallas,ds1388",
255 .data = (void *)ds_1388
256 },
257 {
258 .compatible = "dallas,ds1340",
259 .data = (void *)ds_1340
260 },
261 {
262 .compatible = "maxim,ds3231",
263 .data = (void *)ds_3231
264 },
db2f8141
AB		 265 {
266 .compatible = "st,m41t0",
267 .data = (void *)m41t00
268 },
7ef6d2c2
JMC		 269 {
270 .compatible = "st,m41t00",
271 .data = (void *)m41t00
272 },
273 {
274 .compatible = "microchip,mcp7940x",
275 .data = (void *)mcp794xx
276 },
277 {
278 .compatible = "microchip,mcp7941x",
279 .data = (void *)mcp794xx
280 },
281 {
282 .compatible = "pericom,pt7c4338",
283 .data = (void *)ds_1307
284 },
285 {
286 .compatible = "epson,rx8025",
287 .data = (void *)rx_8025
288 },
289 {
290 .compatible = "isil,isl12057",
291 .data = (void *)ds_1337
292 },
293 { }
294};
295MODULE_DEVICE_TABLE(of, ds1307_of_match);
296#endif
297
9c19b893
TH		 298#ifdef CONFIG_ACPI
299static const struct acpi_device_id ds1307_acpi_ids[] = {
300 { .id = "DS1307", .driver_data = ds_1307 },
300a7735 301 { .id = "DS1308", .driver_data = ds_1308 },
9c19b893
TH		 302 { .id = "DS1337", .driver_data = ds_1337 },
303 { .id = "DS1338", .driver_data = ds_1338 },
304 { .id = "DS1339", .driver_data = ds_1339 },
305 { .id = "DS1388", .driver_data = ds_1388 },
306 { .id = "DS1340", .driver_data = ds_1340 },
307 { .id = "DS3231", .driver_data = ds_3231 },
8566f70c 308 { .id = "M41T0", .driver_data = m41t0 },
9c19b893
TH		 309 { .id = "M41T00", .driver_data = m41t00 },
310 { .id = "MCP7940X", .driver_data = mcp794xx },
311 { .id = "MCP7941X", .driver_data = mcp794xx },
312 { .id = "PT7C4338", .driver_data = ds_1307 },
313 { .id = "RX8025", .driver_data = rx_8025 },
314 { .id = "ISL12057", .driver_data = ds_1337 },
315 { }
316};
317MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
318#endif
319
cb49a5e9 320/*
cb49a5e9
RG		 321 * The ds1337 and ds1339 both have two alarms, but we only use the first
322 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
323 * signal; ds1339 chips have only one alarm signal.
324 */
2fb07a10 325static irqreturn_t ds1307_irq(int irq, void *dev_id)
cb49a5e9 326{
11e5890b 327 struct ds1307 *ds1307 = dev_id;
2fb07a10 328 struct mutex *lock = &ds1307->rtc->ops_lock;
078f3f64 329 int stat, ret;
cb49a5e9 330
cb49a5e9 331 mutex_lock(lock);
11e5890b
HK		 332 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
333 if (ret)
cb49a5e9
RG		 334 goto out;
335
336 if (stat & DS1337_BIT_A1I) {
337 stat &= ~DS1337_BIT_A1I;
11e5890b 338 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
cb49a5e9 339
078f3f64
HK		 340 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
341 DS1337_BIT_A1IE, 0);
11e5890b 342 if (ret)
cb49a5e9
RG		 343 goto out;
344
cb49a5e9 345 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG		 346 }
347
348out:
cb49a5e9 349 mutex_unlock(lock);
cb49a5e9 350
cb49a5e9
RG		 351 return IRQ_HANDLED;
352}
353
354/*----------------------------------------------------------------------*/
355
1abb0dc9
DB		 356static int ds1307_get_time(struct device *dev, struct rtc_time *t)
357{
358 struct ds1307 *ds1307 = dev_get_drvdata(dev);
11e5890b 359 int tmp, ret;
e48585de 360 const struct chip_desc *chip = &chips[ds1307->type];
1abb0dc9 361
045e0e85 362 /* read the RTC date and time registers all at once */
11e5890b
HK		 363 ret = regmap_bulk_read(ds1307->regmap, ds1307->offset, ds1307->regs, 7);
364 if (ret) {
365 dev_err(dev, "%s error %d\n", "read", ret);
366 return ret;
1abb0dc9
DB		 367 }
368
01a4ca16 369 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
1abb0dc9 370
8566f70c
SA		 371 /* if oscillator fail bit is set, no data can be trusted */
372 if (ds1307->type == m41t0 &&
373 ds1307->regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
374 dev_warn_once(dev, "oscillator failed, set time!\n");
375 return -EINVAL;
376 }
377
fe20ba70
AB		 378 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
379 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 380 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB		 381 t->tm_hour = bcd2bin(tmp);
382 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
383 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 384 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 385 t->tm_mon = bcd2bin(tmp) - 1;
fe20ba70 386 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9 387
e48585de
HK		 388 if (ds1307->regs[chip->century_reg] & chip->century_bit &&
389 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
390 t->tm_year += 100;
50d6c0ea 391
1abb0dc9
DB		 392 dev_dbg(dev, "%s secs=%d, mins=%d, "
393 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
394 "read", t->tm_sec, t->tm_min,
395 t->tm_hour, t->tm_mday,
396 t->tm_mon, t->tm_year, t->tm_wday);
397
045e0e85
DB		 398 /* initial clock setting can be undefined */
399 return rtc_valid_tm(t);
1abb0dc9
DB		 400}
401
402static int ds1307_set_time(struct device *dev, struct rtc_time *t)
403{
404 struct ds1307 *ds1307 = dev_get_drvdata(dev);
e48585de 405 const struct chip_desc *chip = &chips[ds1307->type];
1abb0dc9
DB		 406 int result;
407 int tmp;
408 u8 *buf = ds1307->regs;
409
410 dev_dbg(dev, "%s secs=%d, mins=%d, "
411 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 412 "write", t->tm_sec, t->tm_min,
413 t->tm_hour, t->tm_mday,
414 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 415
50d6c0ea
AB		 416 if (t->tm_year < 100)
417 return -EINVAL;
418
e48585de
HK		 419#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
420 if (t->tm_year > (chip->century_bit ? 299 : 199))
421 return -EINVAL;
50d6c0ea 422#else
e48585de 423 if (t->tm_year > 199)
50d6c0ea
AB		 424 return -EINVAL;
425#endif
426
fe20ba70
AB		 427 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
428 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
429 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
430 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
431 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
432 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 433
434 /* assume 20YY not 19YY */
435 tmp = t->tm_year - 100;
fe20ba70 436 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 437
e48585de
HK		 438 if (chip->century_enable_bit)
439 buf[chip->century_reg] |= chip->century_enable_bit;
440 if (t->tm_year > 199 && chip->century_bit)
441 buf[chip->century_reg] |= chip->century_bit;
442
443 if (ds1307->type == mcp794xx) {
40ce972d
DA		 444 /*
445 * these bits were cleared when preparing the date/time
446 * values and need to be set again before writing the
447 * buffer out to the device.
448 */
f4199f85
TN		 449 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
450 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
be5f59f4 451 }
1abb0dc9 452
01a4ca16 453 dev_dbg(dev, "%s: %7ph\n", "write", buf);
1abb0dc9 454
11e5890b
HK		 455 result = regmap_bulk_write(ds1307->regmap, ds1307->offset, buf, 7);
456 if (result) {
fed40b73
BS		 457 dev_err(dev, "%s error %d\n", "write", result);
458 return result;
1abb0dc9
DB		 459 }
460 return 0;
461}
462
74d88eb2 463static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 464{
11e5890b 465 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9
RG		 466 int ret;
467
468 if (!test_bit(HAS_ALARM, &ds1307->flags))
469 return -EINVAL;
470
471 /* read all ALARM1, ALARM2, and status registers at once */
11e5890b
HK		 472 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
473 ds1307->regs, 9);
474 if (ret) {
cb49a5e9 475 dev_err(dev, "%s error %d\n", "alarm read", ret);
11e5890b 476 return ret;
cb49a5e9
RG		 477 }
478
ff67abd2
RV		 479 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
480 &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]);
cb49a5e9 481
40ce972d
DA		 482 /*
483 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 484 * and that all four fields are checked matches
485 */
486 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
487 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
488 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
489 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
cb49a5e9
RG		 490
491 /* ... and status */
492 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
493 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
494
495 dev_dbg(dev, "%s secs=%d, mins=%d, "
496 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
497 "alarm read", t->time.tm_sec, t->time.tm_min,
498 t->time.tm_hour, t->time.tm_mday,
499 t->enabled, t->pending);
500
501 return 0;
502}
503
74d88eb2 504static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 505{
11e5890b 506 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9
RG		 507 unsigned char *buf = ds1307->regs;
508 u8 control, status;
509 int ret;
510
511 if (!test_bit(HAS_ALARM, &ds1307->flags))
512 return -EINVAL;
513
514 dev_dbg(dev, "%s secs=%d, mins=%d, "
515 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
516 "alarm set", t->time.tm_sec, t->time.tm_min,
517 t->time.tm_hour, t->time.tm_mday,
518 t->enabled, t->pending);
519
520 /* read current status of both alarms and the chip */
11e5890b
HK		 521 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
522 if (ret) {
cb49a5e9 523 dev_err(dev, "%s error %d\n", "alarm write", ret);
11e5890b 524 return ret;
cb49a5e9
RG		 525 }
526 control = ds1307->regs[7];
527 status = ds1307->regs[8];
528
ff67abd2
RV		 529 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
530 &ds1307->regs[0], &ds1307->regs[4], control, status);
cb49a5e9
RG		 531
532 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG		 533 buf[0] = bin2bcd(t->time.tm_sec);
534 buf[1] = bin2bcd(t->time.tm_min);
535 buf[2] = bin2bcd(t->time.tm_hour);
536 buf[3] = bin2bcd(t->time.tm_mday);
537
538 /* set ALARM2 to non-garbage */
539 buf[4] = 0;
540 buf[5] = 0;
541 buf[6] = 0;
542
5919fb97 543 /* disable alarms */
cb49a5e9 544 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
cb49a5e9
RG		 545 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
546
11e5890b
HK		 547 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
548 if (ret) {
cb49a5e9 549 dev_err(dev, "can't set alarm time\n");
fed40b73 550 return ret;
cb49a5e9
RG		 551 }
552
5919fb97
NB		 553 /* optionally enable ALARM1 */
554 if (t->enabled) {
555 dev_dbg(dev, "alarm IRQ armed\n");
556 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
11e5890b 557 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, buf[7]);
5919fb97
NB		 558 }
559
cb49a5e9
RG		 560 return 0;
561}
562
16380c15 563static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9 564{
11e5890b 565 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 566
16380c15
JS		 567 if (!test_bit(HAS_ALARM, &ds1307->flags))
568 return -ENOTTY;
cb49a5e9 569
078f3f64
HK		 570 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
571 DS1337_BIT_A1IE,
572 enabled ? DS1337_BIT_A1IE : 0);
cb49a5e9
RG		 573}
574
ff8371ac 575static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB		 576 .read_time = ds1307_get_time,
577 .set_time = ds1307_set_time,
74d88eb2
JR		 578 .read_alarm = ds1337_read_alarm,
579 .set_alarm = ds1337_set_alarm,
16380c15 580 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB		 581};
582
682d73f6
DB		 583/*----------------------------------------------------------------------*/
584
ee0981be
MV		 585/*
586 * Alarm support for rx8130 devices.
587 */
588
589#define RX8130_REG_ALARM_MIN 0x07
590#define RX8130_REG_ALARM_HOUR 0x08
591#define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
592#define RX8130_REG_EXTENSION 0x0c
593#define RX8130_REG_EXTENSION_WADA (1 << 3)
594#define RX8130_REG_FLAG 0x0d
595#define RX8130_REG_FLAG_AF (1 << 3)
596#define RX8130_REG_CONTROL0 0x0e
597#define RX8130_REG_CONTROL0_AIE (1 << 3)
598
599static irqreturn_t rx8130_irq(int irq, void *dev_id)
600{
601 struct ds1307 *ds1307 = dev_id;
602 struct mutex *lock = &ds1307->rtc->ops_lock;
603 u8 ctl[3];
604 int ret;
605
606 mutex_lock(lock);
607
608 /* Read control registers. */
609 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
610 if (ret < 0)
611 goto out;
612 if (!(ctl[1] & RX8130_REG_FLAG_AF))
613 goto out;
614 ctl[1] &= ~RX8130_REG_FLAG_AF;
615 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
616
617 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
618 if (ret < 0)
619 goto out;
620
621 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
622
623out:
624 mutex_unlock(lock);
625
626 return IRQ_HANDLED;
627}
628
629static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
630{
631 struct ds1307 *ds1307 = dev_get_drvdata(dev);
632 u8 ald[3], ctl[3];
633 int ret;
634
635 if (!test_bit(HAS_ALARM, &ds1307->flags))
636 return -EINVAL;
637
638 /* Read alarm registers. */
639 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 3);
640 if (ret < 0)
641 return ret;
642
643 /* Read control registers. */
644 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
645 if (ret < 0)
646 return ret;
647
648 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
649 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
650
651 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
652 t->time.tm_sec = -1;
653 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
654 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
655 t->time.tm_wday = -1;
656 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
657 t->time.tm_mon = -1;
658 t->time.tm_year = -1;
659 t->time.tm_yday = -1;
660 t->time.tm_isdst = -1;
661
662 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
663 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
664 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
665
666 return 0;
667}
668
669static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
670{
671 struct ds1307 *ds1307 = dev_get_drvdata(dev);
672 u8 ald[3], ctl[3];
673 int ret;
674
675 if (!test_bit(HAS_ALARM, &ds1307->flags))
676 return -EINVAL;
677
678 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
679 "enabled=%d pending=%d\n", __func__,
680 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
681 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
682 t->enabled, t->pending);
683
684 /* Read control registers. */
685 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
686 if (ret < 0)
687 return ret;
688
689 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
690 ctl[1] |= RX8130_REG_FLAG_AF;
691 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
692
693 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
694 if (ret < 0)
695 return ret;
696
697 /* Hardware alarm precision is 1 minute! */
698 ald[0] = bin2bcd(t->time.tm_min);
699 ald[1] = bin2bcd(t->time.tm_hour);
700 ald[2] = bin2bcd(t->time.tm_mday);
701
702 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 3);
703 if (ret < 0)
704 return ret;
705
706 if (!t->enabled)
707 return 0;
708
709 ctl[2] |= RX8130_REG_CONTROL0_AIE;
710
711 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
712}
713
714static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
715{
716 struct ds1307 *ds1307 = dev_get_drvdata(dev);
717 int ret, reg;
718
719 if (!test_bit(HAS_ALARM, &ds1307->flags))
720 return -EINVAL;
721
722 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
723 if (ret < 0)
724 return ret;
725
726 if (enabled)
727 reg |= RX8130_REG_CONTROL0_AIE;
728 else
729 reg &= ~RX8130_REG_CONTROL0_AIE;
730
731 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
732}
733
734static const struct rtc_class_ops rx8130_rtc_ops = {
735 .read_time = ds1307_get_time,
736 .set_time = ds1307_set_time,
737 .read_alarm = rx8130_read_alarm,
738 .set_alarm = rx8130_set_alarm,
739 .alarm_irq_enable = rx8130_alarm_irq_enable,
740};
741
742/*----------------------------------------------------------------------*/
743
1d1945d2 744/*
f4199f85 745 * Alarm support for mcp794xx devices.
1d1945d2
SG		 746 */
747
e29385fa
K		 748#define MCP794XX_REG_WEEKDAY 0x3
749#define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
f4199f85
TN		 750#define MCP794XX_REG_CONTROL 0x07
751# define MCP794XX_BIT_ALM0_EN 0x10
752# define MCP794XX_BIT_ALM1_EN 0x20
753#define MCP794XX_REG_ALARM0_BASE 0x0a
754#define MCP794XX_REG_ALARM0_CTRL 0x0d
755#define MCP794XX_REG_ALARM1_BASE 0x11
756#define MCP794XX_REG_ALARM1_CTRL 0x14
757# define MCP794XX_BIT_ALMX_IF (1 << 3)
758# define MCP794XX_BIT_ALMX_C0 (1 << 4)
759# define MCP794XX_BIT_ALMX_C1 (1 << 5)
760# define MCP794XX_BIT_ALMX_C2 (1 << 6)
761# define MCP794XX_BIT_ALMX_POL (1 << 7)
762# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
763 MCP794XX_BIT_ALMX_C1 | \
764 MCP794XX_BIT_ALMX_C2)
765
2fb07a10 766static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
1d1945d2 767{
11e5890b 768 struct ds1307 *ds1307 = dev_id;
2fb07a10 769 struct mutex *lock = &ds1307->rtc->ops_lock;
1d1945d2
SG		 770 int reg, ret;
771
2fb07a10 772 mutex_lock(lock);
1d1945d2
SG		 773
774 /* Check and clear alarm 0 interrupt flag. */
11e5890b
HK		 775 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
776 if (ret)
1d1945d2 777 goto out;
f4199f85 778 if (!(reg & MCP794XX_BIT_ALMX_IF))
1d1945d2 779 goto out;
f4199f85 780 reg &= ~MCP794XX_BIT_ALMX_IF;
11e5890b
HK		 781 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
782 if (ret)
1d1945d2
SG		 783 goto out;
784
785 /* Disable alarm 0. */
078f3f64
HK		 786 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
787 MCP794XX_BIT_ALM0_EN, 0);
11e5890b 788 if (ret)
1d1945d2
SG		 789 goto out;
790
791 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
792
793out:
2fb07a10
FB		 794 mutex_unlock(lock);
795
796 return IRQ_HANDLED;
1d1945d2
SG		 797}
798
f4199f85 799static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2 800{
11e5890b 801 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1d1945d2
SG		 802 u8 *regs = ds1307->regs;
803 int ret;
804
805 if (!test_bit(HAS_ALARM, &ds1307->flags))
806 return -EINVAL;
807
808 /* Read control and alarm 0 registers. */
11e5890b
HK		 809 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
810 if (ret)
1d1945d2
SG		 811 return ret;
812
f4199f85 813 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
1d1945d2
SG		 814
815 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
816 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
817 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
818 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
819 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
820 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
821 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
822 t->time.tm_year = -1;
823 t->time.tm_yday = -1;
824 t->time.tm_isdst = -1;
825
826 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
827 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
828 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
829 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
f4199f85
TN		 830 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
831 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
832 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
1d1945d2
SG		 833
834 return 0;
835}
836
f4199f85 837static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2 838{
11e5890b 839 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1d1945d2
SG		 840 unsigned char *regs = ds1307->regs;
841 int ret;
842
843 if (!test_bit(HAS_ALARM, &ds1307->flags))
844 return -EINVAL;
845
846 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
847 "enabled=%d pending=%d\n", __func__,
848 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
849 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
850 t->enabled, t->pending);
851
852 /* Read control and alarm 0 registers. */
11e5890b
HK		 853 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
854 if (ret)
1d1945d2
SG		 855 return ret;
856
857 /* Set alarm 0, using 24-hour and day-of-month modes. */
858 regs[3] = bin2bcd(t->time.tm_sec);
859 regs[4] = bin2bcd(t->time.tm_min);
860 regs[5] = bin2bcd(t->time.tm_hour);
62c8c20a 861 regs[6] = bin2bcd(t->time.tm_wday + 1);
1d1945d2 862 regs[7] = bin2bcd(t->time.tm_mday);
62c8c20a 863 regs[8] = bin2bcd(t->time.tm_mon + 1);
1d1945d2
SG		 864
865 /* Clear the alarm 0 interrupt flag. */
f4199f85 866 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
1d1945d2 867 /* Set alarm match: second, minute, hour, day, date, month. */
f4199f85 868 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
e3edd671
NM		 869 /* Disable interrupt. We will not enable until completely programmed */
870 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 871
11e5890b
HK		 872 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
873 if (ret)
1d1945d2
SG		 874 return ret;
875
e3edd671
NM		 876 if (!t->enabled)
877 return 0;
878 regs[0] |= MCP794XX_BIT_ALM0_EN;
11e5890b 879 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
1d1945d2
SG		 880}
881
f4199f85 882static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
1d1945d2 883{
11e5890b 884 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1d1945d2
SG		 885
886 if (!test_bit(HAS_ALARM, &ds1307->flags))
887 return -EINVAL;
888
078f3f64
HK		 889 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
890 MCP794XX_BIT_ALM0_EN,
891 enabled ? MCP794XX_BIT_ALM0_EN : 0);
1d1945d2
SG		 892}
893
f4199f85 894static const struct rtc_class_ops mcp794xx_rtc_ops = {
1d1945d2
SG		 895 .read_time = ds1307_get_time,
896 .set_time = ds1307_set_time,
f4199f85
TN		 897 .read_alarm = mcp794xx_read_alarm,
898 .set_alarm = mcp794xx_set_alarm,
899 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
1d1945d2
SG		 900};
901
902/*----------------------------------------------------------------------*/
903
abc925f7
AB		 904static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
905 size_t bytes)
682d73f6 906{
abc925f7 907 struct ds1307 *ds1307 = priv;
682d73f6 908
abc925f7
AB		 909 return regmap_bulk_read(ds1307->regmap, ds1307->nvram_offset + offset,
910 val, bytes);
682d73f6
DB		 911}
912
abc925f7
AB		 913static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
914 size_t bytes)
682d73f6 915{
abc925f7 916 struct ds1307 *ds1307 = priv;
682d73f6 917
abc925f7
AB		 918 return regmap_bulk_write(ds1307->regmap, ds1307->nvram_offset + offset,
919 val, bytes);
682d73f6
DB		 920}
921
682d73f6
DB		 922/*----------------------------------------------------------------------*/
923
11e5890b 924static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
33b04b7b
MV		 925 uint32_t ohms, bool diode)
926{
927 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
928 DS1307_TRICKLE_CHARGER_NO_DIODE;
929
930 switch (ohms) {
931 case 250:
932 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
933 break;
934 case 2000:
935 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
936 break;
937 case 4000:
938 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
939 break;
940 default:
11e5890b 941 dev_warn(ds1307->dev,
33b04b7b
MV		 942 "Unsupported ohm value %u in dt\n", ohms);
943 return 0;
944 }
945 return setup;
946}
947
d8490fd5 948static u8 ds1307_trickle_init(struct ds1307 *ds1307,
7624df48 949 const struct chip_desc *chip)
33b04b7b 950{
d8490fd5 951 uint32_t ohms;
33b04b7b
MV		 952 bool diode = true;
953
954 if (!chip->do_trickle_setup)
d8490fd5
HK		 955 return 0;
956
11e5890b
HK		 957 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
958 &ohms))
d8490fd5
HK		 959 return 0;
960
11e5890b 961 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
33b04b7b 962 diode = false;
d8490fd5
HK		 963
964 return chip->do_trickle_setup(ds1307, ohms, diode);
33b04b7b
MV		 965}
966
445c0207
AM		 967/*----------------------------------------------------------------------*/
968
969#ifdef CONFIG_RTC_DRV_DS1307_HWMON
970
971/*
972 * Temperature sensor support for ds3231 devices.
973 */
974
975#define DS3231_REG_TEMPERATURE 0x11
976
977/*
978 * A user-initiated temperature conversion is not started by this function,
979 * so the temperature is updated once every 64 seconds.
980 */
9a3dce62 981static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
445c0207
AM		 982{
983 struct ds1307 *ds1307 = dev_get_drvdata(dev);
984 u8 temp_buf[2];
985 s16 temp;
986 int ret;
987
11e5890b
HK		 988 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
989 temp_buf, sizeof(temp_buf));
990 if (ret)
445c0207 991 return ret;
445c0207
AM		 992 /*
993 * Temperature is represented as a 10-bit code with a resolution of
994 * 0.25 degree celsius and encoded in two's complement format.
995 */
996 temp = (temp_buf[0] << 8) | temp_buf[1];
997 temp >>= 6;
998 *mC = temp * 250;
999
1000 return 0;
1001}
1002
1003static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1004 struct device_attribute *attr, char *buf)
1005{
1006 int ret;
9a3dce62 1007 s32 temp;
445c0207
AM		 1008
1009 ret = ds3231_hwmon_read_temp(dev, &temp);
1010 if (ret)
1011 return ret;
1012
1013 return sprintf(buf, "%d\n", temp);
1014}
1015static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, ds3231_hwmon_show_temp,
1016 NULL, 0);
1017
1018static struct attribute *ds3231_hwmon_attrs[] = {
1019 &sensor_dev_attr_temp1_input.dev_attr.attr,
1020 NULL,
1021};
1022ATTRIBUTE_GROUPS(ds3231_hwmon);
1023
1024static void ds1307_hwmon_register(struct ds1307 *ds1307)
1025{
1026 struct device *dev;
1027
1028 if (ds1307->type != ds_3231)
1029 return;
1030
11e5890b 1031 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
445c0207
AM		 1032 ds1307, ds3231_hwmon_groups);
1033 if (IS_ERR(dev)) {
11e5890b
HK		 1034 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1035 PTR_ERR(dev));
445c0207
AM		 1036 }
1037}
1038
1039#else
1040
1041static void ds1307_hwmon_register(struct ds1307 *ds1307)
1042{
1043}
1044
6c6ff145
AM		 1045#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1046
1047/*----------------------------------------------------------------------*/
1048
1049/*
1050 * Square-wave output support for DS3231
1051 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1052 */
1053#ifdef CONFIG_COMMON_CLK
1054
1055enum {
1056 DS3231_CLK_SQW = 0,
1057 DS3231_CLK_32KHZ,
1058};
1059
1060#define clk_sqw_to_ds1307(clk) \
1061 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1062#define clk_32khz_to_ds1307(clk) \
1063 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1064
1065static int ds3231_clk_sqw_rates[] = {
1066 1,
1067 1024,
1068 4096,
1069 8192,
1070};
1071
1072static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1073{
6c6ff145 1074 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1075 int ret;
1076
1077 mutex_lock(lock);
078f3f64
HK		 1078 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1079 mask, value);
6c6ff145
AM		 1080 mutex_unlock(lock);
1081
1082 return ret;
1083}
1084
1085static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1086 unsigned long parent_rate)
1087{
1088 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1089 int control, ret;
6c6ff145
AM		 1090 int rate_sel = 0;
1091
11e5890b
HK		 1092 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1093 if (ret)
1094 return ret;
6c6ff145
AM		 1095 if (control & DS1337_BIT_RS1)
1096 rate_sel += 1;
1097 if (control & DS1337_BIT_RS2)
1098 rate_sel += 2;
1099
1100 return ds3231_clk_sqw_rates[rate_sel];
1101}
1102
1103static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1104 unsigned long *prate)
1105{
1106 int i;
1107
1108 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1109 if (ds3231_clk_sqw_rates[i] <= rate)
1110 return ds3231_clk_sqw_rates[i];
1111 }
1112
1113 return 0;
1114}
1115
1116static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1117 unsigned long parent_rate)
1118{
1119 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1120 int control = 0;
1121 int rate_sel;
1122
1123 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1124 rate_sel++) {
1125 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1126 break;
1127 }
1128
1129 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1130 return -EINVAL;
1131
1132 if (rate_sel & 1)
1133 control |= DS1337_BIT_RS1;
1134 if (rate_sel & 2)
1135 control |= DS1337_BIT_RS2;
1136
1137 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1138 control);
1139}
1140
1141static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1142{
1143 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1144
1145 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1146}
1147
1148static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1149{
1150 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1151
1152 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1153}
1154
1155static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1156{
1157 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1158 int control, ret;
6c6ff145 1159
11e5890b
HK		 1160 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1161 if (ret)
1162 return ret;
6c6ff145
AM		 1163
1164 return !(control & DS1337_BIT_INTCN);
1165}
1166
1167static const struct clk_ops ds3231_clk_sqw_ops = {
1168 .prepare = ds3231_clk_sqw_prepare,
1169 .unprepare = ds3231_clk_sqw_unprepare,
1170 .is_prepared = ds3231_clk_sqw_is_prepared,
1171 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1172 .round_rate = ds3231_clk_sqw_round_rate,
1173 .set_rate = ds3231_clk_sqw_set_rate,
1174};
1175
1176static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1177 unsigned long parent_rate)
1178{
1179 return 32768;
1180}
1181
1182static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1183{
6c6ff145 1184 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1185 int ret;
1186
1187 mutex_lock(lock);
078f3f64
HK		 1188 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1189 DS3231_BIT_EN32KHZ,
1190 enable ? DS3231_BIT_EN32KHZ : 0);
6c6ff145
AM		 1191 mutex_unlock(lock);
1192
1193 return ret;
1194}
1195
1196static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1197{
1198 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1199
1200 return ds3231_clk_32khz_control(ds1307, true);
1201}
1202
1203static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1204{
1205 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1206
1207 ds3231_clk_32khz_control(ds1307, false);
1208}
1209
1210static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1211{
1212 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
11e5890b 1213 int status, ret;
6c6ff145 1214
11e5890b
HK		 1215 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1216 if (ret)
1217 return ret;
6c6ff145
AM		 1218
1219 return !!(status & DS3231_BIT_EN32KHZ);
1220}
1221
1222static const struct clk_ops ds3231_clk_32khz_ops = {
1223 .prepare = ds3231_clk_32khz_prepare,
1224 .unprepare = ds3231_clk_32khz_unprepare,
1225 .is_prepared = ds3231_clk_32khz_is_prepared,
1226 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1227};
1228
1229static struct clk_init_data ds3231_clks_init[] = {
1230 [DS3231_CLK_SQW] = {
1231 .name = "ds3231_clk_sqw",
1232 .ops = &ds3231_clk_sqw_ops,
6c6ff145
AM		 1233 },
1234 [DS3231_CLK_32KHZ] = {
1235 .name = "ds3231_clk_32khz",
1236 .ops = &ds3231_clk_32khz_ops,
6c6ff145
AM		 1237 },
1238};
1239
1240static int ds3231_clks_register(struct ds1307 *ds1307)
1241{
11e5890b 1242 struct device_node *node = ds1307->dev->of_node;
6c6ff145
AM		 1243 struct clk_onecell_data *onecell;
1244 int i;
1245
11e5890b 1246 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
6c6ff145
AM		 1247 if (!onecell)
1248 return -ENOMEM;
1249
1250 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
11e5890b
HK		 1251 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1252 sizeof(onecell->clks[0]), GFP_KERNEL);
6c6ff145
AM		 1253 if (!onecell->clks)
1254 return -ENOMEM;
1255
1256 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1257 struct clk_init_data init = ds3231_clks_init[i];
1258
1259 /*
1260 * Interrupt signal due to alarm conditions and square-wave
1261 * output share same pin, so don't initialize both.
1262 */
1263 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1264 continue;
1265
1266 /* optional override of the clockname */
1267 of_property_read_string_index(node, "clock-output-names", i,
1268 &init.name);
1269 ds1307->clks[i].init = &init;
1270
11e5890b
HK		 1271 onecell->clks[i] = devm_clk_register(ds1307->dev,
1272 &ds1307->clks[i]);
6c6ff145
AM		 1273 if (IS_ERR(onecell->clks[i]))
1274 return PTR_ERR(onecell->clks[i]);
1275 }
1276
1277 if (!node)
1278 return 0;
1279
1280 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1281
1282 return 0;
1283}
1284
1285static void ds1307_clks_register(struct ds1307 *ds1307)
1286{
1287 int ret;
1288
1289 if (ds1307->type != ds_3231)
1290 return;
1291
1292 ret = ds3231_clks_register(ds1307);
1293 if (ret) {
11e5890b
HK		 1294 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1295 ret);
6c6ff145
AM		 1296 }
1297}
1298
1299#else
1300
1301static void ds1307_clks_register(struct ds1307 *ds1307)
1302{
1303}
1304
1305#endif /* CONFIG_COMMON_CLK */
445c0207 1306
11e5890b
HK		 1307static const struct regmap_config regmap_config = {
1308 .reg_bits = 8,
1309 .val_bits = 8,
1310 .max_register = 0x12,
1311};
1312
5a167f45
GKH		 1313static int ds1307_probe(struct i2c_client *client,
1314 const struct i2c_device_id *id)
1abb0dc9
DB		 1315{
1316 struct ds1307 *ds1307;
1317 int err = -ENODEV;
e29385fa 1318 int tmp, wday;
7624df48 1319 const struct chip_desc *chip;
82e2d43f 1320 bool want_irq;
8bc2a407 1321 bool ds1307_can_wakeup_device = false;
fed40b73 1322 unsigned char *buf;
01ce893d 1323 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
e29385fa
K		 1324 struct rtc_time tm;
1325 unsigned long timestamp;
d8490fd5 1326 u8 trickle_charger_setup = 0;
e29385fa 1327
1d1945d2 1328 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1abb0dc9 1329
edca66d2 1330 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 1331 if (!ds1307)
c065f35c 1332 return -ENOMEM;
045e0e85 1333
11e5890b
HK		 1334 dev_set_drvdata(&client->dev, ds1307);
1335 ds1307->dev = &client->dev;
1336 ds1307->name = client->name;
11e5890b
HK		 1337
1338 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1339 if (IS_ERR(ds1307->regmap)) {
1340 dev_err(ds1307->dev, "regmap allocation failed\n");
1341 return PTR_ERR(ds1307->regmap);
1342 }
33df2ee1 1343
11e5890b 1344 i2c_set_clientdata(client, ds1307);
7ef6d2c2
JMC		 1345
1346 if (client->dev.of_node) {
1347 ds1307->type = (enum ds_type)
1348 of_device_get_match_data(&client->dev);
1349 chip = &chips[ds1307->type];
1350 } else if (id) {
9c19b893
TH		 1351 chip = &chips[id->driver_data];
1352 ds1307->type = id->driver_data;
1353 } else {
1354 const struct acpi_device_id *acpi_id;
1355
1356 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
11e5890b 1357 ds1307->dev);
9c19b893
TH		 1358 if (!acpi_id)
1359 return -ENODEV;
1360 chip = &chips[acpi_id->driver_data];
1361 ds1307->type = acpi_id->driver_data;
1362 }
33df2ee1 1363
82e2d43f
HK		 1364 want_irq = client->irq > 0 && chip->alarm;
1365
9c19b893 1366 if (!pdata)
d8490fd5 1367 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
9c19b893 1368 else if (pdata->trickle_charger_setup)
d8490fd5 1369 trickle_charger_setup = pdata->trickle_charger_setup;
33b04b7b 1370
d8490fd5
HK		 1371 if (trickle_charger_setup && chip->trickle_charger_reg) {
1372 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
11e5890b
HK		 1373 dev_dbg(ds1307->dev,
1374 "writing trickle charger info 0x%x to 0x%x\n",
d8490fd5 1375 trickle_charger_setup, chip->trickle_charger_reg);
11e5890b 1376 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
d8490fd5 1377 trickle_charger_setup);
33b04b7b 1378 }
eb86c306 1379
fed40b73 1380 buf = ds1307->regs;
045e0e85 1381
8bc2a407
ML		 1382#ifdef CONFIG_OF
1383/*
1384 * For devices with no IRQ directly connected to the SoC, the RTC chip
1385 * can be forced as a wakeup source by stating that explicitly in
1386 * the device's .dts file using the "wakeup-source" boolean property.
1387 * If the "wakeup-source" property is set, don't request an IRQ.
1388 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1389 * if supported by the RTC.
1390 */
82e2d43f
HK		 1391 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1392 "wakeup-source"))
8bc2a407 1393 ds1307_can_wakeup_device = true;
8bc2a407
ML		 1394#endif
1395
045e0e85
DB		 1396 switch (ds1307->type) {
1397 case ds_1337:
1398 case ds_1339:
97f902b7 1399 case ds_3231:
be5f59f4 1400 /* get registers that the "rtc" read below won't read... */
11e5890b
HK		 1401 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1402 buf, 2);
1403 if (err) {
1404 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1405 goto exit;
1abb0dc9
DB		 1406 }
1407
be5f59f4
RG		 1408 /* oscillator off? turn it on, so clock can tick. */
1409 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG		 1410 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
1411
40ce972d 1412 /*
8bc2a407
ML		 1413 * Using IRQ or defined as wakeup-source?
1414 * Disable the square wave and both alarms.
97f902b7
WS		 1415 * For some variants, be sure alarms can trigger when we're
1416 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 1417 */
82e2d43f 1418 if (want_irq || ds1307_can_wakeup_device) {
0b6ee805 1419 ds1307->regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
cb49a5e9
RG		 1420 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1421 }
1422
11e5890b
HK		 1423 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1424 ds1307->regs[0]);
be5f59f4
RG		 1425
1426 /* oscillator fault? clear flag, and warn */
1427 if (ds1307->regs[1] & DS1337_BIT_OSF) {
11e5890b
HK		 1428 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1429 ds1307->regs[1] & ~DS1337_BIT_OSF);
1430 dev_warn(ds1307->dev, "SET TIME!\n");
1abb0dc9 1431 }
045e0e85 1432 break;
a2166858
MF		 1433
1434 case rx_8025:
11e5890b
HK		 1435 err = regmap_bulk_read(ds1307->regmap,
1436 RX8025_REG_CTRL1 << 4 | 0x08, buf, 2);
1437 if (err) {
1438 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1439 goto exit;
a2166858
MF		 1440 }
1441
1442 /* oscillator off? turn it on, so clock can tick. */
1443 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
1444 ds1307->regs[1] |= RX8025_BIT_XST;
11e5890b
HK		 1445 regmap_write(ds1307->regmap,
1446 RX8025_REG_CTRL2 << 4 | 0x08,
1447 ds1307->regs[1]);
1448 dev_warn(ds1307->dev,
a2166858
MF		 1449 "oscillator stop detected - SET TIME!\n");
1450 }
1451
1452 if (ds1307->regs[1] & RX8025_BIT_PON) {
1453 ds1307->regs[1] &= ~RX8025_BIT_PON;
11e5890b
HK		 1454 regmap_write(ds1307->regmap,
1455 RX8025_REG_CTRL2 << 4 | 0x08,
1456 ds1307->regs[1]);
1457 dev_warn(ds1307->dev, "power-on detected\n");
a2166858
MF		 1458 }
1459
1460 if (ds1307->regs[1] & RX8025_BIT_VDET) {
1461 ds1307->regs[1] &= ~RX8025_BIT_VDET;
11e5890b
HK		 1462 regmap_write(ds1307->regmap,
1463 RX8025_REG_CTRL2 << 4 | 0x08,
1464 ds1307->regs[1]);
1465 dev_warn(ds1307->dev, "voltage drop detected\n");
a2166858
MF		 1466 }
1467
1468 /* make sure we are running in 24hour mode */
1469 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
1470 u8 hour;
1471
1472 /* switch to 24 hour mode */
11e5890b
HK		 1473 regmap_write(ds1307->regmap,
1474 RX8025_REG_CTRL1 << 4 | 0x08,
1475 ds1307->regs[0] | RX8025_BIT_2412);
1476
1477 err = regmap_bulk_read(ds1307->regmap,
1478 RX8025_REG_CTRL1 << 4 | 0x08,
1479 buf, 2);
1480 if (err) {
1481 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1482 goto exit;
a2166858
MF		 1483 }
1484
1485 /* correct hour */
1486 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1487 if (hour == 12)
1488 hour = 0;
1489 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1490 hour += 12;
1491
11e5890b
HK		 1492 regmap_write(ds1307->regmap,
1493 DS1307_REG_HOUR << 4 | 0x08, hour);
a2166858
MF		 1494 }
1495 break;
ee0981be
MV		 1496 case rx_8130:
1497 ds1307->offset = 0x10; /* Seconds starts at 0x10 */
1498 rtc_ops = &rx8130_rtc_ops;
ee0981be 1499 break;
33df2ee1
JT		 1500 case ds_1388:
1501 ds1307->offset = 1; /* Seconds starts at 1 */
1502 break;
f4199f85
TN		 1503 case mcp794xx:
1504 rtc_ops = &mcp794xx_rtc_ops;
1d1945d2 1505 break;
045e0e85
DB		 1506 default:
1507 break;
1508 }
1abb0dc9
DB		 1509
1510read_rtc:
1511 /* read RTC registers */
11e5890b
HK		 1512 err = regmap_bulk_read(ds1307->regmap, ds1307->offset, buf, 8);
1513 if (err) {
1514 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1515 goto exit;
1abb0dc9
DB		 1516 }
1517
40ce972d
DA		 1518 /*
1519 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB		 1520 * specify the extra bits as must-be-zero, but there are
1521 * still a few values that are clearly out-of-range.
1522 */
1523 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB		 1524 switch (ds1307->type) {
1525 case ds_1307:
8566f70c 1526 case m41t0:
045e0e85 1527 case m41t00:
be5f59f4 1528 /* clock halted? turn it on, so clock can tick. */
045e0e85 1529 if (tmp & DS1307_BIT_CH) {
11e5890b
HK		 1530 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1531 dev_warn(ds1307->dev, "SET TIME!\n");
045e0e85 1532 goto read_rtc;
1abb0dc9 1533 }
045e0e85 1534 break;
300a7735 1535 case ds_1308:
be5f59f4
RG		 1536 case ds_1338:
1537 /* clock halted? turn it on, so clock can tick. */
045e0e85 1538 if (tmp & DS1307_BIT_CH)
11e5890b 1539 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
be5f59f4
RG		 1540
1541 /* oscillator fault? clear flag, and warn */
1542 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
11e5890b
HK		 1543 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1544 ds1307->regs[DS1307_REG_CONTROL] &
1545 ~DS1338_BIT_OSF);
1546 dev_warn(ds1307->dev, "SET TIME!\n");
be5f59f4
RG		 1547 goto read_rtc;
1548 }
045e0e85 1549 break;
fcd8db00
R		 1550 case ds_1340:
1551 /* clock halted? turn it on, so clock can tick. */
1552 if (tmp & DS1340_BIT_nEOSC)
11e5890b 1553 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
fcd8db00 1554
11e5890b
HK		 1555 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1556 if (err) {
1557 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1558 goto exit;
fcd8db00
R		 1559 }
1560
1561 /* oscillator fault? clear flag, and warn */
1562 if (tmp & DS1340_BIT_OSF) {
11e5890b
HK		 1563 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1564 dev_warn(ds1307->dev, "SET TIME!\n");
fcd8db00 1565 }
43fcb815 1566 break;
f4199f85 1567 case mcp794xx:
43fcb815 1568 /* make sure that the backup battery is enabled */
f4199f85 1569 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
11e5890b
HK		 1570 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1571 ds1307->regs[DS1307_REG_WDAY] |
1572 MCP794XX_BIT_VBATEN);
43fcb815
DA		 1573 }
1574
1575 /* clock halted? turn it on, so clock can tick. */
f4199f85 1576 if (!(tmp & MCP794XX_BIT_ST)) {
11e5890b
HK		 1577 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1578 MCP794XX_BIT_ST);
1579 dev_warn(ds1307->dev, "SET TIME!\n");
43fcb815
DA		 1580 goto read_rtc;
1581 }
1582
fcd8db00 1583 break;
32d322bc 1584 default:
045e0e85 1585 break;
1abb0dc9 1586 }
045e0e85 1587
1abb0dc9 1588 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB		 1589 switch (ds1307->type) {
1590 case ds_1340:
8566f70c 1591 case m41t0:
c065f35c 1592 case m41t00:
40ce972d
DA		 1593 /*
1594 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1595 * systems that will run through year 2100.
1596 */
1597 break;
a2166858
MF		 1598 case rx_8025:
1599 break;
c065f35c
DB		 1600 default:
1601 if (!(tmp & DS1307_BIT_12HR))
1602 break;
1603
40ce972d
DA		 1604 /*
1605 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1606 * take note...
1607 */
fe20ba70 1608 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1609 if (tmp == 12)
1610 tmp = 0;
1611 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1612 tmp += 12;
11e5890b
HK		 1613 regmap_write(ds1307->regmap, ds1307->offset + DS1307_REG_HOUR,
1614 bin2bcd(tmp));
1abb0dc9
DB		 1615 }
1616
e29385fa
K		 1617 /*
1618 * Some IPs have weekday reset value = 0x1 which might not correct
1619 * hence compute the wday using the current date/month/year values
1620 */
11e5890b 1621 ds1307_get_time(ds1307->dev, &tm);
e29385fa
K		 1622 wday = tm.tm_wday;
1623 timestamp = rtc_tm_to_time64(&tm);
1624 rtc_time64_to_tm(timestamp, &tm);
1625
1626 /*
1627 * Check if reset wday is different from the computed wday
1628 * If different then set the wday which we computed using
1629 * timestamp
1630 */
078f3f64
HK		 1631 if (wday != tm.tm_wday)
1632 regmap_update_bits(ds1307->regmap, MCP794XX_REG_WEEKDAY,
1633 MCP794XX_REG_WEEKDAY_WDAY_MASK,
1634 tm.tm_wday + 1);
e29385fa 1635
82e2d43f 1636 if (want_irq || ds1307_can_wakeup_device) {
11e5890b 1637 device_set_wakeup_capable(ds1307->dev, true);
3abb1ada
SG		 1638 set_bit(HAS_ALARM, &ds1307->flags);
1639 }
69b119a6
AB		 1640
1641 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1abb0dc9 1642 if (IS_ERR(ds1307->rtc)) {
4071ea25 1643 return PTR_ERR(ds1307->rtc);
1abb0dc9
DB		 1644 }
1645
82e2d43f 1646 if (ds1307_can_wakeup_device && !want_irq) {
11e5890b
HK		 1647 dev_info(ds1307->dev,
1648 "'wakeup-source' is set, request for an IRQ is disabled!\n");
8bc2a407
ML		 1649 /* We cannot support UIE mode if we do not have an IRQ line */
1650 ds1307->rtc->uie_unsupported = 1;
1651 }
1652
cb49a5e9 1653 if (want_irq) {
45947127
HK		 1654 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1655 chip->irq_handler ?: ds1307_irq,
c5983191 1656 IRQF_SHARED | IRQF_ONESHOT,
4b9e2a0c 1657 ds1307->name, ds1307);
cb49a5e9 1658 if (err) {
4071ea25 1659 client->irq = 0;
11e5890b 1660 device_set_wakeup_capable(ds1307->dev, false);
3abb1ada 1661 clear_bit(HAS_ALARM, &ds1307->flags);
11e5890b 1662 dev_err(ds1307->dev, "unable to request IRQ!\n");
3abb1ada 1663 } else
11e5890b 1664 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
cb49a5e9
RG		 1665 }
1666
9eab0a78 1667 if (chip->nvram_size) {
abc925f7
AB		 1668 ds1307->nvmem_cfg.name = "ds1307_nvram";
1669 ds1307->nvmem_cfg.word_size = 1;
1670 ds1307->nvmem_cfg.stride = 1;
1671 ds1307->nvmem_cfg.size = chip->nvram_size;
1672 ds1307->nvmem_cfg.reg_read = ds1307_nvram_read;
1673 ds1307->nvmem_cfg.reg_write = ds1307_nvram_write;
1674 ds1307->nvmem_cfg.priv = ds1307;
1675 ds1307->nvram_offset = chip->nvram_offset;
1676
1677 ds1307->rtc->nvmem_config = &ds1307->nvmem_cfg;
1678 ds1307->rtc->nvram_old_abi = true;
682d73f6
DB		 1679 }
1680
69b119a6
AB		 1681 ds1307->rtc->ops = rtc_ops;
1682 err = rtc_register_device(ds1307->rtc);
1683 if (err)
1684 return err;
1685
445c0207 1686 ds1307_hwmon_register(ds1307);
6c6ff145 1687 ds1307_clks_register(ds1307);
445c0207 1688
1abb0dc9
DB		 1689 return 0;
1690
edca66d2 1691exit:
1abb0dc9
DB		 1692 return err;
1693}
1694
1abb0dc9
DB		 1695static struct i2c_driver ds1307_driver = {
1696 .driver = {
c065f35c 1697 .name = "rtc-ds1307",
7ef6d2c2 1698 .of_match_table = of_match_ptr(ds1307_of_match),
9c19b893 1699 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1abb0dc9 1700 },
c065f35c 1701 .probe = ds1307_probe,
3760f736 1702 .id_table = ds1307_id,
1abb0dc9
DB		 1703};
1704
0abc9201 1705module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 1706
1707MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1708MODULE_LICENSE("GPL");
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