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Commit | Line | Data |
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1abb0dc9 DB |
1 | /* |
2 | * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. | |
3 | * | |
4 | * Copyright (C) 2005 James Chapman (ds1337 core) | |
5 | * Copyright (C) 2006 David Brownell | |
a2166858 | 6 | * Copyright (C) 2009 Matthias Fuchs (rx8025 support) |
bc48b902 | 7 | * Copyright (C) 2012 Bertrand Achard (nvram access fixes) |
1abb0dc9 DB |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/rtc.h> | |
20 | #include <linux/bcd.h> | |
eb86c306 | 21 | #include <linux/rtc/ds1307.h> |
1abb0dc9 | 22 | |
40ce972d DA |
23 | /* |
24 | * We can't determine type by probing, but if we expect pre-Linux code | |
1abb0dc9 DB |
25 | * to have set the chip up as a clock (turning on the oscillator and |
26 | * setting the date and time), Linux can ignore the non-clock features. | |
27 | * That's a natural job for a factory or repair bench. | |
1abb0dc9 DB |
28 | */ |
29 | enum ds_type { | |
045e0e85 DB |
30 | ds_1307, |
31 | ds_1337, | |
32 | ds_1338, | |
33 | ds_1339, | |
34 | ds_1340, | |
33df2ee1 | 35 | ds_1388, |
97f902b7 | 36 | ds_3231, |
045e0e85 | 37 | m41t00, |
43fcb815 | 38 | mcp7941x, |
a2166858 | 39 | rx_8025, |
32d322bc | 40 | last_ds_type /* always last */ |
40ce972d | 41 | /* rs5c372 too? different address... */ |
1abb0dc9 DB |
42 | }; |
43 | ||
1abb0dc9 DB |
44 | |
45 | /* RTC registers don't differ much, except for the century flag */ | |
46 | #define DS1307_REG_SECS 0x00 /* 00-59 */ | |
47 | # define DS1307_BIT_CH 0x80 | |
be5f59f4 | 48 | # define DS1340_BIT_nEOSC 0x80 |
43fcb815 | 49 | # define MCP7941X_BIT_ST 0x80 |
1abb0dc9 DB |
50 | #define DS1307_REG_MIN 0x01 /* 00-59 */ |
51 | #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ | |
c065f35c DB |
52 | # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ |
53 | # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ | |
1abb0dc9 DB |
54 | # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ |
55 | # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ | |
56 | #define DS1307_REG_WDAY 0x03 /* 01-07 */ | |
43fcb815 | 57 | # define MCP7941X_BIT_VBATEN 0x08 |
1abb0dc9 DB |
58 | #define DS1307_REG_MDAY 0x04 /* 01-31 */ |
59 | #define DS1307_REG_MONTH 0x05 /* 01-12 */ | |
60 | # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ | |
61 | #define DS1307_REG_YEAR 0x06 /* 00-99 */ | |
62 | ||
40ce972d DA |
63 | /* |
64 | * Other registers (control, status, alarms, trickle charge, NVRAM, etc) | |
045e0e85 DB |
65 | * start at 7, and they differ a LOT. Only control and status matter for |
66 | * basic RTC date and time functionality; be careful using them. | |
1abb0dc9 | 67 | */ |
045e0e85 | 68 | #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ |
1abb0dc9 | 69 | # define DS1307_BIT_OUT 0x80 |
be5f59f4 | 70 | # define DS1338_BIT_OSF 0x20 |
1abb0dc9 DB |
71 | # define DS1307_BIT_SQWE 0x10 |
72 | # define DS1307_BIT_RS1 0x02 | |
73 | # define DS1307_BIT_RS0 0x01 | |
74 | #define DS1337_REG_CONTROL 0x0e | |
75 | # define DS1337_BIT_nEOSC 0x80 | |
cb49a5e9 | 76 | # define DS1339_BIT_BBSQI 0x20 |
97f902b7 | 77 | # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ |
1abb0dc9 DB |
78 | # define DS1337_BIT_RS2 0x10 |
79 | # define DS1337_BIT_RS1 0x08 | |
80 | # define DS1337_BIT_INTCN 0x04 | |
81 | # define DS1337_BIT_A2IE 0x02 | |
82 | # define DS1337_BIT_A1IE 0x01 | |
045e0e85 DB |
83 | #define DS1340_REG_CONTROL 0x07 |
84 | # define DS1340_BIT_OUT 0x80 | |
85 | # define DS1340_BIT_FT 0x40 | |
86 | # define DS1340_BIT_CALIB_SIGN 0x20 | |
87 | # define DS1340_M_CALIBRATION 0x1f | |
be5f59f4 RG |
88 | #define DS1340_REG_FLAG 0x09 |
89 | # define DS1340_BIT_OSF 0x80 | |
1abb0dc9 DB |
90 | #define DS1337_REG_STATUS 0x0f |
91 | # define DS1337_BIT_OSF 0x80 | |
92 | # define DS1337_BIT_A2I 0x02 | |
93 | # define DS1337_BIT_A1I 0x01 | |
cb49a5e9 | 94 | #define DS1339_REG_ALARM1_SECS 0x07 |
eb86c306 WS |
95 | |
96 | #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 | |
1abb0dc9 | 97 | |
a2166858 MF |
98 | #define RX8025_REG_CTRL1 0x0e |
99 | # define RX8025_BIT_2412 0x20 | |
100 | #define RX8025_REG_CTRL2 0x0f | |
101 | # define RX8025_BIT_PON 0x10 | |
102 | # define RX8025_BIT_VDET 0x40 | |
103 | # define RX8025_BIT_XST 0x20 | |
1abb0dc9 DB |
104 | |
105 | ||
106 | struct ds1307 { | |
33df2ee1 | 107 | u8 offset; /* register's offset */ |
cb49a5e9 | 108 | u8 regs[11]; |
9eab0a78 AB |
109 | u16 nvram_offset; |
110 | struct bin_attribute *nvram; | |
1abb0dc9 | 111 | enum ds_type type; |
cb49a5e9 RG |
112 | unsigned long flags; |
113 | #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ | |
114 | #define HAS_ALARM 1 /* bit 1 == irq claimed */ | |
045e0e85 | 115 | struct i2c_client *client; |
1abb0dc9 | 116 | struct rtc_device *rtc; |
cb49a5e9 | 117 | struct work_struct work; |
0cc43a18 | 118 | s32 (*read_block_data)(const struct i2c_client *client, u8 command, |
30e7b039 | 119 | u8 length, u8 *values); |
0cc43a18 | 120 | s32 (*write_block_data)(const struct i2c_client *client, u8 command, |
30e7b039 | 121 | u8 length, const u8 *values); |
1abb0dc9 DB |
122 | }; |
123 | ||
045e0e85 | 124 | struct chip_desc { |
045e0e85 | 125 | unsigned alarm:1; |
9eab0a78 AB |
126 | u16 nvram_offset; |
127 | u16 nvram_size; | |
eb86c306 | 128 | u16 trickle_charger_reg; |
045e0e85 DB |
129 | }; |
130 | ||
32d322bc WS |
131 | static const struct chip_desc chips[last_ds_type] = { |
132 | [ds_1307] = { | |
9eab0a78 AB |
133 | .nvram_offset = 8, |
134 | .nvram_size = 56, | |
32d322bc WS |
135 | }, |
136 | [ds_1337] = { | |
137 | .alarm = 1, | |
138 | }, | |
139 | [ds_1338] = { | |
9eab0a78 AB |
140 | .nvram_offset = 8, |
141 | .nvram_size = 56, | |
32d322bc WS |
142 | }, |
143 | [ds_1339] = { | |
144 | .alarm = 1, | |
eb86c306 WS |
145 | .trickle_charger_reg = 0x10, |
146 | }, | |
147 | [ds_1340] = { | |
148 | .trickle_charger_reg = 0x08, | |
149 | }, | |
150 | [ds_1388] = { | |
151 | .trickle_charger_reg = 0x0a, | |
32d322bc WS |
152 | }, |
153 | [ds_3231] = { | |
154 | .alarm = 1, | |
155 | }, | |
9eab0a78 AB |
156 | [mcp7941x] = { |
157 | /* this is battery backed SRAM */ | |
158 | .nvram_offset = 0x20, | |
159 | .nvram_size = 0x40, | |
160 | }, | |
32d322bc | 161 | }; |
045e0e85 | 162 | |
3760f736 JD |
163 | static const struct i2c_device_id ds1307_id[] = { |
164 | { "ds1307", ds_1307 }, | |
165 | { "ds1337", ds_1337 }, | |
166 | { "ds1338", ds_1338 }, | |
167 | { "ds1339", ds_1339 }, | |
33df2ee1 | 168 | { "ds1388", ds_1388 }, |
3760f736 | 169 | { "ds1340", ds_1340 }, |
97f902b7 | 170 | { "ds3231", ds_3231 }, |
3760f736 | 171 | { "m41t00", m41t00 }, |
43fcb815 | 172 | { "mcp7941x", mcp7941x }, |
31c1771c | 173 | { "pt7c4338", ds_1307 }, |
a2166858 | 174 | { "rx8025", rx_8025 }, |
3760f736 JD |
175 | { } |
176 | }; | |
177 | MODULE_DEVICE_TABLE(i2c, ds1307_id); | |
1abb0dc9 | 178 | |
cb49a5e9 RG |
179 | /*----------------------------------------------------------------------*/ |
180 | ||
30e7b039 ES |
181 | #define BLOCK_DATA_MAX_TRIES 10 |
182 | ||
0cc43a18 JD |
183 | static s32 ds1307_read_block_data_once(const struct i2c_client *client, |
184 | u8 command, u8 length, u8 *values) | |
30e7b039 ES |
185 | { |
186 | s32 i, data; | |
187 | ||
188 | for (i = 0; i < length; i++) { | |
189 | data = i2c_smbus_read_byte_data(client, command + i); | |
190 | if (data < 0) | |
191 | return data; | |
192 | values[i] = data; | |
193 | } | |
194 | return i; | |
195 | } | |
196 | ||
0cc43a18 | 197 | static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command, |
30e7b039 ES |
198 | u8 length, u8 *values) |
199 | { | |
bc48b902 | 200 | u8 oldvalues[255]; |
30e7b039 ES |
201 | s32 ret; |
202 | int tries = 0; | |
203 | ||
204 | dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length); | |
205 | ret = ds1307_read_block_data_once(client, command, length, values); | |
206 | if (ret < 0) | |
207 | return ret; | |
208 | do { | |
209 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
210 | dev_err(&client->dev, | |
211 | "ds1307_read_block_data failed\n"); | |
212 | return -EIO; | |
213 | } | |
214 | memcpy(oldvalues, values, length); | |
215 | ret = ds1307_read_block_data_once(client, command, length, | |
216 | values); | |
217 | if (ret < 0) | |
218 | return ret; | |
219 | } while (memcmp(oldvalues, values, length)); | |
220 | return length; | |
221 | } | |
222 | ||
0cc43a18 | 223 | static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command, |
30e7b039 ES |
224 | u8 length, const u8 *values) |
225 | { | |
bc48b902 | 226 | u8 currvalues[255]; |
30e7b039 ES |
227 | int tries = 0; |
228 | ||
229 | dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length); | |
230 | do { | |
231 | s32 i, ret; | |
232 | ||
233 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
234 | dev_err(&client->dev, | |
235 | "ds1307_write_block_data failed\n"); | |
236 | return -EIO; | |
237 | } | |
238 | for (i = 0; i < length; i++) { | |
239 | ret = i2c_smbus_write_byte_data(client, command + i, | |
240 | values[i]); | |
241 | if (ret < 0) | |
242 | return ret; | |
243 | } | |
244 | ret = ds1307_read_block_data_once(client, command, length, | |
245 | currvalues); | |
246 | if (ret < 0) | |
247 | return ret; | |
248 | } while (memcmp(currvalues, values, length)); | |
249 | return length; | |
250 | } | |
251 | ||
252 | /*----------------------------------------------------------------------*/ | |
253 | ||
bc48b902 BA |
254 | /* These RTC devices are not designed to be connected to a SMbus adapter. |
255 | SMbus limits block operations length to 32 bytes, whereas it's not | |
256 | limited on I2C buses. As a result, accesses may exceed 32 bytes; | |
257 | in that case, split them into smaller blocks */ | |
258 | ||
259 | static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client, | |
260 | u8 command, u8 length, const u8 *values) | |
261 | { | |
262 | u8 suboffset = 0; | |
263 | ||
264 | if (length <= I2C_SMBUS_BLOCK_MAX) | |
265 | return i2c_smbus_write_i2c_block_data(client, | |
266 | command, length, values); | |
267 | ||
268 | while (suboffset < length) { | |
269 | s32 retval = i2c_smbus_write_i2c_block_data(client, | |
270 | command + suboffset, | |
271 | min(I2C_SMBUS_BLOCK_MAX, length - suboffset), | |
272 | values + suboffset); | |
273 | if (retval < 0) | |
274 | return retval; | |
275 | ||
276 | suboffset += I2C_SMBUS_BLOCK_MAX; | |
277 | } | |
278 | return length; | |
279 | } | |
280 | ||
281 | static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client, | |
282 | u8 command, u8 length, u8 *values) | |
283 | { | |
284 | u8 suboffset = 0; | |
285 | ||
286 | if (length <= I2C_SMBUS_BLOCK_MAX) | |
287 | return i2c_smbus_read_i2c_block_data(client, | |
288 | command, length, values); | |
289 | ||
290 | while (suboffset < length) { | |
291 | s32 retval = i2c_smbus_read_i2c_block_data(client, | |
292 | command + suboffset, | |
293 | min(I2C_SMBUS_BLOCK_MAX, length - suboffset), | |
294 | values + suboffset); | |
295 | if (retval < 0) | |
296 | return retval; | |
297 | ||
298 | suboffset += I2C_SMBUS_BLOCK_MAX; | |
299 | } | |
300 | return length; | |
301 | } | |
302 | ||
303 | /*----------------------------------------------------------------------*/ | |
304 | ||
cb49a5e9 RG |
305 | /* |
306 | * The IRQ logic includes a "real" handler running in IRQ context just | |
307 | * long enough to schedule this workqueue entry. We need a task context | |
308 | * to talk to the RTC, since I2C I/O calls require that; and disable the | |
309 | * IRQ until we clear its status on the chip, so that this handler can | |
310 | * work with any type of triggering (not just falling edge). | |
311 | * | |
312 | * The ds1337 and ds1339 both have two alarms, but we only use the first | |
313 | * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm | |
314 | * signal; ds1339 chips have only one alarm signal. | |
315 | */ | |
316 | static void ds1307_work(struct work_struct *work) | |
317 | { | |
318 | struct ds1307 *ds1307; | |
319 | struct i2c_client *client; | |
320 | struct mutex *lock; | |
321 | int stat, control; | |
322 | ||
323 | ds1307 = container_of(work, struct ds1307, work); | |
324 | client = ds1307->client; | |
325 | lock = &ds1307->rtc->ops_lock; | |
326 | ||
327 | mutex_lock(lock); | |
328 | stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS); | |
329 | if (stat < 0) | |
330 | goto out; | |
331 | ||
332 | if (stat & DS1337_BIT_A1I) { | |
333 | stat &= ~DS1337_BIT_A1I; | |
334 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat); | |
335 | ||
336 | control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); | |
337 | if (control < 0) | |
338 | goto out; | |
339 | ||
340 | control &= ~DS1337_BIT_A1IE; | |
341 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control); | |
342 | ||
cb49a5e9 | 343 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); |
cb49a5e9 RG |
344 | } |
345 | ||
346 | out: | |
347 | if (test_bit(HAS_ALARM, &ds1307->flags)) | |
348 | enable_irq(client->irq); | |
349 | mutex_unlock(lock); | |
350 | } | |
351 | ||
352 | static irqreturn_t ds1307_irq(int irq, void *dev_id) | |
353 | { | |
354 | struct i2c_client *client = dev_id; | |
355 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
356 | ||
357 | disable_irq_nosync(irq); | |
358 | schedule_work(&ds1307->work); | |
359 | return IRQ_HANDLED; | |
360 | } | |
361 | ||
362 | /*----------------------------------------------------------------------*/ | |
363 | ||
1abb0dc9 DB |
364 | static int ds1307_get_time(struct device *dev, struct rtc_time *t) |
365 | { | |
366 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
367 | int tmp; | |
368 | ||
045e0e85 | 369 | /* read the RTC date and time registers all at once */ |
30e7b039 | 370 | tmp = ds1307->read_block_data(ds1307->client, |
33df2ee1 | 371 | ds1307->offset, 7, ds1307->regs); |
fed40b73 | 372 | if (tmp != 7) { |
1abb0dc9 DB |
373 | dev_err(dev, "%s error %d\n", "read", tmp); |
374 | return -EIO; | |
375 | } | |
376 | ||
01a4ca16 | 377 | dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs); |
1abb0dc9 | 378 | |
fe20ba70 AB |
379 | t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f); |
380 | t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f); | |
1abb0dc9 | 381 | tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f; |
fe20ba70 AB |
382 | t->tm_hour = bcd2bin(tmp); |
383 | t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1; | |
384 | t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f); | |
1abb0dc9 | 385 | tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f; |
fe20ba70 | 386 | t->tm_mon = bcd2bin(tmp) - 1; |
1abb0dc9 DB |
387 | |
388 | /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */ | |
fe20ba70 | 389 | t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100; |
1abb0dc9 DB |
390 | |
391 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
392 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
393 | "read", t->tm_sec, t->tm_min, | |
394 | t->tm_hour, t->tm_mday, | |
395 | t->tm_mon, t->tm_year, t->tm_wday); | |
396 | ||
045e0e85 DB |
397 | /* initial clock setting can be undefined */ |
398 | return rtc_valid_tm(t); | |
1abb0dc9 DB |
399 | } |
400 | ||
401 | static int ds1307_set_time(struct device *dev, struct rtc_time *t) | |
402 | { | |
403 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
404 | int result; | |
405 | int tmp; | |
406 | u8 *buf = ds1307->regs; | |
407 | ||
408 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
409 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
11966adc JG |
410 | "write", t->tm_sec, t->tm_min, |
411 | t->tm_hour, t->tm_mday, | |
412 | t->tm_mon, t->tm_year, t->tm_wday); | |
1abb0dc9 | 413 | |
fe20ba70 AB |
414 | buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec); |
415 | buf[DS1307_REG_MIN] = bin2bcd(t->tm_min); | |
416 | buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); | |
417 | buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); | |
418 | buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); | |
419 | buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); | |
1abb0dc9 DB |
420 | |
421 | /* assume 20YY not 19YY */ | |
422 | tmp = t->tm_year - 100; | |
fe20ba70 | 423 | buf[DS1307_REG_YEAR] = bin2bcd(tmp); |
1abb0dc9 | 424 | |
be5f59f4 RG |
425 | switch (ds1307->type) { |
426 | case ds_1337: | |
427 | case ds_1339: | |
97f902b7 | 428 | case ds_3231: |
1abb0dc9 | 429 | buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY; |
be5f59f4 RG |
430 | break; |
431 | case ds_1340: | |
1abb0dc9 DB |
432 | buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN |
433 | | DS1340_BIT_CENTURY; | |
be5f59f4 | 434 | break; |
43fcb815 | 435 | case mcp7941x: |
40ce972d DA |
436 | /* |
437 | * these bits were cleared when preparing the date/time | |
438 | * values and need to be set again before writing the | |
439 | * buffer out to the device. | |
440 | */ | |
43fcb815 DA |
441 | buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST; |
442 | buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN; | |
443 | break; | |
be5f59f4 RG |
444 | default: |
445 | break; | |
446 | } | |
1abb0dc9 | 447 | |
01a4ca16 | 448 | dev_dbg(dev, "%s: %7ph\n", "write", buf); |
1abb0dc9 | 449 | |
33df2ee1 JT |
450 | result = ds1307->write_block_data(ds1307->client, |
451 | ds1307->offset, 7, buf); | |
fed40b73 BS |
452 | if (result < 0) { |
453 | dev_err(dev, "%s error %d\n", "write", result); | |
454 | return result; | |
1abb0dc9 DB |
455 | } |
456 | return 0; | |
457 | } | |
458 | ||
74d88eb2 | 459 | static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 RG |
460 | { |
461 | struct i2c_client *client = to_i2c_client(dev); | |
462 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
463 | int ret; | |
464 | ||
465 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
466 | return -EINVAL; | |
467 | ||
468 | /* read all ALARM1, ALARM2, and status registers at once */ | |
30e7b039 | 469 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
470 | DS1339_REG_ALARM1_SECS, 9, ds1307->regs); |
471 | if (ret != 9) { | |
cb49a5e9 RG |
472 | dev_err(dev, "%s error %d\n", "alarm read", ret); |
473 | return -EIO; | |
474 | } | |
475 | ||
476 | dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n", | |
477 | "alarm read", | |
478 | ds1307->regs[0], ds1307->regs[1], | |
479 | ds1307->regs[2], ds1307->regs[3], | |
480 | ds1307->regs[4], ds1307->regs[5], | |
481 | ds1307->regs[6], ds1307->regs[7], | |
482 | ds1307->regs[8]); | |
483 | ||
40ce972d DA |
484 | /* |
485 | * report alarm time (ALARM1); assume 24 hour and day-of-month modes, | |
cb49a5e9 RG |
486 | * and that all four fields are checked matches |
487 | */ | |
488 | t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f); | |
489 | t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f); | |
490 | t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f); | |
491 | t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f); | |
492 | t->time.tm_mon = -1; | |
493 | t->time.tm_year = -1; | |
494 | t->time.tm_wday = -1; | |
495 | t->time.tm_yday = -1; | |
496 | t->time.tm_isdst = -1; | |
497 | ||
498 | /* ... and status */ | |
499 | t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE); | |
500 | t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I); | |
501 | ||
502 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
503 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
504 | "alarm read", t->time.tm_sec, t->time.tm_min, | |
505 | t->time.tm_hour, t->time.tm_mday, | |
506 | t->enabled, t->pending); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
74d88eb2 | 511 | static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 | 512 | { |
40ce972d | 513 | struct i2c_client *client = to_i2c_client(dev); |
cb49a5e9 RG |
514 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
515 | unsigned char *buf = ds1307->regs; | |
516 | u8 control, status; | |
517 | int ret; | |
518 | ||
519 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
520 | return -EINVAL; | |
521 | ||
522 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
523 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
524 | "alarm set", t->time.tm_sec, t->time.tm_min, | |
525 | t->time.tm_hour, t->time.tm_mday, | |
526 | t->enabled, t->pending); | |
527 | ||
528 | /* read current status of both alarms and the chip */ | |
30e7b039 | 529 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
530 | DS1339_REG_ALARM1_SECS, 9, buf); |
531 | if (ret != 9) { | |
cb49a5e9 RG |
532 | dev_err(dev, "%s error %d\n", "alarm write", ret); |
533 | return -EIO; | |
534 | } | |
535 | control = ds1307->regs[7]; | |
536 | status = ds1307->regs[8]; | |
537 | ||
538 | dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n", | |
539 | "alarm set (old status)", | |
540 | ds1307->regs[0], ds1307->regs[1], | |
541 | ds1307->regs[2], ds1307->regs[3], | |
542 | ds1307->regs[4], ds1307->regs[5], | |
543 | ds1307->regs[6], control, status); | |
544 | ||
545 | /* set ALARM1, using 24 hour and day-of-month modes */ | |
cb49a5e9 RG |
546 | buf[0] = bin2bcd(t->time.tm_sec); |
547 | buf[1] = bin2bcd(t->time.tm_min); | |
548 | buf[2] = bin2bcd(t->time.tm_hour); | |
549 | buf[3] = bin2bcd(t->time.tm_mday); | |
550 | ||
551 | /* set ALARM2 to non-garbage */ | |
552 | buf[4] = 0; | |
553 | buf[5] = 0; | |
554 | buf[6] = 0; | |
555 | ||
556 | /* optionally enable ALARM1 */ | |
557 | buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); | |
558 | if (t->enabled) { | |
559 | dev_dbg(dev, "alarm IRQ armed\n"); | |
560 | buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ | |
561 | } | |
562 | buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); | |
563 | ||
30e7b039 | 564 | ret = ds1307->write_block_data(client, |
fed40b73 BS |
565 | DS1339_REG_ALARM1_SECS, 9, buf); |
566 | if (ret < 0) { | |
cb49a5e9 | 567 | dev_err(dev, "can't set alarm time\n"); |
fed40b73 | 568 | return ret; |
cb49a5e9 RG |
569 | } |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
16380c15 | 574 | static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) |
cb49a5e9 RG |
575 | { |
576 | struct i2c_client *client = to_i2c_client(dev); | |
577 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
578 | int ret; | |
579 | ||
16380c15 JS |
580 | if (!test_bit(HAS_ALARM, &ds1307->flags)) |
581 | return -ENOTTY; | |
cb49a5e9 | 582 | |
16380c15 JS |
583 | ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); |
584 | if (ret < 0) | |
585 | return ret; | |
cb49a5e9 | 586 | |
16380c15 | 587 | if (enabled) |
cb49a5e9 | 588 | ret |= DS1337_BIT_A1IE; |
16380c15 JS |
589 | else |
590 | ret &= ~DS1337_BIT_A1IE; | |
cb49a5e9 | 591 | |
16380c15 JS |
592 | ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret); |
593 | if (ret < 0) | |
594 | return ret; | |
cb49a5e9 RG |
595 | |
596 | return 0; | |
597 | } | |
598 | ||
ff8371ac | 599 | static const struct rtc_class_ops ds13xx_rtc_ops = { |
1abb0dc9 DB |
600 | .read_time = ds1307_get_time, |
601 | .set_time = ds1307_set_time, | |
74d88eb2 JR |
602 | .read_alarm = ds1337_read_alarm, |
603 | .set_alarm = ds1337_set_alarm, | |
16380c15 | 604 | .alarm_irq_enable = ds1307_alarm_irq_enable, |
1abb0dc9 DB |
605 | }; |
606 | ||
682d73f6 DB |
607 | /*----------------------------------------------------------------------*/ |
608 | ||
682d73f6 | 609 | static ssize_t |
2c3c8bea CW |
610 | ds1307_nvram_read(struct file *filp, struct kobject *kobj, |
611 | struct bin_attribute *attr, | |
682d73f6 DB |
612 | char *buf, loff_t off, size_t count) |
613 | { | |
614 | struct i2c_client *client; | |
615 | struct ds1307 *ds1307; | |
682d73f6 DB |
616 | int result; |
617 | ||
fcd8db00 | 618 | client = kobj_to_i2c_client(kobj); |
682d73f6 DB |
619 | ds1307 = i2c_get_clientdata(client); |
620 | ||
9eab0a78 | 621 | if (unlikely(off >= ds1307->nvram->size)) |
682d73f6 | 622 | return 0; |
9eab0a78 AB |
623 | if ((off + count) > ds1307->nvram->size) |
624 | count = ds1307->nvram->size - off; | |
682d73f6 DB |
625 | if (unlikely(!count)) |
626 | return count; | |
627 | ||
9eab0a78 AB |
628 | result = ds1307->read_block_data(client, ds1307->nvram_offset + off, |
629 | count, buf); | |
fed40b73 | 630 | if (result < 0) |
682d73f6 | 631 | dev_err(&client->dev, "%s error %d\n", "nvram read", result); |
fed40b73 | 632 | return result; |
682d73f6 DB |
633 | } |
634 | ||
635 | static ssize_t | |
2c3c8bea CW |
636 | ds1307_nvram_write(struct file *filp, struct kobject *kobj, |
637 | struct bin_attribute *attr, | |
682d73f6 DB |
638 | char *buf, loff_t off, size_t count) |
639 | { | |
640 | struct i2c_client *client; | |
30e7b039 | 641 | struct ds1307 *ds1307; |
fed40b73 | 642 | int result; |
682d73f6 | 643 | |
fcd8db00 | 644 | client = kobj_to_i2c_client(kobj); |
30e7b039 | 645 | ds1307 = i2c_get_clientdata(client); |
682d73f6 | 646 | |
9eab0a78 | 647 | if (unlikely(off >= ds1307->nvram->size)) |
682d73f6 | 648 | return -EFBIG; |
9eab0a78 AB |
649 | if ((off + count) > ds1307->nvram->size) |
650 | count = ds1307->nvram->size - off; | |
682d73f6 DB |
651 | if (unlikely(!count)) |
652 | return count; | |
653 | ||
9eab0a78 AB |
654 | result = ds1307->write_block_data(client, ds1307->nvram_offset + off, |
655 | count, buf); | |
fed40b73 BS |
656 | if (result < 0) { |
657 | dev_err(&client->dev, "%s error %d\n", "nvram write", result); | |
658 | return result; | |
659 | } | |
660 | return count; | |
682d73f6 DB |
661 | } |
662 | ||
682d73f6 DB |
663 | /*----------------------------------------------------------------------*/ |
664 | ||
5a167f45 GKH |
665 | static int ds1307_probe(struct i2c_client *client, |
666 | const struct i2c_device_id *id) | |
1abb0dc9 DB |
667 | { |
668 | struct ds1307 *ds1307; | |
669 | int err = -ENODEV; | |
1abb0dc9 | 670 | int tmp; |
3760f736 | 671 | const struct chip_desc *chip = &chips[id->driver_data]; |
c065f35c | 672 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
c8b18da7 | 673 | bool want_irq = false; |
fed40b73 | 674 | unsigned char *buf; |
01ce893d | 675 | struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); |
97f902b7 WS |
676 | static const int bbsqi_bitpos[] = { |
677 | [ds_1337] = 0, | |
678 | [ds_1339] = DS1339_BIT_BBSQI, | |
679 | [ds_3231] = DS3231_BIT_BBSQW, | |
680 | }; | |
1abb0dc9 | 681 | |
30e7b039 ES |
682 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA) |
683 | && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) | |
c065f35c DB |
684 | return -EIO; |
685 | ||
edca66d2 | 686 | ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); |
40ce972d | 687 | if (!ds1307) |
c065f35c | 688 | return -ENOMEM; |
045e0e85 | 689 | |
1abb0dc9 | 690 | i2c_set_clientdata(client, ds1307); |
33df2ee1 JT |
691 | |
692 | ds1307->client = client; | |
693 | ds1307->type = id->driver_data; | |
33df2ee1 | 694 | |
eb86c306 WS |
695 | if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg) |
696 | i2c_smbus_write_byte_data(client, chip->trickle_charger_reg, | |
697 | DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup); | |
698 | ||
fed40b73 | 699 | buf = ds1307->regs; |
30e7b039 | 700 | if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) { |
bc48b902 BA |
701 | ds1307->read_block_data = ds1307_native_smbus_read_block_data; |
702 | ds1307->write_block_data = ds1307_native_smbus_write_block_data; | |
30e7b039 ES |
703 | } else { |
704 | ds1307->read_block_data = ds1307_read_block_data; | |
705 | ds1307->write_block_data = ds1307_write_block_data; | |
706 | } | |
045e0e85 DB |
707 | |
708 | switch (ds1307->type) { | |
709 | case ds_1337: | |
710 | case ds_1339: | |
97f902b7 | 711 | case ds_3231: |
be5f59f4 | 712 | /* get registers that the "rtc" read below won't read... */ |
30e7b039 | 713 | tmp = ds1307->read_block_data(ds1307->client, |
fed40b73 | 714 | DS1337_REG_CONTROL, 2, buf); |
1abb0dc9 | 715 | if (tmp != 2) { |
6df80e21 | 716 | dev_dbg(&client->dev, "read error %d\n", tmp); |
1abb0dc9 | 717 | err = -EIO; |
edca66d2 | 718 | goto exit; |
1abb0dc9 DB |
719 | } |
720 | ||
be5f59f4 RG |
721 | /* oscillator off? turn it on, so clock can tick. */ |
722 | if (ds1307->regs[0] & DS1337_BIT_nEOSC) | |
cb49a5e9 RG |
723 | ds1307->regs[0] &= ~DS1337_BIT_nEOSC; |
724 | ||
40ce972d DA |
725 | /* |
726 | * Using IRQ? Disable the square wave and both alarms. | |
97f902b7 WS |
727 | * For some variants, be sure alarms can trigger when we're |
728 | * running on Vbackup (BBSQI/BBSQW) | |
cb49a5e9 | 729 | */ |
b24a7267 WS |
730 | if (ds1307->client->irq > 0 && chip->alarm) { |
731 | INIT_WORK(&ds1307->work, ds1307_work); | |
732 | ||
97f902b7 WS |
733 | ds1307->regs[0] |= DS1337_BIT_INTCN |
734 | | bbsqi_bitpos[ds1307->type]; | |
cb49a5e9 | 735 | ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); |
b24a7267 WS |
736 | |
737 | want_irq = true; | |
cb49a5e9 RG |
738 | } |
739 | ||
740 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, | |
741 | ds1307->regs[0]); | |
be5f59f4 RG |
742 | |
743 | /* oscillator fault? clear flag, and warn */ | |
744 | if (ds1307->regs[1] & DS1337_BIT_OSF) { | |
745 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, | |
746 | ds1307->regs[1] & ~DS1337_BIT_OSF); | |
747 | dev_warn(&client->dev, "SET TIME!\n"); | |
1abb0dc9 | 748 | } |
045e0e85 | 749 | break; |
a2166858 MF |
750 | |
751 | case rx_8025: | |
752 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
753 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
754 | if (tmp != 2) { | |
6df80e21 | 755 | dev_dbg(&client->dev, "read error %d\n", tmp); |
a2166858 | 756 | err = -EIO; |
edca66d2 | 757 | goto exit; |
a2166858 MF |
758 | } |
759 | ||
760 | /* oscillator off? turn it on, so clock can tick. */ | |
761 | if (!(ds1307->regs[1] & RX8025_BIT_XST)) { | |
762 | ds1307->regs[1] |= RX8025_BIT_XST; | |
763 | i2c_smbus_write_byte_data(client, | |
764 | RX8025_REG_CTRL2 << 4 | 0x08, | |
765 | ds1307->regs[1]); | |
766 | dev_warn(&client->dev, | |
767 | "oscillator stop detected - SET TIME!\n"); | |
768 | } | |
769 | ||
770 | if (ds1307->regs[1] & RX8025_BIT_PON) { | |
771 | ds1307->regs[1] &= ~RX8025_BIT_PON; | |
772 | i2c_smbus_write_byte_data(client, | |
773 | RX8025_REG_CTRL2 << 4 | 0x08, | |
774 | ds1307->regs[1]); | |
775 | dev_warn(&client->dev, "power-on detected\n"); | |
776 | } | |
777 | ||
778 | if (ds1307->regs[1] & RX8025_BIT_VDET) { | |
779 | ds1307->regs[1] &= ~RX8025_BIT_VDET; | |
780 | i2c_smbus_write_byte_data(client, | |
781 | RX8025_REG_CTRL2 << 4 | 0x08, | |
782 | ds1307->regs[1]); | |
783 | dev_warn(&client->dev, "voltage drop detected\n"); | |
784 | } | |
785 | ||
786 | /* make sure we are running in 24hour mode */ | |
787 | if (!(ds1307->regs[0] & RX8025_BIT_2412)) { | |
788 | u8 hour; | |
789 | ||
790 | /* switch to 24 hour mode */ | |
791 | i2c_smbus_write_byte_data(client, | |
792 | RX8025_REG_CTRL1 << 4 | 0x08, | |
793 | ds1307->regs[0] | | |
794 | RX8025_BIT_2412); | |
795 | ||
796 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
797 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
798 | if (tmp != 2) { | |
6df80e21 | 799 | dev_dbg(&client->dev, "read error %d\n", tmp); |
a2166858 | 800 | err = -EIO; |
edca66d2 | 801 | goto exit; |
a2166858 MF |
802 | } |
803 | ||
804 | /* correct hour */ | |
805 | hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]); | |
806 | if (hour == 12) | |
807 | hour = 0; | |
808 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
809 | hour += 12; | |
810 | ||
811 | i2c_smbus_write_byte_data(client, | |
812 | DS1307_REG_HOUR << 4 | 0x08, | |
813 | hour); | |
814 | } | |
815 | break; | |
33df2ee1 JT |
816 | case ds_1388: |
817 | ds1307->offset = 1; /* Seconds starts at 1 */ | |
818 | break; | |
045e0e85 DB |
819 | default: |
820 | break; | |
821 | } | |
1abb0dc9 DB |
822 | |
823 | read_rtc: | |
824 | /* read RTC registers */ | |
96fc3a45 | 825 | tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf); |
fed40b73 | 826 | if (tmp != 8) { |
6df80e21 | 827 | dev_dbg(&client->dev, "read error %d\n", tmp); |
1abb0dc9 | 828 | err = -EIO; |
edca66d2 | 829 | goto exit; |
1abb0dc9 DB |
830 | } |
831 | ||
40ce972d DA |
832 | /* |
833 | * minimal sanity checking; some chips (like DS1340) don't | |
1abb0dc9 DB |
834 | * specify the extra bits as must-be-zero, but there are |
835 | * still a few values that are clearly out-of-range. | |
836 | */ | |
837 | tmp = ds1307->regs[DS1307_REG_SECS]; | |
045e0e85 DB |
838 | switch (ds1307->type) { |
839 | case ds_1307: | |
045e0e85 | 840 | case m41t00: |
be5f59f4 | 841 | /* clock halted? turn it on, so clock can tick. */ |
045e0e85 | 842 | if (tmp & DS1307_BIT_CH) { |
be5f59f4 RG |
843 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
844 | dev_warn(&client->dev, "SET TIME!\n"); | |
045e0e85 | 845 | goto read_rtc; |
1abb0dc9 | 846 | } |
045e0e85 | 847 | break; |
be5f59f4 RG |
848 | case ds_1338: |
849 | /* clock halted? turn it on, so clock can tick. */ | |
045e0e85 | 850 | if (tmp & DS1307_BIT_CH) |
be5f59f4 RG |
851 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
852 | ||
853 | /* oscillator fault? clear flag, and warn */ | |
854 | if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { | |
855 | i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL, | |
bd16f9eb | 856 | ds1307->regs[DS1307_REG_CONTROL] |
be5f59f4 RG |
857 | & ~DS1338_BIT_OSF); |
858 | dev_warn(&client->dev, "SET TIME!\n"); | |
859 | goto read_rtc; | |
860 | } | |
045e0e85 | 861 | break; |
fcd8db00 R |
862 | case ds_1340: |
863 | /* clock halted? turn it on, so clock can tick. */ | |
864 | if (tmp & DS1340_BIT_nEOSC) | |
865 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); | |
866 | ||
867 | tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG); | |
868 | if (tmp < 0) { | |
6df80e21 | 869 | dev_dbg(&client->dev, "read error %d\n", tmp); |
fcd8db00 | 870 | err = -EIO; |
edca66d2 | 871 | goto exit; |
fcd8db00 R |
872 | } |
873 | ||
874 | /* oscillator fault? clear flag, and warn */ | |
875 | if (tmp & DS1340_BIT_OSF) { | |
876 | i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0); | |
877 | dev_warn(&client->dev, "SET TIME!\n"); | |
878 | } | |
43fcb815 DA |
879 | break; |
880 | case mcp7941x: | |
881 | /* make sure that the backup battery is enabled */ | |
882 | if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) { | |
883 | i2c_smbus_write_byte_data(client, DS1307_REG_WDAY, | |
884 | ds1307->regs[DS1307_REG_WDAY] | |
885 | | MCP7941X_BIT_VBATEN); | |
886 | } | |
887 | ||
888 | /* clock halted? turn it on, so clock can tick. */ | |
889 | if (!(tmp & MCP7941X_BIT_ST)) { | |
890 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, | |
891 | MCP7941X_BIT_ST); | |
892 | dev_warn(&client->dev, "SET TIME!\n"); | |
893 | goto read_rtc; | |
894 | } | |
895 | ||
fcd8db00 | 896 | break; |
32d322bc | 897 | default: |
045e0e85 | 898 | break; |
1abb0dc9 | 899 | } |
045e0e85 | 900 | |
1abb0dc9 | 901 | tmp = ds1307->regs[DS1307_REG_HOUR]; |
c065f35c DB |
902 | switch (ds1307->type) { |
903 | case ds_1340: | |
904 | case m41t00: | |
40ce972d DA |
905 | /* |
906 | * NOTE: ignores century bits; fix before deploying | |
c065f35c DB |
907 | * systems that will run through year 2100. |
908 | */ | |
909 | break; | |
a2166858 MF |
910 | case rx_8025: |
911 | break; | |
c065f35c DB |
912 | default: |
913 | if (!(tmp & DS1307_BIT_12HR)) | |
914 | break; | |
915 | ||
40ce972d DA |
916 | /* |
917 | * Be sure we're in 24 hour mode. Multi-master systems | |
c065f35c DB |
918 | * take note... |
919 | */ | |
fe20ba70 | 920 | tmp = bcd2bin(tmp & 0x1f); |
c065f35c DB |
921 | if (tmp == 12) |
922 | tmp = 0; | |
923 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
924 | tmp += 12; | |
1abb0dc9 | 925 | i2c_smbus_write_byte_data(client, |
96fc3a45 | 926 | ds1307->offset + DS1307_REG_HOUR, |
fe20ba70 | 927 | bin2bcd(tmp)); |
1abb0dc9 DB |
928 | } |
929 | ||
5ea73514 | 930 | device_set_wakeup_capable(&client->dev, want_irq); |
edca66d2 | 931 | ds1307->rtc = devm_rtc_device_register(&client->dev, client->name, |
1abb0dc9 DB |
932 | &ds13xx_rtc_ops, THIS_MODULE); |
933 | if (IS_ERR(ds1307->rtc)) { | |
4071ea25 | 934 | return PTR_ERR(ds1307->rtc); |
1abb0dc9 DB |
935 | } |
936 | ||
cb49a5e9 | 937 | if (want_irq) { |
43d15bcd | 938 | err = request_irq(client->irq, ds1307_irq, IRQF_SHARED, |
cb49a5e9 RG |
939 | ds1307->rtc->name, client); |
940 | if (err) { | |
4071ea25 AZ |
941 | client->irq = 0; |
942 | dev_err(&client->dev, "unable to request IRQ!\n"); | |
943 | } else { | |
26b3c01f | 944 | |
4071ea25 AZ |
945 | set_bit(HAS_ALARM, &ds1307->flags); |
946 | dev_dbg(&client->dev, "got IRQ %d\n", client->irq); | |
947 | } | |
cb49a5e9 RG |
948 | } |
949 | ||
9eab0a78 | 950 | if (chip->nvram_size) { |
4071ea25 | 951 | |
edca66d2 JH |
952 | ds1307->nvram = devm_kzalloc(&client->dev, |
953 | sizeof(struct bin_attribute), | |
954 | GFP_KERNEL); | |
9eab0a78 | 955 | if (!ds1307->nvram) { |
4071ea25 AZ |
956 | dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n"); |
957 | } else { | |
958 | ||
959 | ds1307->nvram->attr.name = "nvram"; | |
960 | ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR; | |
961 | ||
962 | sysfs_bin_attr_init(ds1307->nvram); | |
963 | ||
964 | ds1307->nvram->read = ds1307_nvram_read; | |
965 | ds1307->nvram->write = ds1307_nvram_write; | |
966 | ds1307->nvram->size = chip->nvram_size; | |
967 | ds1307->nvram_offset = chip->nvram_offset; | |
968 | ||
969 | err = sysfs_create_bin_file(&client->dev.kobj, | |
970 | ds1307->nvram); | |
971 | if (err) { | |
972 | dev_err(&client->dev, | |
973 | "unable to create sysfs file: %s\n", | |
974 | ds1307->nvram->attr.name); | |
975 | } else { | |
976 | set_bit(HAS_NVRAM, &ds1307->flags); | |
977 | dev_info(&client->dev, "%zu bytes nvram\n", | |
978 | ds1307->nvram->size); | |
979 | } | |
9eab0a78 | 980 | } |
682d73f6 DB |
981 | } |
982 | ||
1abb0dc9 DB |
983 | return 0; |
984 | ||
edca66d2 | 985 | exit: |
1abb0dc9 DB |
986 | return err; |
987 | } | |
988 | ||
5a167f45 | 989 | static int ds1307_remove(struct i2c_client *client) |
1abb0dc9 | 990 | { |
40ce972d | 991 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
cb49a5e9 RG |
992 | |
993 | if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) { | |
994 | free_irq(client->irq, client); | |
995 | cancel_work_sync(&ds1307->work); | |
996 | } | |
1abb0dc9 | 997 | |
edca66d2 | 998 | if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) |
9eab0a78 | 999 | sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram); |
682d73f6 | 1000 | |
1abb0dc9 DB |
1001 | return 0; |
1002 | } | |
1003 | ||
1004 | static struct i2c_driver ds1307_driver = { | |
1005 | .driver = { | |
c065f35c | 1006 | .name = "rtc-ds1307", |
1abb0dc9 DB |
1007 | .owner = THIS_MODULE, |
1008 | }, | |
c065f35c | 1009 | .probe = ds1307_probe, |
5a167f45 | 1010 | .remove = ds1307_remove, |
3760f736 | 1011 | .id_table = ds1307_id, |
1abb0dc9 DB |
1012 | }; |
1013 | ||
0abc9201 | 1014 | module_i2c_driver(ds1307_driver); |
1abb0dc9 DB |
1015 | |
1016 | MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); | |
1017 | MODULE_LICENSE("GPL"); |