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Commit | Line | Data |
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1abb0dc9 DB |
1 | /* |
2 | * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. | |
3 | * | |
4 | * Copyright (C) 2005 James Chapman (ds1337 core) | |
5 | * Copyright (C) 2006 David Brownell | |
a2166858 | 6 | * Copyright (C) 2009 Matthias Fuchs (rx8025 support) |
bc48b902 | 7 | * Copyright (C) 2012 Bertrand Achard (nvram access fixes) |
1abb0dc9 DB |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
eac7237f NM |
14 | #include <linux/bcd.h> |
15 | #include <linux/i2c.h> | |
1abb0dc9 | 16 | #include <linux/init.h> |
eac7237f NM |
17 | #include <linux/module.h> |
18 | #include <linux/rtc/ds1307.h> | |
19 | #include <linux/rtc.h> | |
1abb0dc9 | 20 | #include <linux/slab.h> |
1abb0dc9 | 21 | #include <linux/string.h> |
445c0207 AM |
22 | #include <linux/hwmon.h> |
23 | #include <linux/hwmon-sysfs.h> | |
1abb0dc9 | 24 | |
40ce972d DA |
25 | /* |
26 | * We can't determine type by probing, but if we expect pre-Linux code | |
1abb0dc9 DB |
27 | * to have set the chip up as a clock (turning on the oscillator and |
28 | * setting the date and time), Linux can ignore the non-clock features. | |
29 | * That's a natural job for a factory or repair bench. | |
1abb0dc9 DB |
30 | */ |
31 | enum ds_type { | |
045e0e85 DB |
32 | ds_1307, |
33 | ds_1337, | |
34 | ds_1338, | |
35 | ds_1339, | |
36 | ds_1340, | |
33df2ee1 | 37 | ds_1388, |
97f902b7 | 38 | ds_3231, |
045e0e85 | 39 | m41t00, |
f4199f85 | 40 | mcp794xx, |
a2166858 | 41 | rx_8025, |
32d322bc | 42 | last_ds_type /* always last */ |
40ce972d | 43 | /* rs5c372 too? different address... */ |
1abb0dc9 DB |
44 | }; |
45 | ||
1abb0dc9 DB |
46 | |
47 | /* RTC registers don't differ much, except for the century flag */ | |
48 | #define DS1307_REG_SECS 0x00 /* 00-59 */ | |
49 | # define DS1307_BIT_CH 0x80 | |
be5f59f4 | 50 | # define DS1340_BIT_nEOSC 0x80 |
f4199f85 | 51 | # define MCP794XX_BIT_ST 0x80 |
1abb0dc9 DB |
52 | #define DS1307_REG_MIN 0x01 /* 00-59 */ |
53 | #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ | |
c065f35c DB |
54 | # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ |
55 | # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ | |
1abb0dc9 DB |
56 | # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ |
57 | # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ | |
58 | #define DS1307_REG_WDAY 0x03 /* 01-07 */ | |
f4199f85 | 59 | # define MCP794XX_BIT_VBATEN 0x08 |
1abb0dc9 DB |
60 | #define DS1307_REG_MDAY 0x04 /* 01-31 */ |
61 | #define DS1307_REG_MONTH 0x05 /* 01-12 */ | |
62 | # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ | |
63 | #define DS1307_REG_YEAR 0x06 /* 00-99 */ | |
64 | ||
40ce972d DA |
65 | /* |
66 | * Other registers (control, status, alarms, trickle charge, NVRAM, etc) | |
045e0e85 DB |
67 | * start at 7, and they differ a LOT. Only control and status matter for |
68 | * basic RTC date and time functionality; be careful using them. | |
1abb0dc9 | 69 | */ |
045e0e85 | 70 | #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ |
1abb0dc9 | 71 | # define DS1307_BIT_OUT 0x80 |
be5f59f4 | 72 | # define DS1338_BIT_OSF 0x20 |
1abb0dc9 DB |
73 | # define DS1307_BIT_SQWE 0x10 |
74 | # define DS1307_BIT_RS1 0x02 | |
75 | # define DS1307_BIT_RS0 0x01 | |
76 | #define DS1337_REG_CONTROL 0x0e | |
77 | # define DS1337_BIT_nEOSC 0x80 | |
cb49a5e9 | 78 | # define DS1339_BIT_BBSQI 0x20 |
97f902b7 | 79 | # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ |
1abb0dc9 DB |
80 | # define DS1337_BIT_RS2 0x10 |
81 | # define DS1337_BIT_RS1 0x08 | |
82 | # define DS1337_BIT_INTCN 0x04 | |
83 | # define DS1337_BIT_A2IE 0x02 | |
84 | # define DS1337_BIT_A1IE 0x01 | |
045e0e85 DB |
85 | #define DS1340_REG_CONTROL 0x07 |
86 | # define DS1340_BIT_OUT 0x80 | |
87 | # define DS1340_BIT_FT 0x40 | |
88 | # define DS1340_BIT_CALIB_SIGN 0x20 | |
89 | # define DS1340_M_CALIBRATION 0x1f | |
be5f59f4 RG |
90 | #define DS1340_REG_FLAG 0x09 |
91 | # define DS1340_BIT_OSF 0x80 | |
1abb0dc9 DB |
92 | #define DS1337_REG_STATUS 0x0f |
93 | # define DS1337_BIT_OSF 0x80 | |
94 | # define DS1337_BIT_A2I 0x02 | |
95 | # define DS1337_BIT_A1I 0x01 | |
cb49a5e9 | 96 | #define DS1339_REG_ALARM1_SECS 0x07 |
eb86c306 WS |
97 | |
98 | #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 | |
1abb0dc9 | 99 | |
a2166858 MF |
100 | #define RX8025_REG_CTRL1 0x0e |
101 | # define RX8025_BIT_2412 0x20 | |
102 | #define RX8025_REG_CTRL2 0x0f | |
103 | # define RX8025_BIT_PON 0x10 | |
104 | # define RX8025_BIT_VDET 0x40 | |
105 | # define RX8025_BIT_XST 0x20 | |
1abb0dc9 DB |
106 | |
107 | ||
108 | struct ds1307 { | |
33df2ee1 | 109 | u8 offset; /* register's offset */ |
cb49a5e9 | 110 | u8 regs[11]; |
9eab0a78 AB |
111 | u16 nvram_offset; |
112 | struct bin_attribute *nvram; | |
1abb0dc9 | 113 | enum ds_type type; |
cb49a5e9 RG |
114 | unsigned long flags; |
115 | #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ | |
116 | #define HAS_ALARM 1 /* bit 1 == irq claimed */ | |
045e0e85 | 117 | struct i2c_client *client; |
1abb0dc9 | 118 | struct rtc_device *rtc; |
0cc43a18 | 119 | s32 (*read_block_data)(const struct i2c_client *client, u8 command, |
30e7b039 | 120 | u8 length, u8 *values); |
0cc43a18 | 121 | s32 (*write_block_data)(const struct i2c_client *client, u8 command, |
30e7b039 | 122 | u8 length, const u8 *values); |
1abb0dc9 DB |
123 | }; |
124 | ||
045e0e85 | 125 | struct chip_desc { |
045e0e85 | 126 | unsigned alarm:1; |
9eab0a78 AB |
127 | u16 nvram_offset; |
128 | u16 nvram_size; | |
eb86c306 | 129 | u16 trickle_charger_reg; |
33b04b7b MV |
130 | u8 trickle_charger_setup; |
131 | u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool); | |
045e0e85 DB |
132 | }; |
133 | ||
33b04b7b MV |
134 | static u8 do_trickle_setup_ds1339(struct i2c_client *, |
135 | uint32_t ohms, bool diode); | |
136 | ||
137 | static struct chip_desc chips[last_ds_type] = { | |
32d322bc | 138 | [ds_1307] = { |
9eab0a78 AB |
139 | .nvram_offset = 8, |
140 | .nvram_size = 56, | |
32d322bc WS |
141 | }, |
142 | [ds_1337] = { | |
143 | .alarm = 1, | |
144 | }, | |
145 | [ds_1338] = { | |
9eab0a78 AB |
146 | .nvram_offset = 8, |
147 | .nvram_size = 56, | |
32d322bc WS |
148 | }, |
149 | [ds_1339] = { | |
150 | .alarm = 1, | |
eb86c306 | 151 | .trickle_charger_reg = 0x10, |
33b04b7b | 152 | .do_trickle_setup = &do_trickle_setup_ds1339, |
eb86c306 WS |
153 | }, |
154 | [ds_1340] = { | |
155 | .trickle_charger_reg = 0x08, | |
156 | }, | |
157 | [ds_1388] = { | |
158 | .trickle_charger_reg = 0x0a, | |
32d322bc WS |
159 | }, |
160 | [ds_3231] = { | |
161 | .alarm = 1, | |
162 | }, | |
f4199f85 | 163 | [mcp794xx] = { |
1d1945d2 | 164 | .alarm = 1, |
9eab0a78 AB |
165 | /* this is battery backed SRAM */ |
166 | .nvram_offset = 0x20, | |
167 | .nvram_size = 0x40, | |
168 | }, | |
32d322bc | 169 | }; |
045e0e85 | 170 | |
3760f736 JD |
171 | static const struct i2c_device_id ds1307_id[] = { |
172 | { "ds1307", ds_1307 }, | |
173 | { "ds1337", ds_1337 }, | |
174 | { "ds1338", ds_1338 }, | |
175 | { "ds1339", ds_1339 }, | |
33df2ee1 | 176 | { "ds1388", ds_1388 }, |
3760f736 | 177 | { "ds1340", ds_1340 }, |
97f902b7 | 178 | { "ds3231", ds_3231 }, |
3760f736 | 179 | { "m41t00", m41t00 }, |
f4199f85 TN |
180 | { "mcp7940x", mcp794xx }, |
181 | { "mcp7941x", mcp794xx }, | |
31c1771c | 182 | { "pt7c4338", ds_1307 }, |
a2166858 | 183 | { "rx8025", rx_8025 }, |
3760f736 JD |
184 | { } |
185 | }; | |
186 | MODULE_DEVICE_TABLE(i2c, ds1307_id); | |
1abb0dc9 | 187 | |
cb49a5e9 RG |
188 | /*----------------------------------------------------------------------*/ |
189 | ||
30e7b039 ES |
190 | #define BLOCK_DATA_MAX_TRIES 10 |
191 | ||
0cc43a18 JD |
192 | static s32 ds1307_read_block_data_once(const struct i2c_client *client, |
193 | u8 command, u8 length, u8 *values) | |
30e7b039 ES |
194 | { |
195 | s32 i, data; | |
196 | ||
197 | for (i = 0; i < length; i++) { | |
198 | data = i2c_smbus_read_byte_data(client, command + i); | |
199 | if (data < 0) | |
200 | return data; | |
201 | values[i] = data; | |
202 | } | |
203 | return i; | |
204 | } | |
205 | ||
0cc43a18 | 206 | static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command, |
30e7b039 ES |
207 | u8 length, u8 *values) |
208 | { | |
bc48b902 | 209 | u8 oldvalues[255]; |
30e7b039 ES |
210 | s32 ret; |
211 | int tries = 0; | |
212 | ||
213 | dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length); | |
214 | ret = ds1307_read_block_data_once(client, command, length, values); | |
215 | if (ret < 0) | |
216 | return ret; | |
217 | do { | |
218 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
219 | dev_err(&client->dev, | |
220 | "ds1307_read_block_data failed\n"); | |
221 | return -EIO; | |
222 | } | |
223 | memcpy(oldvalues, values, length); | |
224 | ret = ds1307_read_block_data_once(client, command, length, | |
225 | values); | |
226 | if (ret < 0) | |
227 | return ret; | |
228 | } while (memcmp(oldvalues, values, length)); | |
229 | return length; | |
230 | } | |
231 | ||
0cc43a18 | 232 | static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command, |
30e7b039 ES |
233 | u8 length, const u8 *values) |
234 | { | |
bc48b902 | 235 | u8 currvalues[255]; |
30e7b039 ES |
236 | int tries = 0; |
237 | ||
238 | dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length); | |
239 | do { | |
240 | s32 i, ret; | |
241 | ||
242 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
243 | dev_err(&client->dev, | |
244 | "ds1307_write_block_data failed\n"); | |
245 | return -EIO; | |
246 | } | |
247 | for (i = 0; i < length; i++) { | |
248 | ret = i2c_smbus_write_byte_data(client, command + i, | |
249 | values[i]); | |
250 | if (ret < 0) | |
251 | return ret; | |
252 | } | |
253 | ret = ds1307_read_block_data_once(client, command, length, | |
254 | currvalues); | |
255 | if (ret < 0) | |
256 | return ret; | |
257 | } while (memcmp(currvalues, values, length)); | |
258 | return length; | |
259 | } | |
260 | ||
261 | /*----------------------------------------------------------------------*/ | |
262 | ||
bc48b902 BA |
263 | /* These RTC devices are not designed to be connected to a SMbus adapter. |
264 | SMbus limits block operations length to 32 bytes, whereas it's not | |
265 | limited on I2C buses. As a result, accesses may exceed 32 bytes; | |
266 | in that case, split them into smaller blocks */ | |
267 | ||
268 | static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client, | |
269 | u8 command, u8 length, const u8 *values) | |
270 | { | |
271 | u8 suboffset = 0; | |
272 | ||
273 | if (length <= I2C_SMBUS_BLOCK_MAX) | |
274 | return i2c_smbus_write_i2c_block_data(client, | |
275 | command, length, values); | |
276 | ||
277 | while (suboffset < length) { | |
278 | s32 retval = i2c_smbus_write_i2c_block_data(client, | |
279 | command + suboffset, | |
280 | min(I2C_SMBUS_BLOCK_MAX, length - suboffset), | |
281 | values + suboffset); | |
282 | if (retval < 0) | |
283 | return retval; | |
284 | ||
285 | suboffset += I2C_SMBUS_BLOCK_MAX; | |
286 | } | |
287 | return length; | |
288 | } | |
289 | ||
290 | static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client, | |
291 | u8 command, u8 length, u8 *values) | |
292 | { | |
293 | u8 suboffset = 0; | |
294 | ||
295 | if (length <= I2C_SMBUS_BLOCK_MAX) | |
296 | return i2c_smbus_read_i2c_block_data(client, | |
297 | command, length, values); | |
298 | ||
299 | while (suboffset < length) { | |
300 | s32 retval = i2c_smbus_read_i2c_block_data(client, | |
301 | command + suboffset, | |
302 | min(I2C_SMBUS_BLOCK_MAX, length - suboffset), | |
303 | values + suboffset); | |
304 | if (retval < 0) | |
305 | return retval; | |
306 | ||
307 | suboffset += I2C_SMBUS_BLOCK_MAX; | |
308 | } | |
309 | return length; | |
310 | } | |
311 | ||
312 | /*----------------------------------------------------------------------*/ | |
313 | ||
cb49a5e9 | 314 | /* |
cb49a5e9 RG |
315 | * The ds1337 and ds1339 both have two alarms, but we only use the first |
316 | * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm | |
317 | * signal; ds1339 chips have only one alarm signal. | |
318 | */ | |
2fb07a10 | 319 | static irqreturn_t ds1307_irq(int irq, void *dev_id) |
cb49a5e9 | 320 | { |
2fb07a10 FB |
321 | struct i2c_client *client = dev_id; |
322 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
323 | struct mutex *lock = &ds1307->rtc->ops_lock; | |
cb49a5e9 RG |
324 | int stat, control; |
325 | ||
cb49a5e9 RG |
326 | mutex_lock(lock); |
327 | stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS); | |
328 | if (stat < 0) | |
329 | goto out; | |
330 | ||
331 | if (stat & DS1337_BIT_A1I) { | |
332 | stat &= ~DS1337_BIT_A1I; | |
333 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat); | |
334 | ||
335 | control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); | |
336 | if (control < 0) | |
337 | goto out; | |
338 | ||
339 | control &= ~DS1337_BIT_A1IE; | |
340 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control); | |
341 | ||
cb49a5e9 | 342 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); |
cb49a5e9 RG |
343 | } |
344 | ||
345 | out: | |
cb49a5e9 | 346 | mutex_unlock(lock); |
cb49a5e9 | 347 | |
cb49a5e9 RG |
348 | return IRQ_HANDLED; |
349 | } | |
350 | ||
351 | /*----------------------------------------------------------------------*/ | |
352 | ||
1abb0dc9 DB |
353 | static int ds1307_get_time(struct device *dev, struct rtc_time *t) |
354 | { | |
355 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
356 | int tmp; | |
357 | ||
045e0e85 | 358 | /* read the RTC date and time registers all at once */ |
30e7b039 | 359 | tmp = ds1307->read_block_data(ds1307->client, |
33df2ee1 | 360 | ds1307->offset, 7, ds1307->regs); |
fed40b73 | 361 | if (tmp != 7) { |
1abb0dc9 DB |
362 | dev_err(dev, "%s error %d\n", "read", tmp); |
363 | return -EIO; | |
364 | } | |
365 | ||
01a4ca16 | 366 | dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs); |
1abb0dc9 | 367 | |
fe20ba70 AB |
368 | t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f); |
369 | t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f); | |
1abb0dc9 | 370 | tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f; |
fe20ba70 AB |
371 | t->tm_hour = bcd2bin(tmp); |
372 | t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1; | |
373 | t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f); | |
1abb0dc9 | 374 | tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f; |
fe20ba70 | 375 | t->tm_mon = bcd2bin(tmp) - 1; |
1abb0dc9 DB |
376 | |
377 | /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */ | |
fe20ba70 | 378 | t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100; |
1abb0dc9 DB |
379 | |
380 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
381 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
382 | "read", t->tm_sec, t->tm_min, | |
383 | t->tm_hour, t->tm_mday, | |
384 | t->tm_mon, t->tm_year, t->tm_wday); | |
385 | ||
045e0e85 DB |
386 | /* initial clock setting can be undefined */ |
387 | return rtc_valid_tm(t); | |
1abb0dc9 DB |
388 | } |
389 | ||
390 | static int ds1307_set_time(struct device *dev, struct rtc_time *t) | |
391 | { | |
392 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
393 | int result; | |
394 | int tmp; | |
395 | u8 *buf = ds1307->regs; | |
396 | ||
397 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
398 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
11966adc JG |
399 | "write", t->tm_sec, t->tm_min, |
400 | t->tm_hour, t->tm_mday, | |
401 | t->tm_mon, t->tm_year, t->tm_wday); | |
1abb0dc9 | 402 | |
fe20ba70 AB |
403 | buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec); |
404 | buf[DS1307_REG_MIN] = bin2bcd(t->tm_min); | |
405 | buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); | |
406 | buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); | |
407 | buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); | |
408 | buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); | |
1abb0dc9 DB |
409 | |
410 | /* assume 20YY not 19YY */ | |
411 | tmp = t->tm_year - 100; | |
fe20ba70 | 412 | buf[DS1307_REG_YEAR] = bin2bcd(tmp); |
1abb0dc9 | 413 | |
be5f59f4 RG |
414 | switch (ds1307->type) { |
415 | case ds_1337: | |
416 | case ds_1339: | |
97f902b7 | 417 | case ds_3231: |
1abb0dc9 | 418 | buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY; |
be5f59f4 RG |
419 | break; |
420 | case ds_1340: | |
1abb0dc9 DB |
421 | buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN |
422 | | DS1340_BIT_CENTURY; | |
be5f59f4 | 423 | break; |
f4199f85 | 424 | case mcp794xx: |
40ce972d DA |
425 | /* |
426 | * these bits were cleared when preparing the date/time | |
427 | * values and need to be set again before writing the | |
428 | * buffer out to the device. | |
429 | */ | |
f4199f85 TN |
430 | buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST; |
431 | buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; | |
43fcb815 | 432 | break; |
be5f59f4 RG |
433 | default: |
434 | break; | |
435 | } | |
1abb0dc9 | 436 | |
01a4ca16 | 437 | dev_dbg(dev, "%s: %7ph\n", "write", buf); |
1abb0dc9 | 438 | |
33df2ee1 JT |
439 | result = ds1307->write_block_data(ds1307->client, |
440 | ds1307->offset, 7, buf); | |
fed40b73 BS |
441 | if (result < 0) { |
442 | dev_err(dev, "%s error %d\n", "write", result); | |
443 | return result; | |
1abb0dc9 DB |
444 | } |
445 | return 0; | |
446 | } | |
447 | ||
74d88eb2 | 448 | static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 RG |
449 | { |
450 | struct i2c_client *client = to_i2c_client(dev); | |
451 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
452 | int ret; | |
453 | ||
454 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
455 | return -EINVAL; | |
456 | ||
457 | /* read all ALARM1, ALARM2, and status registers at once */ | |
30e7b039 | 458 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
459 | DS1339_REG_ALARM1_SECS, 9, ds1307->regs); |
460 | if (ret != 9) { | |
cb49a5e9 RG |
461 | dev_err(dev, "%s error %d\n", "alarm read", ret); |
462 | return -EIO; | |
463 | } | |
464 | ||
ff67abd2 RV |
465 | dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", |
466 | &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]); | |
cb49a5e9 | 467 | |
40ce972d DA |
468 | /* |
469 | * report alarm time (ALARM1); assume 24 hour and day-of-month modes, | |
cb49a5e9 RG |
470 | * and that all four fields are checked matches |
471 | */ | |
472 | t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f); | |
473 | t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f); | |
474 | t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f); | |
475 | t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f); | |
476 | t->time.tm_mon = -1; | |
477 | t->time.tm_year = -1; | |
478 | t->time.tm_wday = -1; | |
479 | t->time.tm_yday = -1; | |
480 | t->time.tm_isdst = -1; | |
481 | ||
482 | /* ... and status */ | |
483 | t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE); | |
484 | t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I); | |
485 | ||
486 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
487 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
488 | "alarm read", t->time.tm_sec, t->time.tm_min, | |
489 | t->time.tm_hour, t->time.tm_mday, | |
490 | t->enabled, t->pending); | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
74d88eb2 | 495 | static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 | 496 | { |
40ce972d | 497 | struct i2c_client *client = to_i2c_client(dev); |
cb49a5e9 RG |
498 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
499 | unsigned char *buf = ds1307->regs; | |
500 | u8 control, status; | |
501 | int ret; | |
502 | ||
503 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
504 | return -EINVAL; | |
505 | ||
506 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
507 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
508 | "alarm set", t->time.tm_sec, t->time.tm_min, | |
509 | t->time.tm_hour, t->time.tm_mday, | |
510 | t->enabled, t->pending); | |
511 | ||
512 | /* read current status of both alarms and the chip */ | |
30e7b039 | 513 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
514 | DS1339_REG_ALARM1_SECS, 9, buf); |
515 | if (ret != 9) { | |
cb49a5e9 RG |
516 | dev_err(dev, "%s error %d\n", "alarm write", ret); |
517 | return -EIO; | |
518 | } | |
519 | control = ds1307->regs[7]; | |
520 | status = ds1307->regs[8]; | |
521 | ||
ff67abd2 RV |
522 | dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", |
523 | &ds1307->regs[0], &ds1307->regs[4], control, status); | |
cb49a5e9 RG |
524 | |
525 | /* set ALARM1, using 24 hour and day-of-month modes */ | |
cb49a5e9 RG |
526 | buf[0] = bin2bcd(t->time.tm_sec); |
527 | buf[1] = bin2bcd(t->time.tm_min); | |
528 | buf[2] = bin2bcd(t->time.tm_hour); | |
529 | buf[3] = bin2bcd(t->time.tm_mday); | |
530 | ||
531 | /* set ALARM2 to non-garbage */ | |
532 | buf[4] = 0; | |
533 | buf[5] = 0; | |
534 | buf[6] = 0; | |
535 | ||
536 | /* optionally enable ALARM1 */ | |
537 | buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); | |
538 | if (t->enabled) { | |
539 | dev_dbg(dev, "alarm IRQ armed\n"); | |
540 | buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ | |
541 | } | |
542 | buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); | |
543 | ||
30e7b039 | 544 | ret = ds1307->write_block_data(client, |
fed40b73 BS |
545 | DS1339_REG_ALARM1_SECS, 9, buf); |
546 | if (ret < 0) { | |
cb49a5e9 | 547 | dev_err(dev, "can't set alarm time\n"); |
fed40b73 | 548 | return ret; |
cb49a5e9 RG |
549 | } |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
16380c15 | 554 | static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) |
cb49a5e9 RG |
555 | { |
556 | struct i2c_client *client = to_i2c_client(dev); | |
557 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
558 | int ret; | |
559 | ||
16380c15 JS |
560 | if (!test_bit(HAS_ALARM, &ds1307->flags)) |
561 | return -ENOTTY; | |
cb49a5e9 | 562 | |
16380c15 JS |
563 | ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); |
564 | if (ret < 0) | |
565 | return ret; | |
cb49a5e9 | 566 | |
16380c15 | 567 | if (enabled) |
cb49a5e9 | 568 | ret |= DS1337_BIT_A1IE; |
16380c15 JS |
569 | else |
570 | ret &= ~DS1337_BIT_A1IE; | |
cb49a5e9 | 571 | |
16380c15 JS |
572 | ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret); |
573 | if (ret < 0) | |
574 | return ret; | |
cb49a5e9 RG |
575 | |
576 | return 0; | |
577 | } | |
578 | ||
ff8371ac | 579 | static const struct rtc_class_ops ds13xx_rtc_ops = { |
1abb0dc9 DB |
580 | .read_time = ds1307_get_time, |
581 | .set_time = ds1307_set_time, | |
74d88eb2 JR |
582 | .read_alarm = ds1337_read_alarm, |
583 | .set_alarm = ds1337_set_alarm, | |
16380c15 | 584 | .alarm_irq_enable = ds1307_alarm_irq_enable, |
1abb0dc9 DB |
585 | }; |
586 | ||
682d73f6 DB |
587 | /*----------------------------------------------------------------------*/ |
588 | ||
1d1945d2 | 589 | /* |
f4199f85 | 590 | * Alarm support for mcp794xx devices. |
1d1945d2 SG |
591 | */ |
592 | ||
f4199f85 TN |
593 | #define MCP794XX_REG_CONTROL 0x07 |
594 | # define MCP794XX_BIT_ALM0_EN 0x10 | |
595 | # define MCP794XX_BIT_ALM1_EN 0x20 | |
596 | #define MCP794XX_REG_ALARM0_BASE 0x0a | |
597 | #define MCP794XX_REG_ALARM0_CTRL 0x0d | |
598 | #define MCP794XX_REG_ALARM1_BASE 0x11 | |
599 | #define MCP794XX_REG_ALARM1_CTRL 0x14 | |
600 | # define MCP794XX_BIT_ALMX_IF (1 << 3) | |
601 | # define MCP794XX_BIT_ALMX_C0 (1 << 4) | |
602 | # define MCP794XX_BIT_ALMX_C1 (1 << 5) | |
603 | # define MCP794XX_BIT_ALMX_C2 (1 << 6) | |
604 | # define MCP794XX_BIT_ALMX_POL (1 << 7) | |
605 | # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ | |
606 | MCP794XX_BIT_ALMX_C1 | \ | |
607 | MCP794XX_BIT_ALMX_C2) | |
608 | ||
2fb07a10 | 609 | static irqreturn_t mcp794xx_irq(int irq, void *dev_id) |
1d1945d2 | 610 | { |
2fb07a10 FB |
611 | struct i2c_client *client = dev_id; |
612 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
613 | struct mutex *lock = &ds1307->rtc->ops_lock; | |
1d1945d2 SG |
614 | int reg, ret; |
615 | ||
2fb07a10 | 616 | mutex_lock(lock); |
1d1945d2 SG |
617 | |
618 | /* Check and clear alarm 0 interrupt flag. */ | |
f4199f85 | 619 | reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL); |
1d1945d2 SG |
620 | if (reg < 0) |
621 | goto out; | |
f4199f85 | 622 | if (!(reg & MCP794XX_BIT_ALMX_IF)) |
1d1945d2 | 623 | goto out; |
f4199f85 TN |
624 | reg &= ~MCP794XX_BIT_ALMX_IF; |
625 | ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg); | |
1d1945d2 SG |
626 | if (ret < 0) |
627 | goto out; | |
628 | ||
629 | /* Disable alarm 0. */ | |
f4199f85 | 630 | reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL); |
1d1945d2 SG |
631 | if (reg < 0) |
632 | goto out; | |
f4199f85 TN |
633 | reg &= ~MCP794XX_BIT_ALM0_EN; |
634 | ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg); | |
1d1945d2 SG |
635 | if (ret < 0) |
636 | goto out; | |
637 | ||
638 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); | |
639 | ||
640 | out: | |
2fb07a10 FB |
641 | mutex_unlock(lock); |
642 | ||
643 | return IRQ_HANDLED; | |
1d1945d2 SG |
644 | } |
645 | ||
f4199f85 | 646 | static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
1d1945d2 SG |
647 | { |
648 | struct i2c_client *client = to_i2c_client(dev); | |
649 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
650 | u8 *regs = ds1307->regs; | |
651 | int ret; | |
652 | ||
653 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
654 | return -EINVAL; | |
655 | ||
656 | /* Read control and alarm 0 registers. */ | |
f4199f85 | 657 | ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs); |
1d1945d2 SG |
658 | if (ret < 0) |
659 | return ret; | |
660 | ||
f4199f85 | 661 | t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); |
1d1945d2 SG |
662 | |
663 | /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ | |
664 | t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f); | |
665 | t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f); | |
666 | t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f); | |
667 | t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1; | |
668 | t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f); | |
669 | t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1; | |
670 | t->time.tm_year = -1; | |
671 | t->time.tm_yday = -1; | |
672 | t->time.tm_isdst = -1; | |
673 | ||
674 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " | |
675 | "enabled=%d polarity=%d irq=%d match=%d\n", __func__, | |
676 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
677 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, | |
f4199f85 TN |
678 | !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL), |
679 | !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF), | |
680 | (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); | |
1d1945d2 SG |
681 | |
682 | return 0; | |
683 | } | |
684 | ||
f4199f85 | 685 | static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
1d1945d2 SG |
686 | { |
687 | struct i2c_client *client = to_i2c_client(dev); | |
688 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
689 | unsigned char *regs = ds1307->regs; | |
690 | int ret; | |
691 | ||
692 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
693 | return -EINVAL; | |
694 | ||
695 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " | |
696 | "enabled=%d pending=%d\n", __func__, | |
697 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
698 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, | |
699 | t->enabled, t->pending); | |
700 | ||
701 | /* Read control and alarm 0 registers. */ | |
f4199f85 | 702 | ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs); |
1d1945d2 SG |
703 | if (ret < 0) |
704 | return ret; | |
705 | ||
706 | /* Set alarm 0, using 24-hour and day-of-month modes. */ | |
707 | regs[3] = bin2bcd(t->time.tm_sec); | |
708 | regs[4] = bin2bcd(t->time.tm_min); | |
709 | regs[5] = bin2bcd(t->time.tm_hour); | |
62c8c20a | 710 | regs[6] = bin2bcd(t->time.tm_wday + 1); |
1d1945d2 | 711 | regs[7] = bin2bcd(t->time.tm_mday); |
62c8c20a | 712 | regs[8] = bin2bcd(t->time.tm_mon + 1); |
1d1945d2 SG |
713 | |
714 | /* Clear the alarm 0 interrupt flag. */ | |
f4199f85 | 715 | regs[6] &= ~MCP794XX_BIT_ALMX_IF; |
1d1945d2 | 716 | /* Set alarm match: second, minute, hour, day, date, month. */ |
f4199f85 | 717 | regs[6] |= MCP794XX_MSK_ALMX_MATCH; |
e3edd671 NM |
718 | /* Disable interrupt. We will not enable until completely programmed */ |
719 | regs[0] &= ~MCP794XX_BIT_ALM0_EN; | |
1d1945d2 | 720 | |
f4199f85 | 721 | ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs); |
1d1945d2 SG |
722 | if (ret < 0) |
723 | return ret; | |
724 | ||
e3edd671 NM |
725 | if (!t->enabled) |
726 | return 0; | |
727 | regs[0] |= MCP794XX_BIT_ALM0_EN; | |
728 | return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, regs[0]); | |
1d1945d2 SG |
729 | } |
730 | ||
f4199f85 | 731 | static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) |
1d1945d2 SG |
732 | { |
733 | struct i2c_client *client = to_i2c_client(dev); | |
734 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
735 | int reg; | |
736 | ||
737 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
738 | return -EINVAL; | |
739 | ||
f4199f85 | 740 | reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL); |
1d1945d2 SG |
741 | if (reg < 0) |
742 | return reg; | |
743 | ||
744 | if (enabled) | |
f4199f85 | 745 | reg |= MCP794XX_BIT_ALM0_EN; |
1d1945d2 | 746 | else |
f4199f85 | 747 | reg &= ~MCP794XX_BIT_ALM0_EN; |
1d1945d2 | 748 | |
f4199f85 | 749 | return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg); |
1d1945d2 SG |
750 | } |
751 | ||
f4199f85 | 752 | static const struct rtc_class_ops mcp794xx_rtc_ops = { |
1d1945d2 SG |
753 | .read_time = ds1307_get_time, |
754 | .set_time = ds1307_set_time, | |
f4199f85 TN |
755 | .read_alarm = mcp794xx_read_alarm, |
756 | .set_alarm = mcp794xx_set_alarm, | |
757 | .alarm_irq_enable = mcp794xx_alarm_irq_enable, | |
1d1945d2 SG |
758 | }; |
759 | ||
760 | /*----------------------------------------------------------------------*/ | |
761 | ||
682d73f6 | 762 | static ssize_t |
2c3c8bea CW |
763 | ds1307_nvram_read(struct file *filp, struct kobject *kobj, |
764 | struct bin_attribute *attr, | |
682d73f6 DB |
765 | char *buf, loff_t off, size_t count) |
766 | { | |
767 | struct i2c_client *client; | |
768 | struct ds1307 *ds1307; | |
682d73f6 DB |
769 | int result; |
770 | ||
fcd8db00 | 771 | client = kobj_to_i2c_client(kobj); |
682d73f6 DB |
772 | ds1307 = i2c_get_clientdata(client); |
773 | ||
9eab0a78 AB |
774 | result = ds1307->read_block_data(client, ds1307->nvram_offset + off, |
775 | count, buf); | |
fed40b73 | 776 | if (result < 0) |
682d73f6 | 777 | dev_err(&client->dev, "%s error %d\n", "nvram read", result); |
fed40b73 | 778 | return result; |
682d73f6 DB |
779 | } |
780 | ||
781 | static ssize_t | |
2c3c8bea CW |
782 | ds1307_nvram_write(struct file *filp, struct kobject *kobj, |
783 | struct bin_attribute *attr, | |
682d73f6 DB |
784 | char *buf, loff_t off, size_t count) |
785 | { | |
786 | struct i2c_client *client; | |
30e7b039 | 787 | struct ds1307 *ds1307; |
fed40b73 | 788 | int result; |
682d73f6 | 789 | |
fcd8db00 | 790 | client = kobj_to_i2c_client(kobj); |
30e7b039 | 791 | ds1307 = i2c_get_clientdata(client); |
682d73f6 | 792 | |
9eab0a78 AB |
793 | result = ds1307->write_block_data(client, ds1307->nvram_offset + off, |
794 | count, buf); | |
fed40b73 BS |
795 | if (result < 0) { |
796 | dev_err(&client->dev, "%s error %d\n", "nvram write", result); | |
797 | return result; | |
798 | } | |
799 | return count; | |
682d73f6 DB |
800 | } |
801 | ||
33b04b7b | 802 | |
682d73f6 DB |
803 | /*----------------------------------------------------------------------*/ |
804 | ||
33b04b7b MV |
805 | static u8 do_trickle_setup_ds1339(struct i2c_client *client, |
806 | uint32_t ohms, bool diode) | |
807 | { | |
808 | u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : | |
809 | DS1307_TRICKLE_CHARGER_NO_DIODE; | |
810 | ||
811 | switch (ohms) { | |
812 | case 250: | |
813 | setup |= DS1307_TRICKLE_CHARGER_250_OHM; | |
814 | break; | |
815 | case 2000: | |
816 | setup |= DS1307_TRICKLE_CHARGER_2K_OHM; | |
817 | break; | |
818 | case 4000: | |
819 | setup |= DS1307_TRICKLE_CHARGER_4K_OHM; | |
820 | break; | |
821 | default: | |
822 | dev_warn(&client->dev, | |
823 | "Unsupported ohm value %u in dt\n", ohms); | |
824 | return 0; | |
825 | } | |
826 | return setup; | |
827 | } | |
828 | ||
829 | static void ds1307_trickle_of_init(struct i2c_client *client, | |
830 | struct chip_desc *chip) | |
831 | { | |
832 | uint32_t ohms = 0; | |
833 | bool diode = true; | |
834 | ||
835 | if (!chip->do_trickle_setup) | |
836 | goto out; | |
837 | if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms)) | |
838 | goto out; | |
839 | if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable")) | |
840 | diode = false; | |
841 | chip->trickle_charger_setup = chip->do_trickle_setup(client, | |
842 | ohms, diode); | |
843 | out: | |
844 | return; | |
845 | } | |
846 | ||
445c0207 AM |
847 | /*----------------------------------------------------------------------*/ |
848 | ||
849 | #ifdef CONFIG_RTC_DRV_DS1307_HWMON | |
850 | ||
851 | /* | |
852 | * Temperature sensor support for ds3231 devices. | |
853 | */ | |
854 | ||
855 | #define DS3231_REG_TEMPERATURE 0x11 | |
856 | ||
857 | /* | |
858 | * A user-initiated temperature conversion is not started by this function, | |
859 | * so the temperature is updated once every 64 seconds. | |
860 | */ | |
861 | static int ds3231_hwmon_read_temp(struct device *dev, s16 *mC) | |
862 | { | |
863 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
864 | u8 temp_buf[2]; | |
865 | s16 temp; | |
866 | int ret; | |
867 | ||
868 | ret = ds1307->read_block_data(ds1307->client, DS3231_REG_TEMPERATURE, | |
869 | sizeof(temp_buf), temp_buf); | |
870 | if (ret < 0) | |
871 | return ret; | |
872 | if (ret != sizeof(temp_buf)) | |
873 | return -EIO; | |
874 | ||
875 | /* | |
876 | * Temperature is represented as a 10-bit code with a resolution of | |
877 | * 0.25 degree celsius and encoded in two's complement format. | |
878 | */ | |
879 | temp = (temp_buf[0] << 8) | temp_buf[1]; | |
880 | temp >>= 6; | |
881 | *mC = temp * 250; | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
886 | static ssize_t ds3231_hwmon_show_temp(struct device *dev, | |
887 | struct device_attribute *attr, char *buf) | |
888 | { | |
889 | int ret; | |
890 | s16 temp; | |
891 | ||
892 | ret = ds3231_hwmon_read_temp(dev, &temp); | |
893 | if (ret) | |
894 | return ret; | |
895 | ||
896 | return sprintf(buf, "%d\n", temp); | |
897 | } | |
898 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, ds3231_hwmon_show_temp, | |
899 | NULL, 0); | |
900 | ||
901 | static struct attribute *ds3231_hwmon_attrs[] = { | |
902 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
903 | NULL, | |
904 | }; | |
905 | ATTRIBUTE_GROUPS(ds3231_hwmon); | |
906 | ||
907 | static void ds1307_hwmon_register(struct ds1307 *ds1307) | |
908 | { | |
909 | struct device *dev; | |
910 | ||
911 | if (ds1307->type != ds_3231) | |
912 | return; | |
913 | ||
914 | dev = devm_hwmon_device_register_with_groups(&ds1307->client->dev, | |
915 | ds1307->client->name, | |
916 | ds1307, ds3231_hwmon_groups); | |
917 | if (IS_ERR(dev)) { | |
918 | dev_warn(&ds1307->client->dev, | |
919 | "unable to register hwmon device %ld\n", PTR_ERR(dev)); | |
920 | } | |
921 | } | |
922 | ||
923 | #else | |
924 | ||
925 | static void ds1307_hwmon_register(struct ds1307 *ds1307) | |
926 | { | |
927 | } | |
928 | ||
929 | #endif | |
930 | ||
5a167f45 GKH |
931 | static int ds1307_probe(struct i2c_client *client, |
932 | const struct i2c_device_id *id) | |
1abb0dc9 DB |
933 | { |
934 | struct ds1307 *ds1307; | |
935 | int err = -ENODEV; | |
1abb0dc9 | 936 | int tmp; |
33b04b7b | 937 | struct chip_desc *chip = &chips[id->driver_data]; |
c065f35c | 938 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
c8b18da7 | 939 | bool want_irq = false; |
8bc2a407 | 940 | bool ds1307_can_wakeup_device = false; |
fed40b73 | 941 | unsigned char *buf; |
01ce893d | 942 | struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); |
2fb07a10 FB |
943 | irq_handler_t irq_handler = ds1307_irq; |
944 | ||
97f902b7 WS |
945 | static const int bbsqi_bitpos[] = { |
946 | [ds_1337] = 0, | |
947 | [ds_1339] = DS1339_BIT_BBSQI, | |
948 | [ds_3231] = DS3231_BIT_BBSQW, | |
949 | }; | |
1d1945d2 | 950 | const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops; |
1abb0dc9 | 951 | |
30e7b039 ES |
952 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA) |
953 | && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) | |
c065f35c DB |
954 | return -EIO; |
955 | ||
edca66d2 | 956 | ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); |
40ce972d | 957 | if (!ds1307) |
c065f35c | 958 | return -ENOMEM; |
045e0e85 | 959 | |
1abb0dc9 | 960 | i2c_set_clientdata(client, ds1307); |
33df2ee1 JT |
961 | |
962 | ds1307->client = client; | |
963 | ds1307->type = id->driver_data; | |
33df2ee1 | 964 | |
33b04b7b MV |
965 | if (!pdata && client->dev.of_node) |
966 | ds1307_trickle_of_init(client, chip); | |
967 | else if (pdata && pdata->trickle_charger_setup) | |
968 | chip->trickle_charger_setup = pdata->trickle_charger_setup; | |
969 | ||
970 | if (chip->trickle_charger_setup && chip->trickle_charger_reg) { | |
971 | dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n", | |
972 | DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup, | |
973 | chip->trickle_charger_reg); | |
eb86c306 | 974 | i2c_smbus_write_byte_data(client, chip->trickle_charger_reg, |
33b04b7b MV |
975 | DS13XX_TRICKLE_CHARGER_MAGIC | |
976 | chip->trickle_charger_setup); | |
977 | } | |
eb86c306 | 978 | |
fed40b73 | 979 | buf = ds1307->regs; |
30e7b039 | 980 | if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) { |
bc48b902 BA |
981 | ds1307->read_block_data = ds1307_native_smbus_read_block_data; |
982 | ds1307->write_block_data = ds1307_native_smbus_write_block_data; | |
30e7b039 ES |
983 | } else { |
984 | ds1307->read_block_data = ds1307_read_block_data; | |
985 | ds1307->write_block_data = ds1307_write_block_data; | |
986 | } | |
045e0e85 | 987 | |
8bc2a407 ML |
988 | #ifdef CONFIG_OF |
989 | /* | |
990 | * For devices with no IRQ directly connected to the SoC, the RTC chip | |
991 | * can be forced as a wakeup source by stating that explicitly in | |
992 | * the device's .dts file using the "wakeup-source" boolean property. | |
993 | * If the "wakeup-source" property is set, don't request an IRQ. | |
994 | * This will guarantee the 'wakealarm' sysfs entry is available on the device, | |
995 | * if supported by the RTC. | |
996 | */ | |
997 | if (of_property_read_bool(client->dev.of_node, "wakeup-source")) { | |
998 | ds1307_can_wakeup_device = true; | |
999 | } | |
1000 | #endif | |
1001 | ||
045e0e85 DB |
1002 | switch (ds1307->type) { |
1003 | case ds_1337: | |
1004 | case ds_1339: | |
97f902b7 | 1005 | case ds_3231: |
be5f59f4 | 1006 | /* get registers that the "rtc" read below won't read... */ |
30e7b039 | 1007 | tmp = ds1307->read_block_data(ds1307->client, |
fed40b73 | 1008 | DS1337_REG_CONTROL, 2, buf); |
1abb0dc9 | 1009 | if (tmp != 2) { |
6df80e21 | 1010 | dev_dbg(&client->dev, "read error %d\n", tmp); |
1abb0dc9 | 1011 | err = -EIO; |
edca66d2 | 1012 | goto exit; |
1abb0dc9 DB |
1013 | } |
1014 | ||
be5f59f4 RG |
1015 | /* oscillator off? turn it on, so clock can tick. */ |
1016 | if (ds1307->regs[0] & DS1337_BIT_nEOSC) | |
cb49a5e9 RG |
1017 | ds1307->regs[0] &= ~DS1337_BIT_nEOSC; |
1018 | ||
40ce972d | 1019 | /* |
8bc2a407 ML |
1020 | * Using IRQ or defined as wakeup-source? |
1021 | * Disable the square wave and both alarms. | |
97f902b7 WS |
1022 | * For some variants, be sure alarms can trigger when we're |
1023 | * running on Vbackup (BBSQI/BBSQW) | |
cb49a5e9 | 1024 | */ |
8bc2a407 ML |
1025 | if (chip->alarm && (ds1307->client->irq > 0 || |
1026 | ds1307_can_wakeup_device)) { | |
97f902b7 WS |
1027 | ds1307->regs[0] |= DS1337_BIT_INTCN |
1028 | | bbsqi_bitpos[ds1307->type]; | |
cb49a5e9 | 1029 | ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); |
b24a7267 WS |
1030 | |
1031 | want_irq = true; | |
cb49a5e9 RG |
1032 | } |
1033 | ||
1034 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, | |
1035 | ds1307->regs[0]); | |
be5f59f4 RG |
1036 | |
1037 | /* oscillator fault? clear flag, and warn */ | |
1038 | if (ds1307->regs[1] & DS1337_BIT_OSF) { | |
1039 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, | |
1040 | ds1307->regs[1] & ~DS1337_BIT_OSF); | |
1041 | dev_warn(&client->dev, "SET TIME!\n"); | |
1abb0dc9 | 1042 | } |
045e0e85 | 1043 | break; |
a2166858 MF |
1044 | |
1045 | case rx_8025: | |
1046 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
1047 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
1048 | if (tmp != 2) { | |
6df80e21 | 1049 | dev_dbg(&client->dev, "read error %d\n", tmp); |
a2166858 | 1050 | err = -EIO; |
edca66d2 | 1051 | goto exit; |
a2166858 MF |
1052 | } |
1053 | ||
1054 | /* oscillator off? turn it on, so clock can tick. */ | |
1055 | if (!(ds1307->regs[1] & RX8025_BIT_XST)) { | |
1056 | ds1307->regs[1] |= RX8025_BIT_XST; | |
1057 | i2c_smbus_write_byte_data(client, | |
1058 | RX8025_REG_CTRL2 << 4 | 0x08, | |
1059 | ds1307->regs[1]); | |
1060 | dev_warn(&client->dev, | |
1061 | "oscillator stop detected - SET TIME!\n"); | |
1062 | } | |
1063 | ||
1064 | if (ds1307->regs[1] & RX8025_BIT_PON) { | |
1065 | ds1307->regs[1] &= ~RX8025_BIT_PON; | |
1066 | i2c_smbus_write_byte_data(client, | |
1067 | RX8025_REG_CTRL2 << 4 | 0x08, | |
1068 | ds1307->regs[1]); | |
1069 | dev_warn(&client->dev, "power-on detected\n"); | |
1070 | } | |
1071 | ||
1072 | if (ds1307->regs[1] & RX8025_BIT_VDET) { | |
1073 | ds1307->regs[1] &= ~RX8025_BIT_VDET; | |
1074 | i2c_smbus_write_byte_data(client, | |
1075 | RX8025_REG_CTRL2 << 4 | 0x08, | |
1076 | ds1307->regs[1]); | |
1077 | dev_warn(&client->dev, "voltage drop detected\n"); | |
1078 | } | |
1079 | ||
1080 | /* make sure we are running in 24hour mode */ | |
1081 | if (!(ds1307->regs[0] & RX8025_BIT_2412)) { | |
1082 | u8 hour; | |
1083 | ||
1084 | /* switch to 24 hour mode */ | |
1085 | i2c_smbus_write_byte_data(client, | |
1086 | RX8025_REG_CTRL1 << 4 | 0x08, | |
1087 | ds1307->regs[0] | | |
1088 | RX8025_BIT_2412); | |
1089 | ||
1090 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
1091 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
1092 | if (tmp != 2) { | |
6df80e21 | 1093 | dev_dbg(&client->dev, "read error %d\n", tmp); |
a2166858 | 1094 | err = -EIO; |
edca66d2 | 1095 | goto exit; |
a2166858 MF |
1096 | } |
1097 | ||
1098 | /* correct hour */ | |
1099 | hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]); | |
1100 | if (hour == 12) | |
1101 | hour = 0; | |
1102 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
1103 | hour += 12; | |
1104 | ||
1105 | i2c_smbus_write_byte_data(client, | |
1106 | DS1307_REG_HOUR << 4 | 0x08, | |
1107 | hour); | |
1108 | } | |
1109 | break; | |
33df2ee1 JT |
1110 | case ds_1388: |
1111 | ds1307->offset = 1; /* Seconds starts at 1 */ | |
1112 | break; | |
f4199f85 TN |
1113 | case mcp794xx: |
1114 | rtc_ops = &mcp794xx_rtc_ops; | |
1d1945d2 | 1115 | if (ds1307->client->irq > 0 && chip->alarm) { |
2fb07a10 | 1116 | irq_handler = mcp794xx_irq; |
1d1945d2 SG |
1117 | want_irq = true; |
1118 | } | |
1119 | break; | |
045e0e85 DB |
1120 | default: |
1121 | break; | |
1122 | } | |
1abb0dc9 DB |
1123 | |
1124 | read_rtc: | |
1125 | /* read RTC registers */ | |
96fc3a45 | 1126 | tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf); |
fed40b73 | 1127 | if (tmp != 8) { |
6df80e21 | 1128 | dev_dbg(&client->dev, "read error %d\n", tmp); |
1abb0dc9 | 1129 | err = -EIO; |
edca66d2 | 1130 | goto exit; |
1abb0dc9 DB |
1131 | } |
1132 | ||
40ce972d DA |
1133 | /* |
1134 | * minimal sanity checking; some chips (like DS1340) don't | |
1abb0dc9 DB |
1135 | * specify the extra bits as must-be-zero, but there are |
1136 | * still a few values that are clearly out-of-range. | |
1137 | */ | |
1138 | tmp = ds1307->regs[DS1307_REG_SECS]; | |
045e0e85 DB |
1139 | switch (ds1307->type) { |
1140 | case ds_1307: | |
045e0e85 | 1141 | case m41t00: |
be5f59f4 | 1142 | /* clock halted? turn it on, so clock can tick. */ |
045e0e85 | 1143 | if (tmp & DS1307_BIT_CH) { |
be5f59f4 RG |
1144 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
1145 | dev_warn(&client->dev, "SET TIME!\n"); | |
045e0e85 | 1146 | goto read_rtc; |
1abb0dc9 | 1147 | } |
045e0e85 | 1148 | break; |
be5f59f4 RG |
1149 | case ds_1338: |
1150 | /* clock halted? turn it on, so clock can tick. */ | |
045e0e85 | 1151 | if (tmp & DS1307_BIT_CH) |
be5f59f4 RG |
1152 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
1153 | ||
1154 | /* oscillator fault? clear flag, and warn */ | |
1155 | if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { | |
1156 | i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL, | |
bd16f9eb | 1157 | ds1307->regs[DS1307_REG_CONTROL] |
be5f59f4 RG |
1158 | & ~DS1338_BIT_OSF); |
1159 | dev_warn(&client->dev, "SET TIME!\n"); | |
1160 | goto read_rtc; | |
1161 | } | |
045e0e85 | 1162 | break; |
fcd8db00 R |
1163 | case ds_1340: |
1164 | /* clock halted? turn it on, so clock can tick. */ | |
1165 | if (tmp & DS1340_BIT_nEOSC) | |
1166 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); | |
1167 | ||
1168 | tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG); | |
1169 | if (tmp < 0) { | |
6df80e21 | 1170 | dev_dbg(&client->dev, "read error %d\n", tmp); |
fcd8db00 | 1171 | err = -EIO; |
edca66d2 | 1172 | goto exit; |
fcd8db00 R |
1173 | } |
1174 | ||
1175 | /* oscillator fault? clear flag, and warn */ | |
1176 | if (tmp & DS1340_BIT_OSF) { | |
1177 | i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0); | |
1178 | dev_warn(&client->dev, "SET TIME!\n"); | |
1179 | } | |
43fcb815 | 1180 | break; |
f4199f85 | 1181 | case mcp794xx: |
43fcb815 | 1182 | /* make sure that the backup battery is enabled */ |
f4199f85 | 1183 | if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { |
43fcb815 DA |
1184 | i2c_smbus_write_byte_data(client, DS1307_REG_WDAY, |
1185 | ds1307->regs[DS1307_REG_WDAY] | |
f4199f85 | 1186 | | MCP794XX_BIT_VBATEN); |
43fcb815 DA |
1187 | } |
1188 | ||
1189 | /* clock halted? turn it on, so clock can tick. */ | |
f4199f85 | 1190 | if (!(tmp & MCP794XX_BIT_ST)) { |
43fcb815 | 1191 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, |
f4199f85 | 1192 | MCP794XX_BIT_ST); |
43fcb815 DA |
1193 | dev_warn(&client->dev, "SET TIME!\n"); |
1194 | goto read_rtc; | |
1195 | } | |
1196 | ||
fcd8db00 | 1197 | break; |
32d322bc | 1198 | default: |
045e0e85 | 1199 | break; |
1abb0dc9 | 1200 | } |
045e0e85 | 1201 | |
1abb0dc9 | 1202 | tmp = ds1307->regs[DS1307_REG_HOUR]; |
c065f35c DB |
1203 | switch (ds1307->type) { |
1204 | case ds_1340: | |
1205 | case m41t00: | |
40ce972d DA |
1206 | /* |
1207 | * NOTE: ignores century bits; fix before deploying | |
c065f35c DB |
1208 | * systems that will run through year 2100. |
1209 | */ | |
1210 | break; | |
a2166858 MF |
1211 | case rx_8025: |
1212 | break; | |
c065f35c DB |
1213 | default: |
1214 | if (!(tmp & DS1307_BIT_12HR)) | |
1215 | break; | |
1216 | ||
40ce972d DA |
1217 | /* |
1218 | * Be sure we're in 24 hour mode. Multi-master systems | |
c065f35c DB |
1219 | * take note... |
1220 | */ | |
fe20ba70 | 1221 | tmp = bcd2bin(tmp & 0x1f); |
c065f35c DB |
1222 | if (tmp == 12) |
1223 | tmp = 0; | |
1224 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
1225 | tmp += 12; | |
1abb0dc9 | 1226 | i2c_smbus_write_byte_data(client, |
96fc3a45 | 1227 | ds1307->offset + DS1307_REG_HOUR, |
fe20ba70 | 1228 | bin2bcd(tmp)); |
1abb0dc9 DB |
1229 | } |
1230 | ||
3abb1ada SG |
1231 | if (want_irq) { |
1232 | device_set_wakeup_capable(&client->dev, true); | |
1233 | set_bit(HAS_ALARM, &ds1307->flags); | |
1234 | } | |
edca66d2 | 1235 | ds1307->rtc = devm_rtc_device_register(&client->dev, client->name, |
1d1945d2 | 1236 | rtc_ops, THIS_MODULE); |
1abb0dc9 | 1237 | if (IS_ERR(ds1307->rtc)) { |
4071ea25 | 1238 | return PTR_ERR(ds1307->rtc); |
1abb0dc9 DB |
1239 | } |
1240 | ||
8bc2a407 ML |
1241 | if (ds1307_can_wakeup_device) { |
1242 | /* Disable request for an IRQ */ | |
1243 | want_irq = false; | |
1244 | dev_info(&client->dev, "'wakeup-source' is set, request for an IRQ is disabled!\n"); | |
1245 | /* We cannot support UIE mode if we do not have an IRQ line */ | |
1246 | ds1307->rtc->uie_unsupported = 1; | |
1247 | } | |
1248 | ||
cb49a5e9 | 1249 | if (want_irq) { |
c5983191 NM |
1250 | err = devm_request_threaded_irq(&client->dev, |
1251 | client->irq, NULL, irq_handler, | |
1252 | IRQF_SHARED | IRQF_ONESHOT, | |
1253 | ds1307->rtc->name, client); | |
cb49a5e9 | 1254 | if (err) { |
4071ea25 | 1255 | client->irq = 0; |
3abb1ada SG |
1256 | device_set_wakeup_capable(&client->dev, false); |
1257 | clear_bit(HAS_ALARM, &ds1307->flags); | |
4071ea25 | 1258 | dev_err(&client->dev, "unable to request IRQ!\n"); |
3abb1ada | 1259 | } else |
51c4cfef | 1260 | dev_dbg(&client->dev, "got IRQ %d\n", client->irq); |
cb49a5e9 RG |
1261 | } |
1262 | ||
9eab0a78 | 1263 | if (chip->nvram_size) { |
4071ea25 | 1264 | |
edca66d2 JH |
1265 | ds1307->nvram = devm_kzalloc(&client->dev, |
1266 | sizeof(struct bin_attribute), | |
1267 | GFP_KERNEL); | |
9eab0a78 | 1268 | if (!ds1307->nvram) { |
4071ea25 AZ |
1269 | dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n"); |
1270 | } else { | |
1271 | ||
1272 | ds1307->nvram->attr.name = "nvram"; | |
1273 | ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR; | |
1274 | ||
1275 | sysfs_bin_attr_init(ds1307->nvram); | |
1276 | ||
1277 | ds1307->nvram->read = ds1307_nvram_read; | |
1278 | ds1307->nvram->write = ds1307_nvram_write; | |
1279 | ds1307->nvram->size = chip->nvram_size; | |
1280 | ds1307->nvram_offset = chip->nvram_offset; | |
1281 | ||
1282 | err = sysfs_create_bin_file(&client->dev.kobj, | |
1283 | ds1307->nvram); | |
1284 | if (err) { | |
1285 | dev_err(&client->dev, | |
1286 | "unable to create sysfs file: %s\n", | |
1287 | ds1307->nvram->attr.name); | |
1288 | } else { | |
1289 | set_bit(HAS_NVRAM, &ds1307->flags); | |
1290 | dev_info(&client->dev, "%zu bytes nvram\n", | |
1291 | ds1307->nvram->size); | |
1292 | } | |
9eab0a78 | 1293 | } |
682d73f6 DB |
1294 | } |
1295 | ||
445c0207 AM |
1296 | ds1307_hwmon_register(ds1307); |
1297 | ||
1abb0dc9 DB |
1298 | return 0; |
1299 | ||
edca66d2 | 1300 | exit: |
1abb0dc9 DB |
1301 | return err; |
1302 | } | |
1303 | ||
5a167f45 | 1304 | static int ds1307_remove(struct i2c_client *client) |
1abb0dc9 | 1305 | { |
40ce972d | 1306 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
cb49a5e9 | 1307 | |
edca66d2 | 1308 | if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) |
9eab0a78 | 1309 | sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram); |
682d73f6 | 1310 | |
1abb0dc9 DB |
1311 | return 0; |
1312 | } | |
1313 | ||
1314 | static struct i2c_driver ds1307_driver = { | |
1315 | .driver = { | |
c065f35c | 1316 | .name = "rtc-ds1307", |
1abb0dc9 | 1317 | }, |
c065f35c | 1318 | .probe = ds1307_probe, |
5a167f45 | 1319 | .remove = ds1307_remove, |
3760f736 | 1320 | .id_table = ds1307_id, |
1abb0dc9 DB |
1321 | }; |
1322 | ||
0abc9201 | 1323 | module_i2c_driver(ds1307_driver); |
1abb0dc9 DB |
1324 | |
1325 | MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); | |
1326 | MODULE_LICENSE("GPL"); |