[mirror_ubuntu-jammy-kernel.git] / drivers / rtc / rtc-ds1511.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * An rtc driver for the Dallas DS1511
 *
 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
 * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
 *
 * Real time clock driver for the Dallas 1511 chip, which also
 * contains a watchdog timer.  There is a tiny amount of code that
 * platform code could use to mess with the watchdog device a little
 * bit, but not a full watchdog driver.
 */

#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>

enum ds1511reg {
	DS1511_SEC = 0x0,
	DS1511_MIN = 0x1,
	DS1511_HOUR = 0x2,
	DS1511_DOW = 0x3,
	DS1511_DOM = 0x4,
	DS1511_MONTH = 0x5,
	DS1511_YEAR = 0x6,
	DS1511_CENTURY = 0x7,
	DS1511_AM1_SEC = 0x8,
	DS1511_AM2_MIN = 0x9,
	DS1511_AM3_HOUR = 0xa,
	DS1511_AM4_DATE = 0xb,
	DS1511_WD_MSEC = 0xc,
	DS1511_WD_SEC = 0xd,
	DS1511_CONTROL_A = 0xe,
	DS1511_CONTROL_B = 0xf,
	DS1511_RAMADDR_LSB = 0x10,
	DS1511_RAMDATA = 0x13
};

#define DS1511_BLF1	0x80
#define DS1511_BLF2	0x40
#define DS1511_PRS	0x20
#define DS1511_PAB	0x10
#define DS1511_TDF	0x08
#define DS1511_KSF	0x04
#define DS1511_WDF	0x02
#define DS1511_IRQF	0x01
#define DS1511_TE	0x80
#define DS1511_CS	0x40
#define DS1511_BME	0x20
#define DS1511_TPE	0x10
#define DS1511_TIE	0x08
#define DS1511_KIE	0x04
#define DS1511_WDE	0x02
#define DS1511_WDS	0x01
#define DS1511_RAM_MAX	0x100

#define RTC_CMD		DS1511_CONTROL_B
#define RTC_CMD1	DS1511_CONTROL_A

#define RTC_ALARM_SEC	DS1511_AM1_SEC
#define RTC_ALARM_MIN	DS1511_AM2_MIN
#define RTC_ALARM_HOUR	DS1511_AM3_HOUR
#define RTC_ALARM_DATE	DS1511_AM4_DATE

#define RTC_SEC		DS1511_SEC
#define RTC_MIN		DS1511_MIN
#define RTC_HOUR	DS1511_HOUR
#define RTC_DOW		DS1511_DOW
#define RTC_DOM		DS1511_DOM
#define RTC_MON		DS1511_MONTH
#define RTC_YEAR	DS1511_YEAR
#define RTC_CENTURY	DS1511_CENTURY

#define RTC_TIE	DS1511_TIE
#define RTC_TE	DS1511_TE

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;		/* virtual base address */
	int irq;
	unsigned int irqen;
	int alrm_sec;
	int alrm_min;
	int alrm_hour;
	int alrm_mday;
	spinlock_t lock;
};

static DEFINE_SPINLOCK(ds1511_lock);

static __iomem char *ds1511_base;
static u32 reg_spacing = 1;

static noinline void
rtc_write(uint8_t val, uint32_t reg)
{
	writeb(val, ds1511_base + (reg * reg_spacing));
}

static noinline uint8_t
rtc_read(enum ds1511reg reg)
{
	return readb(ds1511_base + (reg * reg_spacing));
}

static inline void
rtc_disable_update(void)
{
	rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD);
}

static void
rtc_enable_update(void)
{
	rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD);
}

/*
 * #define DS1511_WDOG_RESET_SUPPORT
 *
 * Uncomment this if you want to use these routines in
 * some platform code.
 */
#ifdef DS1511_WDOG_RESET_SUPPORT
/*
 * just enough code to set the watchdog timer so that it
 * will reboot the system
 */
void
ds1511_wdog_set(unsigned long deciseconds)
{
	/*
	 * the wdog timer can take 99.99 seconds
	 */
	deciseconds %= 10000;
	/*
	 * set the wdog values in the wdog registers
	 */
	rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC);
	rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC);
	/*
	 * set wdog enable and wdog 'steering' bit to issue a reset
	 */
	rtc_write(rtc_read(RTC_CMD) | DS1511_WDE | DS1511_WDS, RTC_CMD);
}

void
ds1511_wdog_disable(void)
{
	/*
	 * clear wdog enable and wdog 'steering' bits
	 */
	rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD);
	/*
	 * clear the wdog counter
	 */
	rtc_write(0, DS1511_WD_MSEC);
	rtc_write(0, DS1511_WD_SEC);
}
#endif

/*
 * set the rtc chip's idea of the time.
 * stupidly, some callers call with year unmolested;
 * and some call with  year = year - 1900.  thanks.
 */
static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
{
	u8 mon, day, dow, hrs, min, sec, yrs, cen;
	unsigned long flags;

	/*
	 * won't have to change this for a while
	 */
	if (rtc_tm->tm_year < 1900)
		rtc_tm->tm_year += 1900;

	if (rtc_tm->tm_year < 1970)
		return -EINVAL;

	yrs = rtc_tm->tm_year % 100;
	cen = rtc_tm->tm_year / 100;
	mon = rtc_tm->tm_mon + 1;   /* tm_mon starts at zero */
	day = rtc_tm->tm_mday;
	dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
	hrs = rtc_tm->tm_hour;
	min = rtc_tm->tm_min;
	sec = rtc_tm->tm_sec;

	if ((mon > 12) || (day == 0))
		return -EINVAL;

	if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year))
		return -EINVAL;

	if ((hrs >= 24) || (min >= 60) || (sec >= 60))
		return -EINVAL;

	/*
	 * each register is a different number of valid bits
	 */
	sec = bin2bcd(sec) & 0x7f;
	min = bin2bcd(min) & 0x7f;
	hrs = bin2bcd(hrs) & 0x3f;
	day = bin2bcd(day) & 0x3f;
	mon = bin2bcd(mon) & 0x1f;
	yrs = bin2bcd(yrs) & 0xff;
	cen = bin2bcd(cen) & 0xff;

	spin_lock_irqsave(&ds1511_lock, flags);
	rtc_disable_update();
	rtc_write(cen, RTC_CENTURY);
	rtc_write(yrs, RTC_YEAR);
	rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON);
	rtc_write(day, RTC_DOM);
	rtc_write(hrs, RTC_HOUR);
	rtc_write(min, RTC_MIN);
	rtc_write(sec, RTC_SEC);
	rtc_write(dow, RTC_DOW);
	rtc_enable_update();
	spin_unlock_irqrestore(&ds1511_lock, flags);

	return 0;
}

static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
{
	unsigned int century;
	unsigned long flags;

	spin_lock_irqsave(&ds1511_lock, flags);
	rtc_disable_update();

	rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f;
	rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f;
	rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f;
	rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f;
	rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7;
	rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f;
	rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f;
	century = rtc_read(RTC_CENTURY);

	rtc_enable_update();
	spin_unlock_irqrestore(&ds1511_lock, flags);

	rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
	rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
	rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
	rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
	rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
	rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
	rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
	century = bcd2bin(century) * 100;

	/*
	 * Account for differences between how the RTC uses the values
	 * and how they are defined in a struct rtc_time;
	 */
	century += rtc_tm->tm_year;
	rtc_tm->tm_year = century - 1900;

	rtc_tm->tm_mon--;

	return 0;
}

/*
 * write the alarm register settings
 *
 * we only have the use to interrupt every second, otherwise
 * known as the update interrupt, or the interrupt if the whole
 * date/hours/mins/secs matches.  the ds1511 has many more
 * permutations, but the kernel doesn't.
 */
static void
ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
{
	unsigned long flags;

	spin_lock_irqsave(&pdata->lock, flags);
	rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
	       0x80 : bin2bcd(pdata->alrm_mday) & 0x3f,
	       RTC_ALARM_DATE);
	rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
	       0x80 : bin2bcd(pdata->alrm_hour) & 0x3f,
	       RTC_ALARM_HOUR);
	rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
	       0x80 : bin2bcd(pdata->alrm_min) & 0x7f,
	       RTC_ALARM_MIN);
	rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
	       0x80 : bin2bcd(pdata->alrm_sec) & 0x7f,
	       RTC_ALARM_SEC);
	rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD);
	rtc_read(RTC_CMD1);	/* clear interrupts */
	spin_unlock_irqrestore(&pdata->lock, flags);
}

static int
ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (pdata->irq <= 0)
		return -EINVAL;

	pdata->alrm_mday = alrm->time.tm_mday;
	pdata->alrm_hour = alrm->time.tm_hour;
	pdata->alrm_min = alrm->time.tm_min;
	pdata->alrm_sec = alrm->time.tm_sec;
	if (alrm->enabled)
		pdata->irqen |= RTC_AF;

	ds1511_rtc_update_alarm(pdata);
	return 0;
}

static int
ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (pdata->irq <= 0)
		return -EINVAL;

	alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
	alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
	alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
	alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
	alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
	return 0;
}

static irqreturn_t
ds1511_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	unsigned long events = 0;

	spin_lock(&pdata->lock);
	/*
	 * read and clear interrupt
	 */
	if (rtc_read(RTC_CMD1) & DS1511_IRQF) {
		events = RTC_IRQF;
		if (rtc_read(RTC_ALARM_SEC) & 0x80)
			events |= RTC_UF;
		else
			events |= RTC_AF;
		rtc_update_irq(pdata->rtc, 1, events);
	}
	spin_unlock(&pdata->lock);
	return events ? IRQ_HANDLED : IRQ_NONE;
}

static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (pdata->irq <= 0)
		return -EINVAL;
	if (enabled)
		pdata->irqen |= RTC_AF;
	else
		pdata->irqen &= ~RTC_AF;
	ds1511_rtc_update_alarm(pdata);
	return 0;
}

static const struct rtc_class_ops ds1511_rtc_ops = {
	.read_time		= ds1511_rtc_read_time,
	.set_time		= ds1511_rtc_set_time,
	.read_alarm		= ds1511_rtc_read_alarm,
	.set_alarm		= ds1511_rtc_set_alarm,
	.alarm_irq_enable	= ds1511_rtc_alarm_irq_enable,
};

static int ds1511_nvram_read(void *priv, unsigned int pos, void *buf,
			     size_t size)
{
	int i;

	rtc_write(pos, DS1511_RAMADDR_LSB);
	for (i = 0; i < size; i++)
		*(char *)buf++ = rtc_read(DS1511_RAMDATA);

	return 0;
}

static int ds1511_nvram_write(void *priv, unsigned int pos, void *buf,
			      size_t size)
{
	int i;

	rtc_write(pos, DS1511_RAMADDR_LSB);
	for (i = 0; i < size; i++)
		rtc_write(*(char *)buf++, DS1511_RAMDATA);

	return 0;
}

static int ds1511_rtc_probe(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata;
	int ret = 0;
	struct nvmem_config ds1511_nvmem_cfg = {
		.name = "ds1511_nvram",
		.word_size = 1,
		.stride = 1,
		.size = DS1511_RAM_MAX,
		.reg_read = ds1511_nvram_read,
		.reg_write = ds1511_nvram_write,
		.priv = &pdev->dev,
	};

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	ds1511_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ds1511_base))
		return PTR_ERR(ds1511_base);
	pdata->ioaddr = ds1511_base;
	pdata->irq = platform_get_irq(pdev, 0);

	/*
	 * turn on the clock and the crystal, etc.
	 */
	rtc_write(DS1511_BME, RTC_CMD);
	rtc_write(0, RTC_CMD1);
	/*
	 * clear the wdog counter
	 */
	rtc_write(0, DS1511_WD_MSEC);
	rtc_write(0, DS1511_WD_SEC);
	/*
	 * start the clock
	 */
	rtc_enable_update();

	/*
	 * check for a dying bat-tree
	 */
	if (rtc_read(RTC_CMD1) & DS1511_BLF1)
		dev_warn(&pdev->dev, "voltage-low detected.\n");

	spin_lock_init(&pdata->lock);
	platform_set_drvdata(pdev, pdata);

	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(pdata->rtc))
		return PTR_ERR(pdata->rtc);

	pdata->rtc->ops = &ds1511_rtc_ops;

	ret = devm_rtc_register_device(pdata->rtc);
	if (ret)
		return ret;

	devm_rtc_nvmem_register(pdata->rtc, &ds1511_nvmem_cfg);

	/*
	 * if the platform has an interrupt in mind for this device,
	 * then by all means, set it
	 */
	if (pdata->irq > 0) {
		rtc_read(RTC_CMD1);
		if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt,
			IRQF_SHARED, pdev->name, pdev) < 0) {

			dev_warn(&pdev->dev, "interrupt not available.\n");
			pdata->irq = 0;
		}
	}

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:ds1511");

static struct platform_driver ds1511_rtc_driver = {
	.probe		= ds1511_rtc_probe,
	.driver		= {
		.name	= "ds1511",
	},
};

module_platform_driver(ds1511_rtc_driver);

MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
8f26795a AS	2	/*
	3	* An rtc driver for the Dallas DS1511
	4	*
	5	* Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
5b73a41c	6	* Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
8f26795a	7	*
8f26795a AS	8	* Real time clock driver for the Dallas 1511 chip, which also
	9	* contains a watchdog timer. There is a tiny amount of code that
	10	* platform code could use to mess with the watchdog device a little
	11	* bit, but not a full watchdog driver.
	12	*/
	13
	14	#include <linux/bcd.h>
	15	#include <linux/init.h>
	16	#include <linux/kernel.h>
5a0e3ad6	17	#include <linux/gfp.h>
8f26795a AS	18	#include <linux/delay.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/rtc.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
2113852b	23	#include <linux/module.h>
8f26795a	24
8f26795a AS	25	enum ds1511reg {
	26	DS1511_SEC = 0x0,
	27	DS1511_MIN = 0x1,
	28	DS1511_HOUR = 0x2,
	29	DS1511_DOW = 0x3,
	30	DS1511_DOM = 0x4,
	31	DS1511_MONTH = 0x5,
	32	DS1511_YEAR = 0x6,
	33	DS1511_CENTURY = 0x7,
	34	DS1511_AM1_SEC = 0x8,
	35	DS1511_AM2_MIN = 0x9,
	36	DS1511_AM3_HOUR = 0xa,
	37	DS1511_AM4_DATE = 0xb,
	38	DS1511_WD_MSEC = 0xc,
	39	DS1511_WD_SEC = 0xd,
	40	DS1511_CONTROL_A = 0xe,
	41	DS1511_CONTROL_B = 0xf,
	42	DS1511_RAMADDR_LSB = 0x10,
	43	DS1511_RAMDATA = 0x13
	44	};
	45
	46	#define DS1511_BLF1 0x80
	47	#define DS1511_BLF2 0x40
	48	#define DS1511_PRS 0x20
	49	#define DS1511_PAB 0x10
	50	#define DS1511_TDF 0x08
	51	#define DS1511_KSF 0x04
	52	#define DS1511_WDF 0x02
	53	#define DS1511_IRQF 0x01
	54	#define DS1511_TE 0x80
	55	#define DS1511_CS 0x40
	56	#define DS1511_BME 0x20
	57	#define DS1511_TPE 0x10
	58	#define DS1511_TIE 0x08
	59	#define DS1511_KIE 0x04
	60	#define DS1511_WDE 0x02
	61	#define DS1511_WDS 0x01
8ccba142	62	#define DS1511_RAM_MAX 0x100
8f26795a AS	63
	64	#define RTC_CMD DS1511_CONTROL_B
	65	#define RTC_CMD1 DS1511_CONTROL_A
	66
	67	#define RTC_ALARM_SEC DS1511_AM1_SEC
	68	#define RTC_ALARM_MIN DS1511_AM2_MIN
	69	#define RTC_ALARM_HOUR DS1511_AM3_HOUR
	70	#define RTC_ALARM_DATE DS1511_AM4_DATE
	71
	72	#define RTC_SEC DS1511_SEC
	73	#define RTC_MIN DS1511_MIN
	74	#define RTC_HOUR DS1511_HOUR
	75	#define RTC_DOW DS1511_DOW
	76	#define RTC_DOM DS1511_DOM
	77	#define RTC_MON DS1511_MONTH
	78	#define RTC_YEAR DS1511_YEAR
	79	#define RTC_CENTURY DS1511_CENTURY
	80
	81	#define RTC_TIE DS1511_TIE
	82	#define RTC_TE DS1511_TE
	83
	84	struct rtc_plat_data {
	85	struct rtc_device *rtc;
	86	void __iomem ioaddr; / virtual base address */
8f26795a AS	87	int irq;
	88	unsigned int irqen;
	89	int alrm_sec;
	90	int alrm_min;
	91	int alrm_hour;
	92	int alrm_mday;
ba4f3e47	93	spinlock_t lock;
8f26795a AS	94	};
	95
	96	static DEFINE_SPINLOCK(ds1511_lock);
	97
	98	static __iomem char *ds1511_base;
	99	static u32 reg_spacing = 1;
	100
7b2f0053	101	static noinline void
8f26795a AS	102	rtc_write(uint8_t val, uint32_t reg)
	103	{
	104	writeb(val, ds1511_base + (reg * reg_spacing));
	105	}
	106
7b2f0053	107	static noinline uint8_t
8f26795a AS	108	rtc_read(enum ds1511reg reg)
	109	{
	110	return readb(ds1511_base + (reg * reg_spacing));
	111	}
	112
7b2f0053	113	static inline void
8f26795a AS	114	rtc_disable_update(void)
	115	{
	116	rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD);
	117	}
	118
7b2f0053	119	static void
8f26795a AS	120	rtc_enable_update(void)
	121	{
	122	rtc_write((rtc_read(RTC_CMD) \| RTC_TE), RTC_CMD);
	123	}
	124
	125	/*
	126	* #define DS1511_WDOG_RESET_SUPPORT
	127	*
	128	* Uncomment this if you want to use these routines in
	129	* some platform code.
	130	*/
	131	#ifdef DS1511_WDOG_RESET_SUPPORT
	132	/*
	133	* just enough code to set the watchdog timer so that it
	134	* will reboot the system
	135	*/
7b2f0053	136	void
8f26795a AS	137	ds1511_wdog_set(unsigned long deciseconds)
	138	{
	139	/*
	140	* the wdog timer can take 99.99 seconds
	141	*/
	142	deciseconds %= 10000;
	143	/*
	144	* set the wdog values in the wdog registers
	145	*/
fe20ba70 AB	146	rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC);
fe20ba70 AB	147	rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC);
8f26795a AS	148	/*
	149	* set wdog enable and wdog 'steering' bit to issue a reset
	150	*/
8ccba142	151	rtc_write(rtc_read(RTC_CMD) \| DS1511_WDE \| DS1511_WDS, RTC_CMD);
8f26795a AS	152	}
8f26795a AS	153
7b2f0053	154	void
8f26795a AS	155	ds1511_wdog_disable(void)
	156	{
	157	/*
	158	* clear wdog enable and wdog 'steering' bits
	159	*/
	160	rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE \| DS1511_WDS), RTC_CMD);
	161	/*
	162	* clear the wdog counter
	163	*/
	164	rtc_write(0, DS1511_WD_MSEC);
	165	rtc_write(0, DS1511_WD_SEC);
	166	}
	167	#endif
	168
	169	/*
	170	* set the rtc chip's idea of the time.
	171	* stupidly, some callers call with year unmolested;
	172	* and some call with year = year - 1900. thanks.
	173	*/
a3ed107e	174	static int ds1511_rtc_set_time(struct device dev, struct rtc_time rtc_tm)
8f26795a AS	175	{
8f26795a AS	176	u8 mon, day, dow, hrs, min, sec, yrs, cen;
9a0f4aea	177	unsigned long flags;
8f26795a AS	178
	179	/*
	180	* won't have to change this for a while
	181	*/
7b2f0053	182	if (rtc_tm->tm_year < 1900)
8f26795a	183	rtc_tm->tm_year += 1900;
8f26795a	184
7b2f0053	185	if (rtc_tm->tm_year < 1970)
8f26795a	186	return -EINVAL;
7b2f0053	187
8f26795a AS	188	yrs = rtc_tm->tm_year % 100;
	189	cen = rtc_tm->tm_year / 100;
	190	mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */
	191	day = rtc_tm->tm_mday;
	192	dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
	193	hrs = rtc_tm->tm_hour;
	194	min = rtc_tm->tm_min;
	195	sec = rtc_tm->tm_sec;
	196
7b2f0053	197	if ((mon > 12) \|\| (day == 0))
8f26795a	198	return -EINVAL;
8f26795a	199
7b2f0053	200	if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year))
8f26795a	201	return -EINVAL;
8f26795a	202
7b2f0053	203	if ((hrs >= 24) \|\| (min >= 60) \|\| (sec >= 60))
8f26795a	204	return -EINVAL;
8f26795a AS	205
	206	/*
	207	* each register is a different number of valid bits
	208	*/
fe20ba70 AB	209	sec = bin2bcd(sec) & 0x7f;
	210	min = bin2bcd(min) & 0x7f;
	211	hrs = bin2bcd(hrs) & 0x3f;
	212	day = bin2bcd(day) & 0x3f;
	213	mon = bin2bcd(mon) & 0x1f;
	214	yrs = bin2bcd(yrs) & 0xff;
	215	cen = bin2bcd(cen) & 0xff;
8f26795a AS	216
	217	spin_lock_irqsave(&ds1511_lock, flags);
	218	rtc_disable_update();
	219	rtc_write(cen, RTC_CENTURY);
	220	rtc_write(yrs, RTC_YEAR);
	221	rtc_write((rtc_read(RTC_MON) & 0xe0) \| mon, RTC_MON);
	222	rtc_write(day, RTC_DOM);
	223	rtc_write(hrs, RTC_HOUR);
	224	rtc_write(min, RTC_MIN);
	225	rtc_write(sec, RTC_SEC);
	226	rtc_write(dow, RTC_DOW);
	227	rtc_enable_update();
	228	spin_unlock_irqrestore(&ds1511_lock, flags);
	229
	230	return 0;
	231	}
	232
a3ed107e	233	static int ds1511_rtc_read_time(struct device dev, struct rtc_time rtc_tm)
8f26795a AS	234	{
8f26795a AS	235	unsigned int century;
9a0f4aea	236	unsigned long flags;
8f26795a AS	237
	238	spin_lock_irqsave(&ds1511_lock, flags);
	239	rtc_disable_update();
	240
	241	rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f;
	242	rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f;
	243	rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f;
	244	rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f;
	245	rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7;
	246	rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f;
	247	rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f;
	248	century = rtc_read(RTC_CENTURY);
	249
	250	rtc_enable_update();
	251	spin_unlock_irqrestore(&ds1511_lock, flags);
	252
fe20ba70 AB	253	rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
	254	rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
	255	rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
	256	rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
	257	rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
	258	rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
	259	rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
	260	century = bcd2bin(century) * 100;
8f26795a AS	261
	262	/*
	263	* Account for differences between how the RTC uses the values
	264	* and how they are defined in a struct rtc_time;
	265	*/
	266	century += rtc_tm->tm_year;
	267	rtc_tm->tm_year = century - 1900;
	268
	269	rtc_tm->tm_mon--;
	270
8f26795a AS	271	return 0;
	272	}
	273
	274	/*
	275	* write the alarm register settings
	276	*
	277	* we only have the use to interrupt every second, otherwise
	278	* known as the update interrupt, or the interrupt if the whole
	279	* date/hours/mins/secs matches. the ds1511 has many more
	280	* permutations, but the kernel doesn't.
	281	*/
7b2f0053	282	static void
8f26795a AS	283	ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
	284	{
	285	unsigned long flags;
	286
ba4f3e47	287	spin_lock_irqsave(&pdata->lock, flags);
8f26795a	288	rtc_write(pdata->alrm_mday < 0 \|\| (pdata->irqen & RTC_UF) ?
fe20ba70	289	0x80 : bin2bcd(pdata->alrm_mday) & 0x3f,
8f26795a AS	290	RTC_ALARM_DATE);
8f26795a AS	291	rtc_write(pdata->alrm_hour < 0 \|\| (pdata->irqen & RTC_UF) ?
fe20ba70	292	0x80 : bin2bcd(pdata->alrm_hour) & 0x3f,
8f26795a AS	293	RTC_ALARM_HOUR);
8f26795a AS	294	rtc_write(pdata->alrm_min < 0 \|\| (pdata->irqen & RTC_UF) ?
fe20ba70	295	0x80 : bin2bcd(pdata->alrm_min) & 0x7f,
8f26795a AS	296	RTC_ALARM_MIN);
8f26795a AS	297	rtc_write(pdata->alrm_sec < 0 \|\| (pdata->irqen & RTC_UF) ?
fe20ba70	298	0x80 : bin2bcd(pdata->alrm_sec) & 0x7f,
8f26795a AS	299	RTC_ALARM_SEC);
	300	rtc_write(rtc_read(RTC_CMD) \| (pdata->irqen ? RTC_TIE : 0), RTC_CMD);
	301	rtc_read(RTC_CMD1); /* clear interrupts */
ba4f3e47	302	spin_unlock_irqrestore(&pdata->lock, flags);
8f26795a AS	303	}
8f26795a AS	304
7b2f0053	305	static int
8f26795a AS	306	ds1511_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
8f26795a AS	307	{
85368bb9	308	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
8f26795a	309
2fac6674	310	if (pdata->irq <= 0)
8f26795a	311	return -EINVAL;
2fac6674	312
8f26795a AS	313	pdata->alrm_mday = alrm->time.tm_mday;
	314	pdata->alrm_hour = alrm->time.tm_hour;
	315	pdata->alrm_min = alrm->time.tm_min;
	316	pdata->alrm_sec = alrm->time.tm_sec;
7b2f0053	317	if (alrm->enabled)
8f26795a	318	pdata->irqen \|= RTC_AF;
7b2f0053	319
8f26795a AS	320	ds1511_rtc_update_alarm(pdata);
	321	return 0;
	322	}
	323
7b2f0053	324	static int
8f26795a AS	325	ds1511_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
8f26795a AS	326	{
85368bb9	327	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
8f26795a	328
2fac6674	329	if (pdata->irq <= 0)
8f26795a	330	return -EINVAL;
2fac6674	331
8f26795a AS	332	alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
	333	alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
	334	alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
	335	alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
	336	alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
	337	return 0;
	338	}
	339
7b2f0053	340	static irqreturn_t
8f26795a AS	341	ds1511_interrupt(int irq, void *dev_id)
	342	{
	343	struct platform_device *pdev = dev_id;
	344	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
ba4f3e47	345	unsigned long events = 0;
8f26795a	346
ba4f3e47	347	spin_lock(&pdata->lock);
8f26795a AS	348	/*
	349	* read and clear interrupt
	350	*/
ba4f3e47 AN	351	if (rtc_read(RTC_CMD1) & DS1511_IRQF) {
	352	events = RTC_IRQF;
	353	if (rtc_read(RTC_ALARM_SEC) & 0x80)
	354	events \|= RTC_UF;
	355	else
	356	events \|= RTC_AF;
0d71915d	357	rtc_update_irq(pdata->rtc, 1, events);
ba4f3e47 AN	358	}
	359	spin_unlock(&pdata->lock);
	360	return events ? IRQ_HANDLED : IRQ_NONE;
8f26795a AS	361	}
8f26795a AS	362
ba4f3e47	363	static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
8f26795a	364	{
85368bb9	365	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
8f26795a	366
ba4f3e47 AN	367	if (pdata->irq <= 0)
	368	return -EINVAL;
	369	if (enabled)
8f26795a	370	pdata->irqen \|= RTC_AF;
ba4f3e47 AN	371	else
	372	pdata->irqen &= ~RTC_AF;
	373	ds1511_rtc_update_alarm(pdata);
	374	return 0;
	375	}
	376
8f26795a	377	static const struct rtc_class_ops ds1511_rtc_ops = {
ba4f3e47 AN	378	.read_time = ds1511_rtc_read_time,
	379	.set_time = ds1511_rtc_set_time,
	380	.read_alarm = ds1511_rtc_read_alarm,
	381	.set_alarm = ds1511_rtc_set_alarm,
	382	.alarm_irq_enable = ds1511_rtc_alarm_irq_enable,
8f26795a AS	383	};
8f26795a AS	384
9d7ed21f AB	385	static int ds1511_nvram_read(void priv, unsigned int pos, void buf,
9d7ed21f AB	386	size_t size)
8f26795a	387	{
9d7ed21f	388	int i;
8f26795a	389
8f26795a	390	rtc_write(pos, DS1511_RAMADDR_LSB);
9d7ed21f AB	391	for (i = 0; i < size; i++)
9d7ed21f AB	392	(char )buf++ = rtc_read(DS1511_RAMDATA);
7b2f0053	393
9d7ed21f	394	return 0;
8f26795a AS	395	}
8f26795a AS	396
9d7ed21f AB	397	static int ds1511_nvram_write(void priv, unsigned int pos, void buf,
9d7ed21f AB	398	size_t size)
8f26795a	399	{
9d7ed21f	400	int i;
8f26795a	401
8f26795a	402	rtc_write(pos, DS1511_RAMADDR_LSB);
9d7ed21f AB	403	for (i = 0; i < size; i++)
9d7ed21f AB	404	rtc_write((char )buf++, DS1511_RAMDATA);
7b2f0053	405
9d7ed21f	406	return 0;
8f26795a AS	407	}
8f26795a AS	408
5a167f45	409	static int ds1511_rtc_probe(struct platform_device *pdev)
8f26795a	410	{
ba4f3e47	411	struct rtc_plat_data *pdata;
8f26795a	412	int ret = 0;
71e19c5e AB	413	struct nvmem_config ds1511_nvmem_cfg = {
	414	.name = "ds1511_nvram",
	415	.word_size = 1,
	416	.stride = 1,
	417	.size = DS1511_RAM_MAX,
	418	.reg_read = ds1511_nvram_read,
	419	.reg_write = ds1511_nvram_write,
	420	.priv = &pdev->dev,
	421	};
8f26795a	422
ba4f3e47 AN	423	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
ba4f3e47 AN	424	if (!pdata)
8f26795a	425	return -ENOMEM;
7c1d69ee	426
09ef18bc	427	ds1511_base = devm_platform_ioremap_resource(pdev, 0);
7c1d69ee JL	428	if (IS_ERR(ds1511_base))
7c1d69ee JL	429	return PTR_ERR(ds1511_base);
8f26795a AS	430	pdata->ioaddr = ds1511_base;
	431	pdata->irq = platform_get_irq(pdev, 0);
	432
	433	/*
	434	* turn on the clock and the crystal, etc.
	435	*/
8ccba142	436	rtc_write(DS1511_BME, RTC_CMD);
8f26795a AS	437	rtc_write(0, RTC_CMD1);
	438	/*
	439	* clear the wdog counter
	440	*/
	441	rtc_write(0, DS1511_WD_MSEC);
	442	rtc_write(0, DS1511_WD_SEC);
	443	/*
	444	* start the clock
	445	*/
	446	rtc_enable_update();
	447
	448	/*
	449	* check for a dying bat-tree
	450	*/
7b2f0053	451	if (rtc_read(RTC_CMD1) & DS1511_BLF1)
8f26795a	452	dev_warn(&pdev->dev, "voltage-low detected.\n");
8f26795a	453
ba4f3e47 AN	454	spin_lock_init(&pdata->lock);
ba4f3e47 AN	455	platform_set_drvdata(pdev, pdata);
4071ea25	456
3032269b	457	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
4071ea25 AZ	458	if (IS_ERR(pdata->rtc))
	459	return PTR_ERR(pdata->rtc);
	460
3032269b AB	461	pdata->rtc->ops = &ds1511_rtc_ops;
3032269b AB	462
fdcfd854	463	ret = devm_rtc_register_device(pdata->rtc);
3032269b AB	464	if (ret)
	465	return ret;
	466
3a905c2d	467	devm_rtc_nvmem_register(pdata->rtc, &ds1511_nvmem_cfg);
16fef391	468
8f26795a AS	469	/*
	470	* if the platform has an interrupt in mind for this device,
	471	* then by all means, set it
	472	*/
2fac6674	473	if (pdata->irq > 0) {
8f26795a	474	rtc_read(RTC_CMD1);
ba4f3e47	475	if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt,
2f6e5f94	476	IRQF_SHARED, pdev->name, pdev) < 0) {
8f26795a AS	477
8f26795a AS	478	dev_warn(&pdev->dev, "interrupt not available.\n");
2fac6674	479	pdata->irq = 0;
8f26795a AS	480	}
	481	}
	482
8f26795a AS	483	return 0;
	484	}
	485
ad28a07b KS	486	/* work with hotplug and coldplug */
	487	MODULE_ALIAS("platform:ds1511");
	488
8f26795a AS	489	static struct platform_driver ds1511_rtc_driver = {
8f26795a AS	490	.probe = ds1511_rtc_probe,
8f26795a AS	491	.driver = {
8f26795a AS	492	.name = "ds1511",
8f26795a AS	493	},
	494	};
	495
0c4eae66	496	module_platform_driver(ds1511_rtc_driver);
8f26795a	497
5b73a41c	498	MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
8f26795a AS	499	MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
8f26795a AS	500	MODULE_LICENSE("GPL");