]>
Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
aaaf5fbf JK |
2 | /* |
3 | * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time | |
4 | * chips. | |
5 | * | |
6 | * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>. | |
7 | * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>. | |
8 | * | |
9 | * References: | |
10 | * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. | |
11 | * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. | |
12 | * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. | |
13 | * Application Note 90, Using the Multiplex Bus RTC Extended Features. | |
aaaf5fbf JK |
14 | */ |
15 | ||
a737e835 JP |
16 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
17 | ||
aaaf5fbf JK |
18 | #include <linux/bcd.h> |
19 | #include <linux/delay.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/workqueue.h> | |
25 | ||
26 | #include <linux/rtc/ds1685.h> | |
27 | ||
28 | #ifdef CONFIG_PROC_FS | |
29 | #include <linux/proc_fs.h> | |
30 | #endif | |
31 | ||
aaaf5fbf JK |
32 | |
33 | /* ----------------------------------------------------------------------- */ | |
34 | /* Standard read/write functions if platform does not provide overrides */ | |
35 | ||
36 | /** | |
37 | * ds1685_read - read a value from an rtc register. | |
38 | * @rtc: pointer to the ds1685 rtc structure. | |
39 | * @reg: the register address to read. | |
40 | */ | |
41 | static u8 | |
42 | ds1685_read(struct ds1685_priv *rtc, int reg) | |
43 | { | |
44 | return readb((u8 __iomem *)rtc->regs + | |
45 | (reg * rtc->regstep)); | |
46 | } | |
47 | ||
48 | /** | |
49 | * ds1685_write - write a value to an rtc register. | |
50 | * @rtc: pointer to the ds1685 rtc structure. | |
51 | * @reg: the register address to write. | |
52 | * @value: value to write to the register. | |
53 | */ | |
54 | static void | |
55 | ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) | |
56 | { | |
57 | writeb(value, ((u8 __iomem *)rtc->regs + | |
58 | (reg * rtc->regstep))); | |
59 | } | |
60 | /* ----------------------------------------------------------------------- */ | |
61 | ||
62 | ||
63 | /* ----------------------------------------------------------------------- */ | |
64 | /* Inlined functions */ | |
65 | ||
66 | /** | |
67 | * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD. | |
68 | * @rtc: pointer to the ds1685 rtc structure. | |
69 | * @val: u8 time value to consider converting. | |
70 | * @bcd_mask: u8 mask value if BCD mode is used. | |
71 | * @bin_mask: u8 mask value if BIN mode is used. | |
72 | * | |
73 | * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE. | |
74 | */ | |
75 | static inline u8 | |
76 | ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask) | |
77 | { | |
78 | if (rtc->bcd_mode) | |
79 | return (bcd2bin(val) & bcd_mask); | |
80 | ||
81 | return (val & bin_mask); | |
82 | } | |
83 | ||
84 | /** | |
85 | * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD. | |
86 | * @rtc: pointer to the ds1685 rtc structure. | |
87 | * @val: u8 time value to consider converting. | |
88 | * @bin_mask: u8 mask value if BIN mode is used. | |
89 | * @bcd_mask: u8 mask value if BCD mode is used. | |
90 | * | |
91 | * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE. | |
92 | */ | |
93 | static inline u8 | |
94 | ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask) | |
95 | { | |
96 | if (rtc->bcd_mode) | |
97 | return (bin2bcd(val) & bcd_mask); | |
98 | ||
99 | return (val & bin_mask); | |
100 | } | |
101 | ||
c5776dec HS |
102 | /** |
103 | * s1685_rtc_check_mday - check validity of the day of month. | |
104 | * @rtc: pointer to the ds1685 rtc structure. | |
105 | * @mday: day of month. | |
106 | * | |
107 | * Returns -EDOM if the day of month is not within 1..31 range. | |
108 | */ | |
109 | static inline int | |
110 | ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday) | |
111 | { | |
112 | if (rtc->bcd_mode) { | |
113 | if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09) | |
114 | return -EDOM; | |
115 | } else { | |
116 | if (mday < 1 || mday > 31) | |
117 | return -EDOM; | |
118 | } | |
119 | return 0; | |
120 | } | |
121 | ||
aaaf5fbf JK |
122 | /** |
123 | * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. | |
124 | * @rtc: pointer to the ds1685 rtc structure. | |
125 | */ | |
126 | static inline void | |
127 | ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) | |
128 | { | |
129 | rtc->write(rtc, RTC_CTRL_A, | |
130 | (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); | |
131 | } | |
132 | ||
133 | /** | |
134 | * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. | |
135 | * @rtc: pointer to the ds1685 rtc structure. | |
136 | */ | |
137 | static inline void | |
138 | ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) | |
139 | { | |
140 | rtc->write(rtc, RTC_CTRL_A, | |
141 | (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); | |
142 | } | |
143 | ||
144 | /** | |
145 | * ds1685_rtc_begin_data_access - prepare the rtc for data access. | |
146 | * @rtc: pointer to the ds1685 rtc structure. | |
147 | * | |
148 | * This takes several steps to prepare the rtc for access to get/set time | |
149 | * and alarm values from the rtc registers: | |
150 | * - Sets the SET bit in Control Register B. | |
151 | * - Reads Ext Control Register 4A and checks the INCR bit. | |
152 | * - If INCR is active, a short delay is added before Ext Control Register 4A | |
153 | * is read again in a loop until INCR is inactive. | |
154 | * - Switches the rtc to bank 1. This allows access to all relevant | |
155 | * data for normal rtc operation, as bank 0 contains only the nvram. | |
156 | */ | |
157 | static inline void | |
158 | ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) | |
159 | { | |
160 | /* Set the SET bit in Ctrl B */ | |
161 | rtc->write(rtc, RTC_CTRL_B, | |
162 | (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); | |
163 | ||
164 | /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ | |
165 | while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) | |
166 | cpu_relax(); | |
167 | ||
168 | /* Switch to Bank 1 */ | |
169 | ds1685_rtc_switch_to_bank1(rtc); | |
170 | } | |
171 | ||
172 | /** | |
173 | * ds1685_rtc_end_data_access - end data access on the rtc. | |
174 | * @rtc: pointer to the ds1685 rtc structure. | |
175 | * | |
176 | * This ends what was started by ds1685_rtc_begin_data_access: | |
177 | * - Switches the rtc back to bank 0. | |
178 | * - Clears the SET bit in Control Register B. | |
179 | */ | |
180 | static inline void | |
181 | ds1685_rtc_end_data_access(struct ds1685_priv *rtc) | |
182 | { | |
183 | /* Switch back to Bank 0 */ | |
184 | ds1685_rtc_switch_to_bank1(rtc); | |
185 | ||
186 | /* Clear the SET bit in Ctrl B */ | |
187 | rtc->write(rtc, RTC_CTRL_B, | |
188 | (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); | |
189 | } | |
190 | ||
aaaf5fbf JK |
191 | /** |
192 | * ds1685_rtc_get_ssn - retrieve the silicon serial number. | |
193 | * @rtc: pointer to the ds1685 rtc structure. | |
194 | * @ssn: u8 array to hold the bits of the silicon serial number. | |
195 | * | |
196 | * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The | |
197 | * first byte is the model number, the next six bytes are the serial number | |
198 | * digits, and the final byte is a CRC check byte. Together, they form the | |
199 | * silicon serial number. | |
200 | * | |
201 | * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be | |
202 | * called first before calling this function, else data will be read out of | |
203 | * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done. | |
204 | */ | |
205 | static inline void | |
206 | ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) | |
207 | { | |
208 | ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL); | |
209 | ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1); | |
210 | ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2); | |
211 | ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3); | |
212 | ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4); | |
213 | ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5); | |
214 | ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6); | |
215 | ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC); | |
216 | } | |
217 | /* ----------------------------------------------------------------------- */ | |
218 | ||
219 | ||
220 | /* ----------------------------------------------------------------------- */ | |
221 | /* Read/Set Time & Alarm functions */ | |
222 | ||
223 | /** | |
224 | * ds1685_rtc_read_time - reads the time registers. | |
225 | * @dev: pointer to device structure. | |
226 | * @tm: pointer to rtc_time structure. | |
227 | */ | |
228 | static int | |
229 | ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
230 | { | |
85368bb9 | 231 | struct ds1685_priv *rtc = dev_get_drvdata(dev); |
aaaf5fbf JK |
232 | u8 ctrlb, century; |
233 | u8 seconds, minutes, hours, wday, mday, month, years; | |
234 | ||
235 | /* Fetch the time info from the RTC registers. */ | |
236 | ds1685_rtc_begin_data_access(rtc); | |
237 | seconds = rtc->read(rtc, RTC_SECS); | |
238 | minutes = rtc->read(rtc, RTC_MINS); | |
239 | hours = rtc->read(rtc, RTC_HRS); | |
240 | wday = rtc->read(rtc, RTC_WDAY); | |
241 | mday = rtc->read(rtc, RTC_MDAY); | |
242 | month = rtc->read(rtc, RTC_MONTH); | |
243 | years = rtc->read(rtc, RTC_YEAR); | |
244 | century = rtc->read(rtc, RTC_CENTURY); | |
245 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
246 | ds1685_rtc_end_data_access(rtc); | |
247 | ||
248 | /* bcd2bin if needed, perform fixups, and store to rtc_time. */ | |
249 | years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK, | |
250 | RTC_YEAR_BIN_MASK); | |
251 | century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK, | |
252 | RTC_CENTURY_MASK); | |
253 | tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK, | |
254 | RTC_SECS_BIN_MASK); | |
255 | tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK, | |
256 | RTC_MINS_BIN_MASK); | |
257 | tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK, | |
258 | RTC_HRS_24_BIN_MASK); | |
259 | tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK, | |
260 | RTC_WDAY_MASK) - 1); | |
261 | tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, | |
262 | RTC_MDAY_BIN_MASK); | |
263 | tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK, | |
264 | RTC_MONTH_BIN_MASK) - 1); | |
265 | tm->tm_year = ((years + (century * 100)) - 1900); | |
266 | tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); | |
267 | tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ | |
268 | ||
22652ba7 | 269 | return 0; |
aaaf5fbf JK |
270 | } |
271 | ||
272 | /** | |
273 | * ds1685_rtc_set_time - sets the time registers. | |
274 | * @dev: pointer to device structure. | |
275 | * @tm: pointer to rtc_time structure. | |
276 | */ | |
277 | static int | |
278 | ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
279 | { | |
85368bb9 | 280 | struct ds1685_priv *rtc = dev_get_drvdata(dev); |
aaaf5fbf JK |
281 | u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century; |
282 | ||
283 | /* Fetch the time info from rtc_time. */ | |
284 | seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK, | |
285 | RTC_SECS_BCD_MASK); | |
286 | minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK, | |
287 | RTC_MINS_BCD_MASK); | |
288 | hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK, | |
289 | RTC_HRS_24_BCD_MASK); | |
290 | wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK, | |
291 | RTC_WDAY_MASK); | |
292 | mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK, | |
293 | RTC_MDAY_BCD_MASK); | |
294 | month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK, | |
295 | RTC_MONTH_BCD_MASK); | |
296 | years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100), | |
297 | RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK); | |
298 | century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100), | |
299 | RTC_CENTURY_MASK, RTC_CENTURY_MASK); | |
300 | ||
301 | /* | |
302 | * Perform Sanity Checks: | |
303 | * - Months: !> 12, Month Day != 0. | |
304 | * - Month Day !> Max days in current month. | |
305 | * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. | |
306 | */ | |
307 | if ((tm->tm_mon > 11) || (mday == 0)) | |
308 | return -EDOM; | |
309 | ||
310 | if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) | |
311 | return -EDOM; | |
312 | ||
313 | if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || | |
314 | (tm->tm_sec >= 60) || (wday > 7)) | |
315 | return -EDOM; | |
316 | ||
317 | /* | |
318 | * Set the data mode to use and store the time values in the | |
319 | * RTC registers. | |
320 | */ | |
321 | ds1685_rtc_begin_data_access(rtc); | |
322 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
323 | if (rtc->bcd_mode) | |
324 | ctrlb &= ~(RTC_CTRL_B_DM); | |
325 | else | |
326 | ctrlb |= RTC_CTRL_B_DM; | |
327 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
328 | rtc->write(rtc, RTC_SECS, seconds); | |
329 | rtc->write(rtc, RTC_MINS, minutes); | |
330 | rtc->write(rtc, RTC_HRS, hours); | |
331 | rtc->write(rtc, RTC_WDAY, wday); | |
332 | rtc->write(rtc, RTC_MDAY, mday); | |
333 | rtc->write(rtc, RTC_MONTH, month); | |
334 | rtc->write(rtc, RTC_YEAR, years); | |
335 | rtc->write(rtc, RTC_CENTURY, century); | |
336 | ds1685_rtc_end_data_access(rtc); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | /** | |
342 | * ds1685_rtc_read_alarm - reads the alarm registers. | |
343 | * @dev: pointer to device structure. | |
344 | * @alrm: pointer to rtc_wkalrm structure. | |
345 | * | |
346 | * There are three primary alarm registers: seconds, minutes, and hours. | |
347 | * A fourth alarm register for the month date is also available in bank1 for | |
348 | * kickstart/wakeup features. The DS1685/DS1687 manual states that a | |
349 | * "don't care" value ranging from 0xc0 to 0xff may be written into one or | |
350 | * more of the three alarm bytes to act as a wildcard value. The fourth | |
351 | * byte doesn't support a "don't care" value. | |
352 | */ | |
353 | static int | |
354 | ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
355 | { | |
85368bb9 | 356 | struct ds1685_priv *rtc = dev_get_drvdata(dev); |
aaaf5fbf | 357 | u8 seconds, minutes, hours, mday, ctrlb, ctrlc; |
c5776dec | 358 | int ret; |
aaaf5fbf JK |
359 | |
360 | /* Fetch the alarm info from the RTC alarm registers. */ | |
361 | ds1685_rtc_begin_data_access(rtc); | |
362 | seconds = rtc->read(rtc, RTC_SECS_ALARM); | |
363 | minutes = rtc->read(rtc, RTC_MINS_ALARM); | |
364 | hours = rtc->read(rtc, RTC_HRS_ALARM); | |
365 | mday = rtc->read(rtc, RTC_MDAY_ALARM); | |
366 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
367 | ctrlc = rtc->read(rtc, RTC_CTRL_C); | |
368 | ds1685_rtc_end_data_access(rtc); | |
369 | ||
c5776dec HS |
370 | /* Check the month date for validity. */ |
371 | ret = ds1685_rtc_check_mday(rtc, mday); | |
372 | if (ret) | |
373 | return ret; | |
aaaf5fbf JK |
374 | |
375 | /* | |
376 | * Check the three alarm bytes. | |
377 | * | |
378 | * The Linux RTC system doesn't support the "don't care" capability | |
379 | * of this RTC chip. We check for it anyways in case support is | |
56d86a7e | 380 | * added in the future and only assign when we care. |
aaaf5fbf | 381 | */ |
56d86a7e | 382 | if (likely(seconds < 0xc0)) |
aaaf5fbf JK |
383 | alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, |
384 | RTC_SECS_BCD_MASK, | |
385 | RTC_SECS_BIN_MASK); | |
386 | ||
56d86a7e | 387 | if (likely(minutes < 0xc0)) |
aaaf5fbf JK |
388 | alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes, |
389 | RTC_MINS_BCD_MASK, | |
390 | RTC_MINS_BIN_MASK); | |
391 | ||
56d86a7e | 392 | if (likely(hours < 0xc0)) |
aaaf5fbf JK |
393 | alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours, |
394 | RTC_HRS_24_BCD_MASK, | |
395 | RTC_HRS_24_BIN_MASK); | |
396 | ||
397 | /* Write the data to rtc_wkalrm. */ | |
398 | alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, | |
399 | RTC_MDAY_BIN_MASK); | |
aaaf5fbf JK |
400 | alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); |
401 | alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | /** | |
407 | * ds1685_rtc_set_alarm - sets the alarm in registers. | |
408 | * @dev: pointer to device structure. | |
409 | * @alrm: pointer to rtc_wkalrm structure. | |
410 | */ | |
411 | static int | |
412 | ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
413 | { | |
85368bb9 | 414 | struct ds1685_priv *rtc = dev_get_drvdata(dev); |
aaaf5fbf | 415 | u8 ctrlb, seconds, minutes, hours, mday; |
c5776dec | 416 | int ret; |
aaaf5fbf JK |
417 | |
418 | /* Fetch the alarm info and convert to BCD. */ | |
419 | seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec, | |
420 | RTC_SECS_BIN_MASK, | |
421 | RTC_SECS_BCD_MASK); | |
422 | minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min, | |
423 | RTC_MINS_BIN_MASK, | |
424 | RTC_MINS_BCD_MASK); | |
425 | hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour, | |
426 | RTC_HRS_24_BIN_MASK, | |
427 | RTC_HRS_24_BCD_MASK); | |
428 | mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday, | |
429 | RTC_MDAY_BIN_MASK, | |
430 | RTC_MDAY_BCD_MASK); | |
431 | ||
432 | /* Check the month date for validity. */ | |
c5776dec HS |
433 | ret = ds1685_rtc_check_mday(rtc, mday); |
434 | if (ret) | |
435 | return ret; | |
aaaf5fbf JK |
436 | |
437 | /* | |
438 | * Check the three alarm bytes. | |
439 | * | |
440 | * The Linux RTC system doesn't support the "don't care" capability | |
441 | * of this RTC chip because rtc_valid_tm tries to validate every | |
442 | * field, and we only support four fields. We put the support | |
443 | * here anyways for the future. | |
444 | */ | |
39ea34cc | 445 | if (unlikely(seconds >= 0xc0)) |
aaaf5fbf JK |
446 | seconds = 0xff; |
447 | ||
39ea34cc | 448 | if (unlikely(minutes >= 0xc0)) |
aaaf5fbf JK |
449 | minutes = 0xff; |
450 | ||
39ea34cc | 451 | if (unlikely(hours >= 0xc0)) |
aaaf5fbf JK |
452 | hours = 0xff; |
453 | ||
454 | alrm->time.tm_mon = -1; | |
455 | alrm->time.tm_year = -1; | |
456 | alrm->time.tm_wday = -1; | |
457 | alrm->time.tm_yday = -1; | |
458 | alrm->time.tm_isdst = -1; | |
459 | ||
460 | /* Disable the alarm interrupt first. */ | |
461 | ds1685_rtc_begin_data_access(rtc); | |
462 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
463 | rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); | |
464 | ||
465 | /* Read ctrlc to clear RTC_CTRL_C_AF. */ | |
466 | rtc->read(rtc, RTC_CTRL_C); | |
467 | ||
468 | /* | |
469 | * Set the data mode to use and store the time values in the | |
470 | * RTC registers. | |
471 | */ | |
472 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
473 | if (rtc->bcd_mode) | |
474 | ctrlb &= ~(RTC_CTRL_B_DM); | |
475 | else | |
476 | ctrlb |= RTC_CTRL_B_DM; | |
477 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
478 | rtc->write(rtc, RTC_SECS_ALARM, seconds); | |
479 | rtc->write(rtc, RTC_MINS_ALARM, minutes); | |
480 | rtc->write(rtc, RTC_HRS_ALARM, hours); | |
481 | rtc->write(rtc, RTC_MDAY_ALARM, mday); | |
482 | ||
483 | /* Re-enable the alarm if needed. */ | |
484 | if (alrm->enabled) { | |
485 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
486 | ctrlb |= RTC_CTRL_B_AIE; | |
487 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
488 | } | |
489 | ||
490 | /* Done! */ | |
491 | ds1685_rtc_end_data_access(rtc); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | /* ----------------------------------------------------------------------- */ | |
496 | ||
497 | ||
498 | /* ----------------------------------------------------------------------- */ | |
499 | /* /dev/rtcX Interface functions */ | |
500 | ||
aaaf5fbf JK |
501 | /** |
502 | * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. | |
503 | * @dev: pointer to device structure. | |
504 | * @enabled: flag indicating whether to enable or disable. | |
505 | */ | |
506 | static int | |
507 | ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
508 | { | |
509 | struct ds1685_priv *rtc = dev_get_drvdata(dev); | |
aaaf5fbf JK |
510 | |
511 | /* Flip the requisite interrupt-enable bit. */ | |
512 | if (enabled) | |
513 | rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) | | |
514 | RTC_CTRL_B_AIE)); | |
515 | else | |
516 | rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) & | |
517 | ~(RTC_CTRL_B_AIE))); | |
518 | ||
519 | /* Read Control C to clear all the flag bits. */ | |
520 | rtc->read(rtc, RTC_CTRL_C); | |
aaaf5fbf JK |
521 | |
522 | return 0; | |
523 | } | |
aaaf5fbf JK |
524 | /* ----------------------------------------------------------------------- */ |
525 | ||
526 | ||
527 | /* ----------------------------------------------------------------------- */ | |
3b6bddda | 528 | /* IRQ handler */ |
aaaf5fbf JK |
529 | |
530 | /** | |
3b6bddda TB |
531 | * ds1685_rtc_extended_irq - take care of extended interrupts |
532 | * @rtc: pointer to the ds1685 rtc structure. | |
533 | * @pdev: platform device pointer. | |
aaaf5fbf JK |
534 | */ |
535 | static void | |
3b6bddda | 536 | ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev) |
aaaf5fbf | 537 | { |
aaaf5fbf JK |
538 | u8 ctrl4a, ctrl4b; |
539 | ||
aaaf5fbf JK |
540 | ds1685_rtc_switch_to_bank1(rtc); |
541 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
542 | ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); | |
543 | ||
544 | /* | |
545 | * Check for a kickstart interrupt. With Vcc applied, this | |
546 | * typically means that the power button was pressed, so we | |
547 | * begin the shutdown sequence. | |
548 | */ | |
549 | if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) { | |
550 | /* Briefly disable kickstarts to debounce button presses. */ | |
551 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
552 | (rtc->read(rtc, RTC_EXT_CTRL_4B) & | |
553 | ~(RTC_CTRL_4B_KSE))); | |
554 | ||
555 | /* Clear the kickstart flag. */ | |
556 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
557 | (ctrl4a & ~(RTC_CTRL_4A_KF))); | |
558 | ||
559 | ||
560 | /* | |
561 | * Sleep 500ms before re-enabling kickstarts. This allows | |
562 | * adequate time to avoid reading signal jitter as additional | |
563 | * button presses. | |
564 | */ | |
565 | msleep(500); | |
566 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
567 | (rtc->read(rtc, RTC_EXT_CTRL_4B) | | |
568 | RTC_CTRL_4B_KSE)); | |
569 | ||
570 | /* Call the platform pre-poweroff function. Else, shutdown. */ | |
571 | if (rtc->prepare_poweroff != NULL) | |
572 | rtc->prepare_poweroff(); | |
573 | else | |
574 | ds1685_rtc_poweroff(pdev); | |
575 | } | |
576 | ||
577 | /* | |
578 | * Check for a wake-up interrupt. With Vcc applied, this is | |
579 | * essentially a second alarm interrupt, except it takes into | |
580 | * account the 'date' register in bank1 in addition to the | |
581 | * standard three alarm registers. | |
582 | */ | |
583 | if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) { | |
584 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
585 | (ctrl4a & ~(RTC_CTRL_4A_WF))); | |
586 | ||
587 | /* Call the platform wake_alarm function if defined. */ | |
588 | if (rtc->wake_alarm != NULL) | |
589 | rtc->wake_alarm(); | |
590 | else | |
591 | dev_warn(&pdev->dev, | |
592 | "Wake Alarm IRQ just occurred!\n"); | |
593 | } | |
594 | ||
595 | /* | |
596 | * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 | |
597 | * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting | |
598 | * each byte to a logic 1. This has no effect on any extended | |
599 | * NV-SRAM that might be present, nor on the time/calendar/alarm | |
600 | * registers. After a ram-clear is completed, there is a minimum | |
601 | * recovery time of ~150ms in which all reads/writes are locked out. | |
602 | * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot | |
603 | * catch this scenario. | |
604 | */ | |
605 | if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) { | |
606 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
607 | (ctrl4a & ~(RTC_CTRL_4A_RF))); | |
608 | msleep(150); | |
609 | ||
610 | /* Call the platform post_ram_clear function if defined. */ | |
611 | if (rtc->post_ram_clear != NULL) | |
612 | rtc->post_ram_clear(); | |
613 | else | |
614 | dev_warn(&pdev->dev, | |
615 | "RAM-Clear IRQ just occurred!\n"); | |
616 | } | |
617 | ds1685_rtc_switch_to_bank0(rtc); | |
3b6bddda TB |
618 | } |
619 | ||
620 | /** | |
621 | * ds1685_rtc_irq_handler - IRQ handler. | |
622 | * @irq: IRQ number. | |
623 | * @dev_id: platform device pointer. | |
624 | */ | |
625 | static irqreturn_t | |
626 | ds1685_rtc_irq_handler(int irq, void *dev_id) | |
627 | { | |
628 | struct platform_device *pdev = dev_id; | |
629 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
630 | struct mutex *rtc_mutex; | |
631 | u8 ctrlb, ctrlc; | |
632 | unsigned long events = 0; | |
633 | u8 num_irqs = 0; | |
634 | ||
635 | /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ | |
636 | if (unlikely(!rtc)) | |
637 | return IRQ_HANDLED; | |
638 | ||
639 | rtc_mutex = &rtc->dev->ops_lock; | |
640 | mutex_lock(rtc_mutex); | |
641 | ||
642 | /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ | |
643 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
644 | ctrlc = rtc->read(rtc, RTC_CTRL_C); | |
645 | ||
646 | /* Is the IRQF bit set? */ | |
647 | if (likely(ctrlc & RTC_CTRL_C_IRQF)) { | |
648 | /* | |
649 | * We need to determine if it was one of the standard | |
650 | * events: PF, AF, or UF. If so, we handle them and | |
651 | * update the RTC core. | |
652 | */ | |
653 | if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { | |
654 | events = RTC_IRQF; | |
655 | ||
656 | /* Check for a periodic interrupt. */ | |
657 | if ((ctrlb & RTC_CTRL_B_PIE) && | |
658 | (ctrlc & RTC_CTRL_C_PF)) { | |
659 | events |= RTC_PF; | |
660 | num_irqs++; | |
661 | } | |
662 | ||
663 | /* Check for an alarm interrupt. */ | |
664 | if ((ctrlb & RTC_CTRL_B_AIE) && | |
665 | (ctrlc & RTC_CTRL_C_AF)) { | |
666 | events |= RTC_AF; | |
667 | num_irqs++; | |
668 | } | |
aaaf5fbf | 669 | |
3b6bddda TB |
670 | /* Check for an update interrupt. */ |
671 | if ((ctrlb & RTC_CTRL_B_UIE) && | |
672 | (ctrlc & RTC_CTRL_C_UF)) { | |
673 | events |= RTC_UF; | |
674 | num_irqs++; | |
675 | } | |
676 | } else { | |
677 | /* | |
678 | * One of the "extended" interrupts was received that | |
679 | * is not recognized by the RTC core. | |
680 | */ | |
681 | ds1685_rtc_extended_irq(rtc, pdev); | |
682 | } | |
683 | } | |
684 | rtc_update_irq(rtc->dev, num_irqs, events); | |
aaaf5fbf | 685 | mutex_unlock(rtc_mutex); |
3b6bddda TB |
686 | |
687 | return events ? IRQ_HANDLED : IRQ_NONE; | |
aaaf5fbf JK |
688 | } |
689 | /* ----------------------------------------------------------------------- */ | |
690 | ||
691 | ||
692 | /* ----------------------------------------------------------------------- */ | |
693 | /* ProcFS interface */ | |
694 | ||
695 | #ifdef CONFIG_PROC_FS | |
696 | #define NUM_REGS 6 /* Num of control registers. */ | |
697 | #define NUM_BITS 8 /* Num bits per register. */ | |
698 | #define NUM_SPACES 4 /* Num spaces between each bit. */ | |
699 | ||
700 | /* | |
701 | * Periodic Interrupt Rates. | |
702 | */ | |
703 | static const char *ds1685_rtc_pirq_rate[16] = { | |
704 | "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", | |
705 | "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", | |
706 | "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" | |
707 | }; | |
708 | ||
709 | /* | |
710 | * Square-Wave Output Frequencies. | |
711 | */ | |
712 | static const char *ds1685_rtc_sqw_freq[16] = { | |
713 | "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz", | |
714 | "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz" | |
715 | }; | |
716 | ||
aaaf5fbf JK |
717 | /** |
718 | * ds1685_rtc_proc - procfs access function. | |
719 | * @dev: pointer to device structure. | |
720 | * @seq: pointer to seq_file structure. | |
721 | */ | |
722 | static int | |
723 | ds1685_rtc_proc(struct device *dev, struct seq_file *seq) | |
724 | { | |
6f5b390b | 725 | struct ds1685_priv *rtc = dev_get_drvdata(dev); |
aaaf5fbf | 726 | u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8]; |
52ef84d5 | 727 | char *model; |
aaaf5fbf JK |
728 | |
729 | /* Read all the relevant data from the control registers. */ | |
730 | ds1685_rtc_switch_to_bank1(rtc); | |
731 | ds1685_rtc_get_ssn(rtc, ssn); | |
732 | ctrla = rtc->read(rtc, RTC_CTRL_A); | |
733 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
734 | ctrlc = rtc->read(rtc, RTC_CTRL_C); | |
735 | ctrld = rtc->read(rtc, RTC_CTRL_D); | |
736 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
737 | ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); | |
738 | ds1685_rtc_switch_to_bank0(rtc); | |
739 | ||
740 | /* Determine the RTC model. */ | |
741 | switch (ssn[0]) { | |
742 | case RTC_MODEL_DS1685: | |
743 | model = "DS1685/DS1687\0"; | |
744 | break; | |
745 | case RTC_MODEL_DS1689: | |
746 | model = "DS1689/DS1693\0"; | |
747 | break; | |
748 | case RTC_MODEL_DS17285: | |
749 | model = "DS17285/DS17287\0"; | |
750 | break; | |
751 | case RTC_MODEL_DS17485: | |
752 | model = "DS17485/DS17487\0"; | |
753 | break; | |
754 | case RTC_MODEL_DS17885: | |
755 | model = "DS17885/DS17887\0"; | |
756 | break; | |
757 | default: | |
758 | model = "Unknown\0"; | |
759 | break; | |
760 | } | |
761 | ||
762 | /* Print out the information. */ | |
763 | seq_printf(seq, | |
764 | "Model\t\t: %s\n" | |
765 | "Oscillator\t: %s\n" | |
766 | "12/24hr\t\t: %s\n" | |
767 | "DST\t\t: %s\n" | |
768 | "Data mode\t: %s\n" | |
769 | "Battery\t\t: %s\n" | |
770 | "Aux batt\t: %s\n" | |
771 | "Update IRQ\t: %s\n" | |
772 | "Periodic IRQ\t: %s\n" | |
773 | "Periodic Rate\t: %s\n" | |
774 | "SQW Freq\t: %s\n" | |
ff67abd2 | 775 | "Serial #\t: %8phC\n", |
aaaf5fbf JK |
776 | model, |
777 | ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), | |
778 | ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), | |
779 | ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), | |
780 | ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), | |
781 | ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), | |
782 | ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), | |
783 | ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), | |
784 | ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), | |
785 | (!(ctrl4b & RTC_CTRL_4B_E32K) ? | |
786 | ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), | |
787 | (!((ctrl4b & RTC_CTRL_4B_E32K)) ? | |
788 | ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), | |
ff67abd2 | 789 | ssn); |
aaaf5fbf JK |
790 | return 0; |
791 | } | |
792 | #else | |
793 | #define ds1685_rtc_proc NULL | |
794 | #endif /* CONFIG_PROC_FS */ | |
795 | /* ----------------------------------------------------------------------- */ | |
796 | ||
797 | ||
798 | /* ----------------------------------------------------------------------- */ | |
799 | /* RTC Class operations */ | |
800 | ||
801 | static const struct rtc_class_ops | |
802 | ds1685_rtc_ops = { | |
803 | .proc = ds1685_rtc_proc, | |
804 | .read_time = ds1685_rtc_read_time, | |
805 | .set_time = ds1685_rtc_set_time, | |
806 | .read_alarm = ds1685_rtc_read_alarm, | |
807 | .set_alarm = ds1685_rtc_set_alarm, | |
808 | .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, | |
809 | }; | |
810 | /* ----------------------------------------------------------------------- */ | |
811 | ||
482419e1 AB |
812 | static int ds1685_nvram_read(void *priv, unsigned int pos, void *val, |
813 | size_t size) | |
aaaf5fbf | 814 | { |
482419e1 | 815 | struct ds1685_priv *rtc = priv; |
3b6bddda | 816 | struct mutex *rtc_mutex = &rtc->dev->ops_lock; |
aaaf5fbf | 817 | ssize_t count; |
482419e1 | 818 | u8 *buf = val; |
3b6bddda TB |
819 | int err; |
820 | ||
821 | err = mutex_lock_interruptible(rtc_mutex); | |
822 | if (err) | |
823 | return err; | |
aaaf5fbf | 824 | |
aaaf5fbf JK |
825 | ds1685_rtc_switch_to_bank0(rtc); |
826 | ||
827 | /* Read NVRAM in time and bank0 registers. */ | |
828 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; | |
829 | count++, size--) { | |
830 | if (count < NVRAM_SZ_TIME) | |
831 | *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++)); | |
832 | else | |
833 | *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++)); | |
834 | } | |
835 | ||
836 | #ifndef CONFIG_RTC_DRV_DS1689 | |
837 | if (size > 0) { | |
838 | ds1685_rtc_switch_to_bank1(rtc); | |
839 | ||
840 | #ifndef CONFIG_RTC_DRV_DS1685 | |
841 | /* Enable burst-mode on DS17x85/DS17x87 */ | |
842 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
843 | (rtc->read(rtc, RTC_EXT_CTRL_4A) | | |
844 | RTC_CTRL_4A_BME)); | |
845 | ||
846 | /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start | |
847 | * reading with burst-mode */ | |
848 | rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, | |
849 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
850 | #endif | |
851 | ||
852 | /* Read NVRAM in bank1 registers. */ | |
853 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; | |
854 | count++, size--) { | |
855 | #ifdef CONFIG_RTC_DRV_DS1685 | |
856 | /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR | |
857 | * before each read. */ | |
858 | rtc->write(rtc, RTC_BANK1_RAM_ADDR, | |
859 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
860 | #endif | |
861 | *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT); | |
862 | pos++; | |
863 | } | |
864 | ||
865 | #ifndef CONFIG_RTC_DRV_DS1685 | |
866 | /* Disable burst-mode on DS17x85/DS17x87 */ | |
867 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
868 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & | |
869 | ~(RTC_CTRL_4A_BME))); | |
870 | #endif | |
871 | ds1685_rtc_switch_to_bank0(rtc); | |
872 | } | |
873 | #endif /* !CONFIG_RTC_DRV_DS1689 */ | |
3b6bddda | 874 | mutex_unlock(rtc_mutex); |
aaaf5fbf | 875 | |
482419e1 | 876 | return 0; |
aaaf5fbf JK |
877 | } |
878 | ||
482419e1 AB |
879 | static int ds1685_nvram_write(void *priv, unsigned int pos, void *val, |
880 | size_t size) | |
aaaf5fbf | 881 | { |
482419e1 | 882 | struct ds1685_priv *rtc = priv; |
3b6bddda | 883 | struct mutex *rtc_mutex = &rtc->dev->ops_lock; |
aaaf5fbf | 884 | ssize_t count; |
482419e1 | 885 | u8 *buf = val; |
3b6bddda TB |
886 | int err; |
887 | ||
888 | err = mutex_lock_interruptible(rtc_mutex); | |
889 | if (err) | |
890 | return err; | |
aaaf5fbf | 891 | |
aaaf5fbf JK |
892 | ds1685_rtc_switch_to_bank0(rtc); |
893 | ||
894 | /* Write NVRAM in time and bank0 registers. */ | |
895 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; | |
896 | count++, size--) | |
897 | if (count < NVRAM_SZ_TIME) | |
898 | rtc->write(rtc, (NVRAM_TIME_BASE + pos++), | |
899 | *buf++); | |
900 | else | |
901 | rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++); | |
902 | ||
903 | #ifndef CONFIG_RTC_DRV_DS1689 | |
904 | if (size > 0) { | |
905 | ds1685_rtc_switch_to_bank1(rtc); | |
906 | ||
907 | #ifndef CONFIG_RTC_DRV_DS1685 | |
908 | /* Enable burst-mode on DS17x85/DS17x87 */ | |
909 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
910 | (rtc->read(rtc, RTC_EXT_CTRL_4A) | | |
911 | RTC_CTRL_4A_BME)); | |
912 | ||
913 | /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start | |
914 | * writing with burst-mode */ | |
915 | rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, | |
916 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
917 | #endif | |
918 | ||
919 | /* Write NVRAM in bank1 registers. */ | |
920 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; | |
921 | count++, size--) { | |
922 | #ifdef CONFIG_RTC_DRV_DS1685 | |
923 | /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR | |
924 | * before each read. */ | |
925 | rtc->write(rtc, RTC_BANK1_RAM_ADDR, | |
926 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
927 | #endif | |
928 | rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); | |
929 | pos++; | |
930 | } | |
931 | ||
932 | #ifndef CONFIG_RTC_DRV_DS1685 | |
933 | /* Disable burst-mode on DS17x85/DS17x87 */ | |
934 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
935 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & | |
936 | ~(RTC_CTRL_4A_BME))); | |
937 | #endif | |
938 | ds1685_rtc_switch_to_bank0(rtc); | |
939 | } | |
940 | #endif /* !CONFIG_RTC_DRV_DS1689 */ | |
3b6bddda | 941 | mutex_unlock(rtc_mutex); |
aaaf5fbf | 942 | |
482419e1 | 943 | return 0; |
aaaf5fbf JK |
944 | } |
945 | ||
482419e1 AB |
946 | /* ----------------------------------------------------------------------- */ |
947 | /* SysFS interface */ | |
aaaf5fbf JK |
948 | |
949 | /** | |
950 | * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. | |
951 | * @dev: pointer to device structure. | |
952 | * @attr: pointer to device_attribute structure. | |
953 | * @buf: pointer to char array to hold the output. | |
954 | */ | |
955 | static ssize_t | |
956 | ds1685_rtc_sysfs_battery_show(struct device *dev, | |
957 | struct device_attribute *attr, char *buf) | |
958 | { | |
692802d2 | 959 | struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); |
aaaf5fbf JK |
960 | u8 ctrld; |
961 | ||
962 | ctrld = rtc->read(rtc, RTC_CTRL_D); | |
963 | ||
9c25a106 | 964 | return sprintf(buf, "%s\n", |
aaaf5fbf JK |
965 | (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); |
966 | } | |
967 | static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); | |
968 | ||
969 | /** | |
970 | * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. | |
971 | * @dev: pointer to device structure. | |
972 | * @attr: pointer to device_attribute structure. | |
973 | * @buf: pointer to char array to hold the output. | |
974 | */ | |
975 | static ssize_t | |
976 | ds1685_rtc_sysfs_auxbatt_show(struct device *dev, | |
977 | struct device_attribute *attr, char *buf) | |
978 | { | |
692802d2 | 979 | struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); |
aaaf5fbf JK |
980 | u8 ctrl4a; |
981 | ||
982 | ds1685_rtc_switch_to_bank1(rtc); | |
983 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
984 | ds1685_rtc_switch_to_bank0(rtc); | |
985 | ||
9c25a106 | 986 | return sprintf(buf, "%s\n", |
aaaf5fbf JK |
987 | (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); |
988 | } | |
989 | static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); | |
990 | ||
991 | /** | |
992 | * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. | |
993 | * @dev: pointer to device structure. | |
994 | * @attr: pointer to device_attribute structure. | |
995 | * @buf: pointer to char array to hold the output. | |
996 | */ | |
997 | static ssize_t | |
998 | ds1685_rtc_sysfs_serial_show(struct device *dev, | |
999 | struct device_attribute *attr, char *buf) | |
1000 | { | |
692802d2 | 1001 | struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); |
aaaf5fbf JK |
1002 | u8 ssn[8]; |
1003 | ||
1004 | ds1685_rtc_switch_to_bank1(rtc); | |
1005 | ds1685_rtc_get_ssn(rtc, ssn); | |
1006 | ds1685_rtc_switch_to_bank0(rtc); | |
1007 | ||
9c25a106 | 1008 | return sprintf(buf, "%8phC\n", ssn); |
aaaf5fbf JK |
1009 | } |
1010 | static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); | |
1011 | ||
1012 | /** | |
1013 | * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. | |
1014 | */ | |
1015 | static struct attribute* | |
1016 | ds1685_rtc_sysfs_misc_attrs[] = { | |
1017 | &dev_attr_battery.attr, | |
1018 | &dev_attr_auxbatt.attr, | |
1019 | &dev_attr_serial.attr, | |
1020 | NULL, | |
1021 | }; | |
1022 | ||
1023 | /** | |
1024 | * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. | |
1025 | */ | |
1026 | static const struct attribute_group | |
1027 | ds1685_rtc_sysfs_misc_grp = { | |
1028 | .name = "misc", | |
1029 | .attrs = ds1685_rtc_sysfs_misc_attrs, | |
1030 | }; | |
1031 | ||
aaaf5fbf JK |
1032 | /* ----------------------------------------------------------------------- */ |
1033 | /* Driver Probe/Removal */ | |
1034 | ||
1035 | /** | |
1036 | * ds1685_rtc_probe - initializes rtc driver. | |
1037 | * @pdev: pointer to platform_device structure. | |
1038 | */ | |
1039 | static int | |
1040 | ds1685_rtc_probe(struct platform_device *pdev) | |
1041 | { | |
1042 | struct rtc_device *rtc_dev; | |
1043 | struct resource *res; | |
1044 | struct ds1685_priv *rtc; | |
1045 | struct ds1685_rtc_platform_data *pdata; | |
1046 | u8 ctrla, ctrlb, hours; | |
1047 | unsigned char am_pm; | |
1048 | int ret = 0; | |
482419e1 AB |
1049 | struct nvmem_config nvmem_cfg = { |
1050 | .name = "ds1685_nvram", | |
1051 | .size = NVRAM_TOTAL_SZ, | |
1052 | .reg_read = ds1685_nvram_read, | |
1053 | .reg_write = ds1685_nvram_write, | |
1054 | }; | |
aaaf5fbf JK |
1055 | |
1056 | /* Get the platform data. */ | |
1057 | pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; | |
1058 | if (!pdata) | |
1059 | return -ENODEV; | |
1060 | ||
1061 | /* Allocate memory for the rtc device. */ | |
1062 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); | |
1063 | if (!rtc) | |
1064 | return -ENOMEM; | |
1065 | ||
1066 | /* | |
1067 | * Allocate/setup any IORESOURCE_MEM resources, if required. Not all | |
1068 | * platforms put the RTC in an easy-access place. Like the SGI Octane, | |
1069 | * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip | |
1070 | * that sits behind the IOC3 PCI metadevice. | |
1071 | */ | |
1072 | if (pdata->alloc_io_resources) { | |
1073 | /* Get the platform resources. */ | |
1074 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1075 | if (!res) | |
1076 | return -ENXIO; | |
1077 | rtc->size = resource_size(res); | |
1078 | ||
1079 | /* Request a memory region. */ | |
1080 | /* XXX: mmio-only for now. */ | |
1081 | if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size, | |
1082 | pdev->name)) | |
1083 | return -EBUSY; | |
1084 | ||
1085 | /* | |
1086 | * Set the base address for the rtc, and ioremap its | |
1087 | * registers. | |
1088 | */ | |
1089 | rtc->baseaddr = res->start; | |
1090 | rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size); | |
1091 | if (!rtc->regs) | |
1092 | return -ENOMEM; | |
1093 | } | |
1094 | rtc->alloc_io_resources = pdata->alloc_io_resources; | |
1095 | ||
1096 | /* Get the register step size. */ | |
1097 | if (pdata->regstep > 0) | |
1098 | rtc->regstep = pdata->regstep; | |
1099 | else | |
1100 | rtc->regstep = 1; | |
1101 | ||
1102 | /* Platform read function, else default if mmio setup */ | |
1103 | if (pdata->plat_read) | |
1104 | rtc->read = pdata->plat_read; | |
1105 | else | |
1106 | if (pdata->alloc_io_resources) | |
1107 | rtc->read = ds1685_read; | |
1108 | else | |
1109 | return -ENXIO; | |
1110 | ||
1111 | /* Platform write function, else default if mmio setup */ | |
1112 | if (pdata->plat_write) | |
1113 | rtc->write = pdata->plat_write; | |
1114 | else | |
1115 | if (pdata->alloc_io_resources) | |
1116 | rtc->write = ds1685_write; | |
1117 | else | |
1118 | return -ENXIO; | |
1119 | ||
1120 | /* Platform pre-shutdown function, if defined. */ | |
1121 | if (pdata->plat_prepare_poweroff) | |
1122 | rtc->prepare_poweroff = pdata->plat_prepare_poweroff; | |
1123 | ||
1124 | /* Platform wake_alarm function, if defined. */ | |
1125 | if (pdata->plat_wake_alarm) | |
1126 | rtc->wake_alarm = pdata->plat_wake_alarm; | |
1127 | ||
1128 | /* Platform post_ram_clear function, if defined. */ | |
1129 | if (pdata->plat_post_ram_clear) | |
1130 | rtc->post_ram_clear = pdata->plat_post_ram_clear; | |
1131 | ||
3b6bddda | 1132 | /* set the driver data. */ |
aaaf5fbf JK |
1133 | platform_set_drvdata(pdev, rtc); |
1134 | ||
1135 | /* Turn the oscillator on if is not already on (DV1 = 1). */ | |
1136 | ctrla = rtc->read(rtc, RTC_CTRL_A); | |
1137 | if (!(ctrla & RTC_CTRL_A_DV1)) | |
1138 | ctrla |= RTC_CTRL_A_DV1; | |
1139 | ||
1140 | /* Enable the countdown chain (DV2 = 0) */ | |
1141 | ctrla &= ~(RTC_CTRL_A_DV2); | |
1142 | ||
1143 | /* Clear RS3-RS0 in Control A. */ | |
1144 | ctrla &= ~(RTC_CTRL_A_RS_MASK); | |
1145 | ||
1146 | /* | |
1147 | * All done with Control A. Switch to Bank 1 for the remainder of | |
1148 | * the RTC setup so we have access to the extended functions. | |
1149 | */ | |
1150 | ctrla |= RTC_CTRL_A_DV0; | |
1151 | rtc->write(rtc, RTC_CTRL_A, ctrla); | |
1152 | ||
1153 | /* Default to 32768kHz output. */ | |
1154 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
1155 | (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); | |
1156 | ||
1157 | /* Set the SET bit in Control B so we can do some housekeeping. */ | |
1158 | rtc->write(rtc, RTC_CTRL_B, | |
1159 | (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); | |
1160 | ||
1161 | /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ | |
1162 | while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) | |
1163 | cpu_relax(); | |
1164 | ||
1165 | /* | |
1166 | * If the platform supports BCD mode, then set DM=0 in Control B. | |
1167 | * Otherwise, set DM=1 for BIN mode. | |
1168 | */ | |
1169 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
1170 | if (pdata->bcd_mode) | |
1171 | ctrlb &= ~(RTC_CTRL_B_DM); | |
1172 | else | |
1173 | ctrlb |= RTC_CTRL_B_DM; | |
1174 | rtc->bcd_mode = pdata->bcd_mode; | |
1175 | ||
1176 | /* | |
1177 | * Disable Daylight Savings Time (DSE = 0). | |
1178 | * The RTC has hardcoded timezone information that is rendered | |
1179 | * obselete. We'll let the OS deal with DST settings instead. | |
1180 | */ | |
1181 | if (ctrlb & RTC_CTRL_B_DSE) | |
1182 | ctrlb &= ~(RTC_CTRL_B_DSE); | |
1183 | ||
1184 | /* Force 24-hour mode (2412 = 1). */ | |
1185 | if (!(ctrlb & RTC_CTRL_B_2412)) { | |
1186 | /* Reinitialize the time hours. */ | |
1187 | hours = rtc->read(rtc, RTC_HRS); | |
1188 | am_pm = hours & RTC_HRS_AMPM_MASK; | |
1189 | hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, | |
1190 | RTC_HRS_12_BIN_MASK); | |
1191 | hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); | |
1192 | ||
1193 | /* Enable 24-hour mode. */ | |
1194 | ctrlb |= RTC_CTRL_B_2412; | |
1195 | ||
1196 | /* Write back to Control B, including DM & DSE bits. */ | |
1197 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
1198 | ||
1199 | /* Write the time hours back. */ | |
1200 | rtc->write(rtc, RTC_HRS, | |
1201 | ds1685_rtc_bin2bcd(rtc, hours, | |
1202 | RTC_HRS_24_BIN_MASK, | |
1203 | RTC_HRS_24_BCD_MASK)); | |
1204 | ||
1205 | /* Reinitialize the alarm hours. */ | |
1206 | hours = rtc->read(rtc, RTC_HRS_ALARM); | |
1207 | am_pm = hours & RTC_HRS_AMPM_MASK; | |
1208 | hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, | |
1209 | RTC_HRS_12_BIN_MASK); | |
1210 | hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); | |
1211 | ||
1212 | /* Write the alarm hours back. */ | |
1213 | rtc->write(rtc, RTC_HRS_ALARM, | |
1214 | ds1685_rtc_bin2bcd(rtc, hours, | |
1215 | RTC_HRS_24_BIN_MASK, | |
1216 | RTC_HRS_24_BCD_MASK)); | |
1217 | } else { | |
1218 | /* 24-hour mode is already set, so write Control B back. */ | |
1219 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
1220 | } | |
1221 | ||
1222 | /* Unset the SET bit in Control B so the RTC can update. */ | |
1223 | rtc->write(rtc, RTC_CTRL_B, | |
1224 | (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); | |
1225 | ||
1226 | /* Check the main battery. */ | |
1227 | if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) | |
1228 | dev_warn(&pdev->dev, | |
1229 | "Main battery is exhausted! RTC may be invalid!\n"); | |
1230 | ||
1231 | /* Check the auxillary battery. It is optional. */ | |
1232 | if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) | |
1233 | dev_warn(&pdev->dev, | |
1234 | "Aux battery is exhausted or not available.\n"); | |
1235 | ||
1236 | /* Read Ctrl B and clear PIE/AIE/UIE. */ | |
1237 | rtc->write(rtc, RTC_CTRL_B, | |
1238 | (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK))); | |
1239 | ||
1240 | /* Reading Ctrl C auto-clears PF/AF/UF. */ | |
1241 | rtc->read(rtc, RTC_CTRL_C); | |
1242 | ||
1243 | /* Read Ctrl 4B and clear RIE/WIE/KSE. */ | |
1244 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
1245 | (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK))); | |
1246 | ||
1247 | /* Clear RF/WF/KF in Ctrl 4A. */ | |
1248 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
1249 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK))); | |
1250 | ||
1251 | /* | |
1252 | * Re-enable KSE to handle power button events. We do not enable | |
1253 | * WIE or RIE by default. | |
1254 | */ | |
1255 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
1256 | (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE)); | |
1257 | ||
a2ae8323 AB |
1258 | rtc_dev = devm_rtc_allocate_device(&pdev->dev); |
1259 | if (IS_ERR(rtc_dev)) | |
1260 | return PTR_ERR(rtc_dev); | |
1261 | ||
1262 | rtc_dev->ops = &ds1685_rtc_ops; | |
1263 | ||
c36b52ed AB |
1264 | /* Century bit is useless because leap year fails in 1900 and 2100 */ |
1265 | rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; | |
1266 | rtc_dev->range_max = RTC_TIMESTAMP_END_2099; | |
1267 | ||
a2ae8323 AB |
1268 | /* Maximum periodic rate is 8192Hz (0.122070ms). */ |
1269 | rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; | |
1270 | ||
1271 | /* See if the platform doesn't support UIE. */ | |
1272 | if (pdata->uie_unsupported) | |
1273 | rtc_dev->uie_unsupported = 1; | |
1274 | rtc->uie_unsupported = pdata->uie_unsupported; | |
1275 | ||
1276 | rtc->dev = rtc_dev; | |
1277 | ||
aaaf5fbf JK |
1278 | /* |
1279 | * Fetch the IRQ and setup the interrupt handler. | |
1280 | * | |
1281 | * Not all platforms have the IRQF pin tied to something. If not, the | |
1282 | * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but | |
1283 | * there won't be an automatic way of notifying the kernel about it, | |
1284 | * unless ctrlc is explicitly polled. | |
1285 | */ | |
1286 | if (!pdata->no_irq) { | |
1287 | ret = platform_get_irq(pdev, 0); | |
3b6bddda | 1288 | if (ret <= 0) |
aaaf5fbf | 1289 | return ret; |
3b6bddda TB |
1290 | |
1291 | rtc->irq_num = ret; | |
1292 | ||
1293 | /* Request an IRQ. */ | |
1294 | ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num, | |
1295 | NULL, ds1685_rtc_irq_handler, | |
1296 | IRQF_SHARED | IRQF_ONESHOT, | |
1297 | pdev->name, pdev); | |
1298 | ||
1299 | /* Check to see if something came back. */ | |
1300 | if (unlikely(ret)) { | |
1301 | dev_warn(&pdev->dev, | |
1302 | "RTC interrupt not available\n"); | |
1303 | rtc->irq_num = 0; | |
1304 | } | |
aaaf5fbf JK |
1305 | } |
1306 | rtc->no_irq = pdata->no_irq; | |
1307 | ||
1308 | /* Setup complete. */ | |
1309 | ds1685_rtc_switch_to_bank0(rtc); | |
1310 | ||
cfb74916 | 1311 | ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp); |
aaaf5fbf | 1312 | if (ret) |
a2ae8323 | 1313 | return ret; |
aaaf5fbf | 1314 | |
482419e1 AB |
1315 | rtc_dev->nvram_old_abi = true; |
1316 | nvmem_cfg.priv = rtc; | |
1317 | ret = rtc_nvmem_register(rtc_dev, &nvmem_cfg); | |
1318 | if (ret) | |
1319 | return ret; | |
1320 | ||
a2ae8323 | 1321 | return rtc_register_device(rtc_dev); |
aaaf5fbf JK |
1322 | } |
1323 | ||
1324 | /** | |
1325 | * ds1685_rtc_remove - removes rtc driver. | |
1326 | * @pdev: pointer to platform_device structure. | |
1327 | */ | |
1328 | static int | |
1329 | ds1685_rtc_remove(struct platform_device *pdev) | |
1330 | { | |
1331 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
1332 | ||
aaaf5fbf JK |
1333 | /* Read Ctrl B and clear PIE/AIE/UIE. */ |
1334 | rtc->write(rtc, RTC_CTRL_B, | |
1335 | (rtc->read(rtc, RTC_CTRL_B) & | |
1336 | ~(RTC_CTRL_B_PAU_MASK))); | |
1337 | ||
1338 | /* Reading Ctrl C auto-clears PF/AF/UF. */ | |
1339 | rtc->read(rtc, RTC_CTRL_C); | |
1340 | ||
1341 | /* Read Ctrl 4B and clear RIE/WIE/KSE. */ | |
1342 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
1343 | (rtc->read(rtc, RTC_EXT_CTRL_4B) & | |
1344 | ~(RTC_CTRL_4B_RWK_MASK))); | |
1345 | ||
1346 | /* Manually clear RF/WF/KF in Ctrl 4A. */ | |
1347 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
1348 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & | |
1349 | ~(RTC_CTRL_4A_RWK_MASK))); | |
1350 | ||
aaaf5fbf JK |
1351 | return 0; |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * ds1685_rtc_driver - rtc driver properties. | |
1356 | */ | |
1357 | static struct platform_driver ds1685_rtc_driver = { | |
1358 | .driver = { | |
1359 | .name = "rtc-ds1685", | |
aaaf5fbf JK |
1360 | }, |
1361 | .probe = ds1685_rtc_probe, | |
1362 | .remove = ds1685_rtc_remove, | |
1363 | }; | |
508db592 | 1364 | module_platform_driver(ds1685_rtc_driver); |
aaaf5fbf JK |
1365 | /* ----------------------------------------------------------------------- */ |
1366 | ||
1367 | ||
1368 | /* ----------------------------------------------------------------------- */ | |
1369 | /* Poweroff function */ | |
1370 | ||
1371 | /** | |
1372 | * ds1685_rtc_poweroff - uses the RTC chip to power the system off. | |
1373 | * @pdev: pointer to platform_device structure. | |
1374 | */ | |
52ef84d5 | 1375 | void __noreturn |
aaaf5fbf JK |
1376 | ds1685_rtc_poweroff(struct platform_device *pdev) |
1377 | { | |
1378 | u8 ctrla, ctrl4a, ctrl4b; | |
1379 | struct ds1685_priv *rtc; | |
1380 | ||
1381 | /* Check for valid RTC data, else, spin forever. */ | |
1382 | if (unlikely(!pdev)) { | |
a737e835 | 1383 | pr_emerg("platform device data not available, spinning forever ...\n"); |
361c6ed6 | 1384 | while(1); |
aaaf5fbf JK |
1385 | unreachable(); |
1386 | } else { | |
1387 | /* Get the rtc data. */ | |
1388 | rtc = platform_get_drvdata(pdev); | |
1389 | ||
1390 | /* | |
1391 | * Disable our IRQ. We're powering down, so we're not | |
1392 | * going to worry about cleaning up. Most of that should | |
1393 | * have been taken care of by the shutdown scripts and this | |
1394 | * is the final function call. | |
1395 | */ | |
1396 | if (!rtc->no_irq) | |
1397 | disable_irq_nosync(rtc->irq_num); | |
1398 | ||
1399 | /* Oscillator must be on and the countdown chain enabled. */ | |
1400 | ctrla = rtc->read(rtc, RTC_CTRL_A); | |
1401 | ctrla |= RTC_CTRL_A_DV1; | |
1402 | ctrla &= ~(RTC_CTRL_A_DV2); | |
1403 | rtc->write(rtc, RTC_CTRL_A, ctrla); | |
1404 | ||
1405 | /* | |
1406 | * Read Control 4A and check the status of the auxillary | |
1407 | * battery. This must be present and working (VRT2 = 1) | |
1408 | * for wakeup and kickstart functionality to be useful. | |
1409 | */ | |
1410 | ds1685_rtc_switch_to_bank1(rtc); | |
1411 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
1412 | if (ctrl4a & RTC_CTRL_4A_VRT2) { | |
1413 | /* Clear all of the interrupt flags on Control 4A. */ | |
1414 | ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); | |
1415 | rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a); | |
1416 | ||
1417 | /* | |
1418 | * The auxillary battery is present and working. | |
1419 | * Enable extended functions (ABE=1), enable | |
1420 | * wake-up (WIE=1), and enable kickstart (KSE=1) | |
1421 | * in Control 4B. | |
1422 | */ | |
1423 | ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); | |
1424 | ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | | |
1425 | RTC_CTRL_4B_KSE); | |
1426 | rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b); | |
1427 | } | |
1428 | ||
1429 | /* Set PAB to 1 in Control 4A to power the system down. */ | |
1430 | dev_warn(&pdev->dev, "Powerdown.\n"); | |
1431 | msleep(20); | |
1432 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
1433 | (ctrl4a | RTC_CTRL_4A_PAB)); | |
1434 | ||
1435 | /* Spin ... we do not switch back to bank0. */ | |
19105f42 | 1436 | while(1); |
aaaf5fbf JK |
1437 | unreachable(); |
1438 | } | |
1439 | } | |
1440 | EXPORT_SYMBOL(ds1685_rtc_poweroff); | |
1441 | /* ----------------------------------------------------------------------- */ | |
1442 | ||
1443 | ||
1444 | MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>"); | |
1445 | MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>"); | |
1446 | MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); | |
1447 | MODULE_LICENSE("GPL"); | |
aaaf5fbf | 1448 | MODULE_ALIAS("platform:rtc-ds1685"); |