[mirror_ubuntu-jammy-kernel.git] / drivers / rtc / rtc-jz4740.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
 *	 JZ4740 SoC RTC driver
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/reboot.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define JZ_REG_RTC_CTRL		0x00
#define JZ_REG_RTC_SEC		0x04
#define JZ_REG_RTC_SEC_ALARM	0x08
#define JZ_REG_RTC_REGULATOR	0x0C
#define JZ_REG_RTC_HIBERNATE	0x20
#define JZ_REG_RTC_WAKEUP_FILTER	0x24
#define JZ_REG_RTC_RESET_COUNTER	0x28
#define JZ_REG_RTC_SCRATCHPAD	0x34

/* The following are present on the jz4780 */
#define JZ_REG_RTC_WENR	0x3C
#define JZ_RTC_WENR_WEN	BIT(31)

#define JZ_RTC_CTRL_WRDY	BIT(7)
#define JZ_RTC_CTRL_1HZ		BIT(6)
#define JZ_RTC_CTRL_1HZ_IRQ	BIT(5)
#define JZ_RTC_CTRL_AF		BIT(4)
#define JZ_RTC_CTRL_AF_IRQ	BIT(3)
#define JZ_RTC_CTRL_AE		BIT(2)
#define JZ_RTC_CTRL_ENABLE	BIT(0)

/* Magic value to enable writes on jz4780 */
#define JZ_RTC_WENR_MAGIC	0xA55A

#define JZ_RTC_WAKEUP_FILTER_MASK	0x0000FFE0
#define JZ_RTC_RESET_COUNTER_MASK	0x00000FE0

enum jz4740_rtc_type {
	ID_JZ4740,
	ID_JZ4760,
	ID_JZ4780,
};

struct jz4740_rtc {
	void __iomem *base;
	enum jz4740_rtc_type type;

	struct rtc_device *rtc;

	spinlock_t lock;
};

static struct device *dev_for_power_off;

static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
{
	return readl(rtc->base + reg);
}

static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
{
	uint32_t ctrl;
	int timeout = 10000;

	do {
		ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);

	return timeout ? 0 : -EIO;
}

static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
{
	uint32_t ctrl;
	int ret, timeout = 10000;

	ret = jz4740_rtc_wait_write_ready(rtc);
	if (ret != 0)
		return ret;

	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);

	do {
		ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
	} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);

	return timeout ? 0 : -EIO;
}

static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
	uint32_t val)
{
	int ret = 0;

	if (rtc->type >= ID_JZ4760)
		ret = jz4780_rtc_enable_write(rtc);
	if (ret == 0)
		ret = jz4740_rtc_wait_write_ready(rtc);
	if (ret == 0)
		writel(val, rtc->base + reg);

	return ret;
}

static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
	bool set)
{
	int ret;
	unsigned long flags;
	uint32_t ctrl;

	spin_lock_irqsave(&rtc->lock, flags);

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	/* Don't clear interrupt flags by accident */
	ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;

	if (set)
		ctrl |= mask;
	else
		ctrl &= ~mask;

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);

	spin_unlock_irqrestore(&rtc->lock, flags);

	return ret;
}

static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs, secs2;
	int timeout = 5;

	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
		return -EINVAL;

	/* If the seconds register is read while it is updated, it can contain a
	 * bogus value. This can be avoided by making sure that two consecutive
	 * reads have the same value.
	 */
	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);

	while (secs != secs2 && --timeout) {
		secs = secs2;
		secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	}

	if (timeout == 0)
		return -EIO;

	rtc_time64_to_tm(secs, time);

	return 0;
}

static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	int ret;

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
	if (ret)
		return ret;

	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
}

static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs;
	uint32_t ctrl;

	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);

	rtc_time64_to_tm(secs, &alrm->time);

	return 0;
}

static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int ret;
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
	if (!ret)
		ret = jz4740_rtc_ctrl_set_bits(rtc,
			JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);

	return ret;
}

static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
}

static const struct rtc_class_ops jz4740_rtc_ops = {
	.read_time	= jz4740_rtc_read_time,
	.set_time	= jz4740_rtc_set_time,
	.read_alarm	= jz4740_rtc_read_alarm,
	.set_alarm	= jz4740_rtc_set_alarm,
	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
};

static irqreturn_t jz4740_rtc_irq(int irq, void *data)
{
	struct jz4740_rtc *rtc = data;
	uint32_t ctrl;
	unsigned long events = 0;

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	if (ctrl & JZ_RTC_CTRL_1HZ)
		events |= (RTC_UF | RTC_IRQF);

	if (ctrl & JZ_RTC_CTRL_AF)
		events |= (RTC_AF | RTC_IRQF);

	rtc_update_irq(rtc->rtc, 1, events);

	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);

	return IRQ_HANDLED;
}

static void jz4740_rtc_poweroff(struct device *dev)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
}

static void jz4740_rtc_power_off(void)
{
	jz4740_rtc_poweroff(dev_for_power_off);
	kernel_halt();
}

static void jz4740_rtc_clk_disable(void *data)
{
	clk_disable_unprepare(data);
}

static const struct of_device_id jz4740_rtc_of_match[] = {
	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
	{},
};
MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);

static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
					 struct device_node *np,
					 unsigned long rate)
{
	unsigned long wakeup_ticks, reset_ticks;
	unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
	unsigned int reset_pin_assert_time = 100; /* Default: 100ms */

	of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
			     &reset_pin_assert_time);
	of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
			     &min_wakeup_pin_assert_time);

	/*
	 * Set minimum wakeup pin assertion time: 100 ms.
	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
	 */
	wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
	if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
		wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
	else
		wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);

	/*
	 * Set reset pin low-level assertion time after wakeup: 60 ms.
	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
	 */
	reset_ticks = (reset_pin_assert_time * rate) / 1000;
	if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
		reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
	else
		reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
}

static int jz4740_rtc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct jz4740_rtc *rtc;
	unsigned long rate;
	struct clk *clk;
	int ret, irq;

	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	rtc->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(rtc->base))
		return PTR_ERR(rtc->base);

	clk = devm_clk_get(dev, "rtc");
	if (IS_ERR(clk)) {
		dev_err(dev, "Failed to get RTC clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		dev_err(dev, "Failed to enable clock\n");
		return ret;
	}

	ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
	if (ret) {
		dev_err(dev, "Failed to register devm action\n");
		return ret;
	}

	spin_lock_init(&rtc->lock);

	platform_set_drvdata(pdev, rtc);

	device_init_wakeup(dev, 1);

	ret = dev_pm_set_wake_irq(dev, irq);
	if (ret) {
		dev_err(dev, "Failed to set wake irq: %d\n", ret);
		return ret;
	}

	rtc->rtc = devm_rtc_allocate_device(dev);
	if (IS_ERR(rtc->rtc)) {
		ret = PTR_ERR(rtc->rtc);
		dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
		return ret;
	}

	rtc->rtc->ops = &jz4740_rtc_ops;
	rtc->rtc->range_max = U32_MAX;

	rate = clk_get_rate(clk);
	jz4740_rtc_set_wakeup_params(rtc, np, rate);

	/* Each 1 Hz pulse should happen after (rate) ticks */
	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);

	ret = devm_rtc_register_device(rtc->rtc);
	if (ret)
		return ret;

	ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
			       pdev->name, rtc);
	if (ret) {
		dev_err(dev, "Failed to request rtc irq: %d\n", ret);
		return ret;
	}

	if (of_device_is_system_power_controller(np)) {
		dev_for_power_off = dev;

		if (!pm_power_off)
			pm_power_off = jz4740_rtc_power_off;
		else
			dev_warn(dev, "Poweroff handler already present!\n");
	}

	return 0;
}

static struct platform_driver jz4740_rtc_driver = {
	.probe	 = jz4740_rtc_probe,
	.driver	 = {
		.name  = "jz4740-rtc",
		.of_match_table = jz4740_rtc_of_match,
	},
};

module_platform_driver(jz4740_rtc_driver);

MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
MODULE_ALIAS("platform:jz4740-rtc");
Commit	Line	Data
86836d64	1	// SPDX-License-Identifier: GPL-2.0+
3bf0eea8 LPC	2	/*
3bf0eea8 LPC	3	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
d0f744c8	4	* Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
3bf0eea8	5	* JZ4740 SoC RTC driver
3bf0eea8 LPC	6	*/
3bf0eea8 LPC	7
f9eb69d1	8	#include <linux/clk.h>
c08ac489	9	#include <linux/io.h>
3bf0eea8	10	#include <linux/kernel.h>
586655d2	11	#include <linux/module.h>
c05229a8	12	#include <linux/of_device.h>
3bf0eea8	13	#include <linux/platform_device.h>
3b2dc19f	14	#include <linux/pm_wakeirq.h>
f9eb69d1	15	#include <linux/reboot.h>
3bf0eea8 LPC	16	#include <linux/rtc.h>
	17	#include <linux/slab.h>
	18	#include <linux/spinlock.h>
	19
	20	#define JZ_REG_RTC_CTRL 0x00
	21	#define JZ_REG_RTC_SEC 0x04
	22	#define JZ_REG_RTC_SEC_ALARM 0x08
	23	#define JZ_REG_RTC_REGULATOR 0x0C
	24	#define JZ_REG_RTC_HIBERNATE 0x20
f9eb69d1 PC	25	#define JZ_REG_RTC_WAKEUP_FILTER 0x24
f9eb69d1 PC	26	#define JZ_REG_RTC_RESET_COUNTER 0x28
3bf0eea8 LPC	27	#define JZ_REG_RTC_SCRATCHPAD 0x34
3bf0eea8 LPC	28
cd563200 PC	29	/* The following are present on the jz4780 */
	30	#define JZ_REG_RTC_WENR 0x3C
	31	#define JZ_RTC_WENR_WEN BIT(31)
	32
3bf0eea8 LPC	33	#define JZ_RTC_CTRL_WRDY BIT(7)
	34	#define JZ_RTC_CTRL_1HZ BIT(6)
	35	#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
	36	#define JZ_RTC_CTRL_AF BIT(4)
	37	#define JZ_RTC_CTRL_AF_IRQ BIT(3)
	38	#define JZ_RTC_CTRL_AE BIT(2)
	39	#define JZ_RTC_CTRL_ENABLE BIT(0)
	40
cd563200 PC	41	/* Magic value to enable writes on jz4780 */
	42	#define JZ_RTC_WENR_MAGIC 0xA55A
	43
f9eb69d1 PC	44	#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
	45	#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
	46
cd563200 PC	47	enum jz4740_rtc_type {
cd563200 PC	48	ID_JZ4740,
58407485	49	ID_JZ4760,
cd563200 PC	50	ID_JZ4780,
	51	};
	52
3bf0eea8	53	struct jz4740_rtc {
3bf0eea8	54	void __iomem *base;
cd563200	55	enum jz4740_rtc_type type;
3bf0eea8 LPC	56
3bf0eea8 LPC	57	struct rtc_device *rtc;
3bf0eea8 LPC	58
	59	spinlock_t lock;
	60	};
	61
f9eb69d1 PC	62	static struct device *dev_for_power_off;
f9eb69d1 PC	63
3bf0eea8 LPC	64	static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
	65	{
	66	return readl(rtc->base + reg);
	67	}
	68
	69	static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
	70	{
	71	uint32_t ctrl;
695e38d8	72	int timeout = 10000;
3bf0eea8 LPC	73
	74	do {
	75	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	76	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
	77
	78	return timeout ? 0 : -EIO;
	79	}
	80
cd563200 PC	81	static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
	82	{
	83	uint32_t ctrl;
695e38d8	84	int ret, timeout = 10000;
cd563200 PC	85
	86	ret = jz4740_rtc_wait_write_ready(rtc);
	87	if (ret != 0)
	88	return ret;
	89
	90	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
	91
	92	do {
	93	ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
	94	} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
	95
	96	return timeout ? 0 : -EIO;
	97	}
	98
3bf0eea8 LPC	99	static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
	100	uint32_t val)
	101	{
cd563200 PC	102	int ret = 0;
cd563200 PC	103
58407485	104	if (rtc->type >= ID_JZ4760)
cd563200 PC	105	ret = jz4780_rtc_enable_write(rtc);
	106	if (ret == 0)
	107	ret = jz4740_rtc_wait_write_ready(rtc);
3bf0eea8 LPC	108	if (ret == 0)
	109	writel(val, rtc->base + reg);
	110
	111	return ret;
	112	}
	113
	114	static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
	115	bool set)
	116	{
	117	int ret;
	118	unsigned long flags;
	119	uint32_t ctrl;
	120
	121	spin_lock_irqsave(&rtc->lock, flags);
	122
	123	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	124
	125	/* Don't clear interrupt flags by accident */
	126	ctrl \|= JZ_RTC_CTRL_1HZ \| JZ_RTC_CTRL_AF;
	127
	128	if (set)
	129	ctrl \|= mask;
	130	else
	131	ctrl &= ~mask;
	132
	133	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
	134
	135	spin_unlock_irqrestore(&rtc->lock, flags);
	136
	137	return ret;
	138	}
	139
	140	static int jz4740_rtc_read_time(struct device dev, struct rtc_time time)
	141	{
	142	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	143	uint32_t secs, secs2;
	144	int timeout = 5;
	145
7fe8fcee AB	146	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
	147	return -EINVAL;
	148
3bf0eea8 LPC	149	/* If the seconds register is read while it is updated, it can contain a
	150	* bogus value. This can be avoided by making sure that two consecutive
	151	* reads have the same value.
	152	*/
	153	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	154	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	155
	156	while (secs != secs2 && --timeout) {
	157	secs = secs2;
	158	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	159	}
	160
	161	if (timeout == 0)
	162	return -EIO;
	163
be8dce96	164	rtc_time64_to_tm(secs, time);
3bf0eea8	165
ab62670e	166	return 0;
3bf0eea8 LPC	167	}
3bf0eea8 LPC	168
e72746e7	169	static int jz4740_rtc_set_time(struct device dev, struct rtc_time time)
3bf0eea8 LPC	170	{
3bf0eea8 LPC	171	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
7fe8fcee AB	172	int ret;
	173
	174	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
	175	if (ret)
	176	return ret;
3bf0eea8	177
7fe8fcee	178	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
3bf0eea8 LPC	179	}
	180
	181	static int jz4740_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	182	{
	183	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	184	uint32_t secs;
	185	uint32_t ctrl;
	186
	187	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
	188
	189	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	190
	191	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
	192	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
	193
be8dce96	194	rtc_time64_to_tm(secs, &alrm->time);
3bf0eea8	195
d10dcc95	196	return 0;
3bf0eea8 LPC	197	}
	198
	199	static int jz4740_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	200	{
	201	int ret;
	202	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
be8dce96	203	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
3bf0eea8 LPC	204
	205	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
	206	if (!ret)
d0f744c8 PC	207	ret = jz4740_rtc_ctrl_set_bits(rtc,
d0f744c8 PC	208	JZ_RTC_CTRL_AE \| JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
3bf0eea8 LPC	209
	210	return ret;
	211	}
	212
3bf0eea8 LPC	213	static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	214	{
	215	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	216	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
	217	}
	218
34c7b3ac	219	static const struct rtc_class_ops jz4740_rtc_ops = {
3bf0eea8	220	.read_time = jz4740_rtc_read_time,
e72746e7	221	.set_time = jz4740_rtc_set_time,
3bf0eea8 LPC	222	.read_alarm = jz4740_rtc_read_alarm,
3bf0eea8 LPC	223	.set_alarm = jz4740_rtc_set_alarm,
3bf0eea8 LPC	224	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
	225	};
	226
	227	static irqreturn_t jz4740_rtc_irq(int irq, void *data)
	228	{
	229	struct jz4740_rtc *rtc = data;
	230	uint32_t ctrl;
	231	unsigned long events = 0;
	232
	233	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	234
	235	if (ctrl & JZ_RTC_CTRL_1HZ)
	236	events \|= (RTC_UF \| RTC_IRQF);
	237
	238	if (ctrl & JZ_RTC_CTRL_AF)
	239	events \|= (RTC_AF \| RTC_IRQF);
	240
	241	rtc_update_irq(rtc->rtc, 1, events);
	242
	243	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ \| JZ_RTC_CTRL_AF, false);
	244
	245	return IRQ_HANDLED;
	246	}
	247
819c2178	248	static void jz4740_rtc_poweroff(struct device *dev)
3bf0eea8 LPC	249	{
	250	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	251	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
	252	}
3bf0eea8	253
f9eb69d1 PC	254	static void jz4740_rtc_power_off(void)
f9eb69d1 PC	255	{
f9eb69d1	256	jz4740_rtc_poweroff(dev_for_power_off);
586655d2	257	kernel_halt();
f9eb69d1 PC	258	}
f9eb69d1 PC	259
796be8b5 PC	260	static void jz4740_rtc_clk_disable(void *data)
	261	{
	262	clk_disable_unprepare(data);
	263	}
	264
c05229a8 PC	265	static const struct of_device_id jz4740_rtc_of_match[] = {
c05229a8 PC	266	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
58407485	267	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
c05229a8 PC	268	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
	269	{},
	270	};
586655d2	271	MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
c05229a8	272
fe0557f4 PC	273	static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
	274	struct device_node *np,
	275	unsigned long rate)
	276	{
	277	unsigned long wakeup_ticks, reset_ticks;
	278	unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
	279	unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
	280
	281	of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
	282	&reset_pin_assert_time);
	283	of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
	284	&min_wakeup_pin_assert_time);
	285
	286	/*
	287	* Set minimum wakeup pin assertion time: 100 ms.
	288	* Range is 0 to 2 sec if RTC is clocked at 32 kHz.
	289	*/
	290	wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
	291	if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
	292	wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
	293	else
	294	wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
	295	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
	296
	297	/*
	298	* Set reset pin low-level assertion time after wakeup: 60 ms.
	299	* Range is 0 to 125 ms if RTC is clocked at 32 kHz.
	300	*/
	301	reset_ticks = (reset_pin_assert_time * rate) / 1000;
	302	if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
	303	reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
	304	else
	305	reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
	306	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
	307	}
	308
5a167f45	309	static int jz4740_rtc_probe(struct platform_device *pdev)
3bf0eea8	310	{
c61293f1 PC	311	struct device *dev = &pdev->dev;
c61293f1 PC	312	struct device_node *np = dev->of_node;
3bf0eea8	313	struct jz4740_rtc *rtc;
fe0557f4	314	unsigned long rate;
77d8f3c1 PC	315	struct clk *clk;
77d8f3c1 PC	316	int ret, irq;
3bf0eea8	317
c61293f1	318	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
3bf0eea8 LPC	319	if (!rtc)
	320	return -ENOMEM;
	321
24e1f2c9	322	rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
cd563200	323
77d8f3c1 PC	324	irq = platform_get_irq(pdev, 0);
77d8f3c1 PC	325	if (irq < 0)
15eeadd8	326	return irq;
3bf0eea8	327
09ef18bc	328	rtc->base = devm_platform_ioremap_resource(pdev, 0);
3b6aa907 JH	329	if (IS_ERR(rtc->base))
3b6aa907 JH	330	return PTR_ERR(rtc->base);
3bf0eea8	331
77d8f3c1 PC	332	clk = devm_clk_get(dev, "rtc");
77d8f3c1 PC	333	if (IS_ERR(clk)) {
c61293f1	334	dev_err(dev, "Failed to get RTC clock\n");
77d8f3c1	335	return PTR_ERR(clk);
f9eb69d1 PC	336	}
f9eb69d1 PC	337
77d8f3c1	338	ret = clk_prepare_enable(clk);
796be8b5 PC	339	if (ret) {
	340	dev_err(dev, "Failed to enable clock\n");
	341	return ret;
	342	}
	343
77d8f3c1	344	ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
796be8b5 PC	345	if (ret) {
	346	dev_err(dev, "Failed to register devm action\n");
	347	return ret;
	348	}
	349
3bf0eea8 LPC	350	spin_lock_init(&rtc->lock);
	351
	352	platform_set_drvdata(pdev, rtc);
	353
c61293f1	354	device_init_wakeup(dev, 1);
d0f744c8	355
77d8f3c1	356	ret = dev_pm_set_wake_irq(dev, irq);
3b2dc19f	357	if (ret) {
c61293f1	358	dev_err(dev, "Failed to set wake irq: %d\n", ret);
3b2dc19f AB	359	return ret;
	360	}
	361
c61293f1	362	rtc->rtc = devm_rtc_allocate_device(dev);
3bf0eea8 LPC	363	if (IS_ERR(rtc->rtc)) {
3bf0eea8 LPC	364	ret = PTR_ERR(rtc->rtc);
c61293f1	365	dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
a7ab6bed AB	366	return ret;
	367	}
	368
	369	rtc->rtc->ops = &jz4740_rtc_ops;
	370	rtc->rtc->range_max = U32_MAX;
	371
77d8f3c1	372	rate = clk_get_rate(clk);
fe0557f4 PC	373	jz4740_rtc_set_wakeup_params(rtc, np, rate);
fe0557f4 PC	374
378252b6 PC	375	/* Each 1 Hz pulse should happen after (rate) ticks */
	376	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
	377
fdcfd854	378	ret = devm_rtc_register_device(rtc->rtc);
44c638ce	379	if (ret)
c08ac489	380	return ret;
3bf0eea8	381
77d8f3c1	382	ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
c61293f1	383	pdev->name, rtc);
3bf0eea8	384	if (ret) {
c61293f1	385	dev_err(dev, "Failed to request rtc irq: %d\n", ret);
c08ac489	386	return ret;
3bf0eea8 LPC	387	}
3bf0eea8 LPC	388
24e1f2c9	389	if (of_device_is_system_power_controller(np)) {
fe0557f4 PC	390	dev_for_power_off = dev;
	391
	392	if (!pm_power_off)
f9eb69d1	393	pm_power_off = jz4740_rtc_power_off;
fe0557f4	394	else
c61293f1	395	dev_warn(dev, "Poweroff handler already present!\n");
f9eb69d1 PC	396	}
f9eb69d1 PC	397
3bf0eea8	398	return 0;
3bf0eea8 LPC	399	}
3bf0eea8 LPC	400
681d0378	401	static struct platform_driver jz4740_rtc_driver = {
d0f744c8	402	.probe = jz4740_rtc_probe,
d0f744c8 PC	403	.driver = {
d0f744c8 PC	404	.name = "jz4740-rtc",
24e1f2c9	405	.of_match_table = jz4740_rtc_of_match,
3bf0eea8 LPC	406	},
	407	};
	408
586655d2 AB	409	module_platform_driver(jz4740_rtc_driver);
	410
	411	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	412	MODULE_LICENSE("GPL");
	413	MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
	414	MODULE_ALIAS("platform:jz4740-rtc");