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rtc: s3c-rtc: Avoid using broken ALMYEAR register
[mirror_ubuntu-bionic-kernel.git] / drivers / rtc / rtc-m41t80.c
CommitLineData
caaff562
AN
1/*
2 * I2C client/driver for the ST M41T80 family of i2c rtc chips.
3 *
4 * Author: Alexander Bigga <ab@mycable.de>
5 *
6 * Based on m41t00.c by Mark A. Greer <mgreer@mvista.com>
7 *
8 * 2006 (c) mycable GmbH
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
a737e835
JP
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
35aa64f3 18#include <linux/bcd.h>
1373e77b 19#include <linux/clk-provider.h>
35aa64f3 20#include <linux/i2c.h>
caaff562 21#include <linux/init.h>
9fb1f68d 22#include <linux/kernel.h>
35aa64f3 23#include <linux/module.h>
eb235c56 24#include <linux/of_device.h>
35aa64f3 25#include <linux/rtc.h>
caaff562 26#include <linux/slab.h>
613655fa 27#include <linux/mutex.h>
caaff562 28#include <linux/string.h>
617780d2 29#ifdef CONFIG_RTC_DRV_M41T80_WDT
617780d2
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30#include <linux/fs.h>
31#include <linux/ioctl.h>
35aa64f3
MR
32#include <linux/miscdevice.h>
33#include <linux/reboot.h>
34#include <linux/watchdog.h>
617780d2 35#endif
caaff562 36
f2b84ee8
MJ
37#define M41T80_REG_SSEC 0x00
38#define M41T80_REG_SEC 0x01
39#define M41T80_REG_MIN 0x02
40#define M41T80_REG_HOUR 0x03
41#define M41T80_REG_WDAY 0x04
42#define M41T80_REG_DAY 0x05
43#define M41T80_REG_MON 0x06
44#define M41T80_REG_YEAR 0x07
45#define M41T80_REG_ALARM_MON 0x0a
46#define M41T80_REG_ALARM_DAY 0x0b
47#define M41T80_REG_ALARM_HOUR 0x0c
48#define M41T80_REG_ALARM_MIN 0x0d
49#define M41T80_REG_ALARM_SEC 0x0e
50#define M41T80_REG_FLAGS 0x0f
51#define M41T80_REG_SQW 0x13
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52
53#define M41T80_DATETIME_REG_SIZE (M41T80_REG_YEAR + 1)
54#define M41T80_ALARM_REG_SIZE \
55 (M41T80_REG_ALARM_SEC + 1 - M41T80_REG_ALARM_MON)
56
1373e77b
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57#define M41T80_SQW_MAX_FREQ 32768
58
54339f3b
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59#define M41T80_SEC_ST BIT(7) /* ST: Stop Bit */
60#define M41T80_ALMON_AFE BIT(7) /* AFE: AF Enable Bit */
61#define M41T80_ALMON_SQWE BIT(6) /* SQWE: SQW Enable Bit */
62#define M41T80_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */
05a7f27a 63#define M41T80_FLAGS_OF BIT(2) /* OF: Oscillator Failure Bit */
54339f3b
MJ
64#define M41T80_FLAGS_AF BIT(6) /* AF: Alarm Flag Bit */
65#define M41T80_FLAGS_BATT_LOW BIT(4) /* BL: Battery Low Bit */
66#define M41T80_WATCHDOG_RB2 BIT(7) /* RB: Watchdog resolution */
67#define M41T80_WATCHDOG_RB1 BIT(1) /* RB: Watchdog resolution */
68#define M41T80_WATCHDOG_RB0 BIT(0) /* RB: Watchdog resolution */
caaff562 69
54339f3b
MJ
70#define M41T80_FEATURE_HT BIT(0) /* Halt feature */
71#define M41T80_FEATURE_BL BIT(1) /* Battery low indicator */
72#define M41T80_FEATURE_SQ BIT(2) /* Squarewave feature */
73#define M41T80_FEATURE_WD BIT(3) /* Extra watchdog resolution */
74#define M41T80_FEATURE_SQ_ALT BIT(4) /* RSx bits are in reg 4 */
caaff562 75
613655fa 76static DEFINE_MUTEX(m41t80_rtc_mutex);
3760f736 77static const struct i2c_device_id m41t80_id[] = {
f30281f4 78 { "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT },
d3a126fc
SF
79 { "m41t65", M41T80_FEATURE_HT | M41T80_FEATURE_WD },
80 { "m41t80", M41T80_FEATURE_SQ },
81 { "m41t81", M41T80_FEATURE_HT | M41T80_FEATURE_SQ},
82 { "m41t81s", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
83 { "m41t82", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
84 { "m41t83", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
85 { "m41st84", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
86 { "m41st85", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
87 { "m41st87", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
6b1a5235 88 { "rv4162", M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT },
3760f736 89 { }
caaff562 90};
3760f736 91MODULE_DEVICE_TABLE(i2c, m41t80_id);
caaff562 92
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93static const struct of_device_id m41t80_of_match[] = {
94 {
95 .compatible = "st,m41t62",
96 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT)
97 },
98 {
99 .compatible = "st,m41t65",
100 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_WD)
101 },
102 {
103 .compatible = "st,m41t80",
104 .data = (void *)(M41T80_FEATURE_SQ)
105 },
106 {
107 .compatible = "st,m41t81",
108 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_SQ)
109 },
110 {
111 .compatible = "st,m41t81s",
112 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
113 },
114 {
115 .compatible = "st,m41t82",
116 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
117 },
118 {
119 .compatible = "st,m41t83",
120 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
121 },
122 {
123 .compatible = "st,m41t84",
124 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
125 },
126 {
127 .compatible = "st,m41t85",
128 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
129 },
130 {
131 .compatible = "st,m41t87",
132 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
133 },
a897bf13
AB
134 {
135 .compatible = "microcrystal,rv4162",
136 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT)
137 },
138 /* DT compatibility only, do not use compatibles below: */
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JMC
139 {
140 .compatible = "st,rv4162",
141 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT)
142 },
143 {
144 .compatible = "rv4162",
145 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT)
146 },
147 { }
148};
149MODULE_DEVICE_TABLE(of, m41t80_of_match);
150
caaff562 151struct m41t80_data {
eb235c56 152 unsigned long features;
1373e77b 153 struct i2c_client *client;
caaff562 154 struct rtc_device *rtc;
1373e77b
GB
155#ifdef CONFIG_COMMON_CLK
156 struct clk_hw sqw;
2cb90ed3 157 unsigned long freq;
13bb1d78 158 unsigned int sqwe;
1373e77b 159#endif
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160};
161
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162static irqreturn_t m41t80_handle_irq(int irq, void *dev_id)
163{
164 struct i2c_client *client = dev_id;
165 struct m41t80_data *m41t80 = i2c_get_clientdata(client);
166 struct mutex *lock = &m41t80->rtc->ops_lock;
167 unsigned long events = 0;
168 int flags, flags_afe;
169
170 mutex_lock(lock);
171
172 flags_afe = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
173 if (flags_afe < 0) {
174 mutex_unlock(lock);
175 return IRQ_NONE;
176 }
177
178 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
179 if (flags <= 0) {
180 mutex_unlock(lock);
181 return IRQ_NONE;
182 }
183
184 if (flags & M41T80_FLAGS_AF) {
185 flags &= ~M41T80_FLAGS_AF;
186 flags_afe &= ~M41T80_ALMON_AFE;
187 events |= RTC_AF;
188 }
189
190 if (events) {
191 rtc_update_irq(m41t80->rtc, 1, events);
192 i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, flags);
193 i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
194 flags_afe);
195 }
196
197 mutex_unlock(lock);
198
199 return IRQ_HANDLED;
200}
201
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202static int m41t80_get_datetime(struct i2c_client *client,
203 struct rtc_time *tm)
204{
f2b84ee8 205 unsigned char buf[8];
05a7f27a
MJ
206 int err, flags;
207
208 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
209 if (flags < 0)
210 return flags;
211
212 if (flags & M41T80_FLAGS_OF) {
213 dev_err(&client->dev, "Oscillator failure, data is invalid.\n");
214 return -EINVAL;
215 }
caaff562 216
f2b84ee8
MJ
217 err = i2c_smbus_read_i2c_block_data(client, M41T80_REG_SSEC,
218 sizeof(buf), buf);
219 if (err < 0) {
220 dev_err(&client->dev, "Unable to read date\n");
caaff562
AN
221 return -EIO;
222 }
223
fe20ba70
AB
224 tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f);
225 tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f);
226 tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f);
227 tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f);
caaff562 228 tm->tm_wday = buf[M41T80_REG_WDAY] & 0x07;
fe20ba70 229 tm->tm_mon = bcd2bin(buf[M41T80_REG_MON] & 0x1f) - 1;
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230
231 /* assume 20YY not 19YY, and ignore the Century Bit */
fe20ba70 232 tm->tm_year = bcd2bin(buf[M41T80_REG_YEAR]) + 100;
b485fe5e 233 return rtc_valid_tm(tm);
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AN
234}
235
236/* Sets the given date and time to the real time clock. */
237static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm)
238{
0f546b05 239 struct m41t80_data *clientdata = i2c_get_clientdata(client);
f2b84ee8 240 unsigned char buf[8];
05a7f27a 241 int err, flags;
caaff562 242
f2b84ee8
MJ
243 if (tm->tm_year < 100 || tm->tm_year > 199)
244 return -EINVAL;
caaff562 245
caaff562 246 buf[M41T80_REG_SSEC] = 0;
f2b84ee8
MJ
247 buf[M41T80_REG_SEC] = bin2bcd(tm->tm_sec);
248 buf[M41T80_REG_MIN] = bin2bcd(tm->tm_min);
249 buf[M41T80_REG_HOUR] = bin2bcd(tm->tm_hour);
250 buf[M41T80_REG_DAY] = bin2bcd(tm->tm_mday);
251 buf[M41T80_REG_MON] = bin2bcd(tm->tm_mon + 1);
252 buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year - 100);
253 buf[M41T80_REG_WDAY] = tm->tm_wday;
254
0f546b05
GB
255 /* If the square wave output is controlled in the weekday register */
256 if (clientdata->features & M41T80_FEATURE_SQ_ALT) {
257 int val;
258
259 val = i2c_smbus_read_byte_data(client, M41T80_REG_WDAY);
260 if (val < 0)
261 return val;
262
263 buf[M41T80_REG_WDAY] |= (val & 0xf0);
264 }
265
f2b84ee8
MJ
266 err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_SSEC,
267 sizeof(buf), buf);
268 if (err < 0) {
269 dev_err(&client->dev, "Unable to write to date registers\n");
270 return err;
bcebd81d 271 }
caaff562 272
05a7f27a
MJ
273 /* Clear the OF bit of Flags Register */
274 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
275 if (flags < 0)
276 return flags;
277
278 if (i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS,
279 flags & ~M41T80_FLAGS_OF)) {
280 dev_err(&client->dev, "Unable to write flags register\n");
281 return -EIO;
282 }
283
f2b84ee8 284 return err;
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285}
286
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287static int m41t80_rtc_proc(struct device *dev, struct seq_file *seq)
288{
289 struct i2c_client *client = to_i2c_client(dev);
290 struct m41t80_data *clientdata = i2c_get_clientdata(client);
291 u8 reg;
292
3760f736 293 if (clientdata->features & M41T80_FEATURE_BL) {
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AN
294 reg = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
295 seq_printf(seq, "battery\t\t: %s\n",
296 (reg & M41T80_FLAGS_BATT_LOW) ? "exhausted" : "ok");
297 }
298 return 0;
299}
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AN
300
301static int m41t80_rtc_read_time(struct device *dev, struct rtc_time *tm)
302{
303 return m41t80_get_datetime(to_i2c_client(dev), tm);
304}
305
306static int m41t80_rtc_set_time(struct device *dev, struct rtc_time *tm)
307{
308 return m41t80_set_datetime(to_i2c_client(dev), tm);
309}
310
9c6dfed9
MJ
311static int m41t80_alarm_irq_enable(struct device *dev, unsigned int enabled)
312{
313 struct i2c_client *client = to_i2c_client(dev);
314 int flags, retval;
315
316 flags = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
317 if (flags < 0)
318 return flags;
319
320 if (enabled)
321 flags |= M41T80_ALMON_AFE;
322 else
323 flags &= ~M41T80_ALMON_AFE;
324
325 retval = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, flags);
326 if (retval < 0) {
e89487fe 327 dev_err(dev, "Unable to enable alarm IRQ %d\n", retval);
9c6dfed9
MJ
328 return retval;
329 }
330 return 0;
331}
332
333static int m41t80_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
334{
335 struct i2c_client *client = to_i2c_client(dev);
336 u8 alarmvals[5];
337 int ret, err;
338
339 alarmvals[0] = bin2bcd(alrm->time.tm_mon + 1);
340 alarmvals[1] = bin2bcd(alrm->time.tm_mday);
341 alarmvals[2] = bin2bcd(alrm->time.tm_hour);
342 alarmvals[3] = bin2bcd(alrm->time.tm_min);
343 alarmvals[4] = bin2bcd(alrm->time.tm_sec);
344
345 /* Clear AF and AFE flags */
346 ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
347 if (ret < 0)
348 return ret;
349 err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
350 ret & ~(M41T80_ALMON_AFE));
351 if (err < 0) {
352 dev_err(dev, "Unable to clear AFE bit\n");
353 return err;
354 }
355
2de9261c
GB
356 /* Keep SQWE bit value */
357 alarmvals[0] |= (ret & M41T80_ALMON_SQWE);
358
9c6dfed9
MJ
359 ret = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
360 if (ret < 0)
361 return ret;
362
363 err = i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS,
364 ret & ~(M41T80_FLAGS_AF));
365 if (err < 0) {
366 dev_err(dev, "Unable to clear AF bit\n");
367 return err;
368 }
369
370 /* Write the alarm */
371 err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_ALARM_MON,
372 5, alarmvals);
373 if (err)
374 return err;
375
376 /* Enable the alarm interrupt */
377 if (alrm->enabled) {
378 alarmvals[0] |= M41T80_ALMON_AFE;
379 err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
380 alarmvals[0]);
381 if (err)
382 return err;
383 }
384
385 return 0;
386}
387
388static int m41t80_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
389{
390 struct i2c_client *client = to_i2c_client(dev);
391 u8 alarmvals[5];
392 int flags, ret;
393
394 ret = i2c_smbus_read_i2c_block_data(client, M41T80_REG_ALARM_MON,
395 5, alarmvals);
396 if (ret != 5)
397 return ret < 0 ? ret : -EIO;
398
399 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
400 if (flags < 0)
401 return flags;
402
403 alrm->time.tm_sec = bcd2bin(alarmvals[4] & 0x7f);
404 alrm->time.tm_min = bcd2bin(alarmvals[3] & 0x7f);
405 alrm->time.tm_hour = bcd2bin(alarmvals[2] & 0x3f);
9c6dfed9 406 alrm->time.tm_mday = bcd2bin(alarmvals[1] & 0x3f);
c39c674e 407 alrm->time.tm_mon = bcd2bin(alarmvals[0] & 0x3f) - 1;
9c6dfed9
MJ
408
409 alrm->enabled = !!(alarmvals[0] & M41T80_ALMON_AFE);
410 alrm->pending = (flags & M41T80_FLAGS_AF) && alrm->enabled;
411
412 return 0;
413}
414
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AN
415static struct rtc_class_ops m41t80_rtc_ops = {
416 .read_time = m41t80_rtc_read_time,
417 .set_time = m41t80_rtc_set_time,
caaff562 418 .proc = m41t80_rtc_proc,
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AN
419};
420
ae036af8
SC
421#ifdef CONFIG_PM_SLEEP
422static int m41t80_suspend(struct device *dev)
423{
424 struct i2c_client *client = to_i2c_client(dev);
425
426 if (client->irq >= 0 && device_may_wakeup(dev))
427 enable_irq_wake(client->irq);
428
429 return 0;
430}
431
432static int m41t80_resume(struct device *dev)
433{
434 struct i2c_client *client = to_i2c_client(dev);
435
436 if (client->irq >= 0 && device_may_wakeup(dev))
437 disable_irq_wake(client->irq);
438
439 return 0;
440}
441#endif
442
443static SIMPLE_DEV_PM_OPS(m41t80_pm, m41t80_suspend, m41t80_resume);
444
1373e77b
GB
445#ifdef CONFIG_COMMON_CLK
446#define sqw_to_m41t80_data(_hw) container_of(_hw, struct m41t80_data, sqw)
447
2cb90ed3
TK
448static unsigned long m41t80_decode_freq(int setting)
449{
450 return (setting == 0) ? 0 : (setting == 1) ? M41T80_SQW_MAX_FREQ :
451 M41T80_SQW_MAX_FREQ >> setting;
452}
453
454static unsigned long m41t80_get_freq(struct m41t80_data *m41t80)
1373e77b 455{
1373e77b
GB
456 struct i2c_client *client = m41t80->client;
457 int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ?
458 M41T80_REG_WDAY : M41T80_REG_SQW;
459 int ret = i2c_smbus_read_byte_data(client, reg_sqw);
1373e77b
GB
460
461 if (ret < 0)
462 return 0;
2cb90ed3
TK
463 return m41t80_decode_freq(ret >> 4);
464}
1373e77b 465
2cb90ed3
TK
466static unsigned long m41t80_sqw_recalc_rate(struct clk_hw *hw,
467 unsigned long parent_rate)
468{
469 return sqw_to_m41t80_data(hw)->freq;
1373e77b
GB
470}
471
472static long m41t80_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
473 unsigned long *prate)
474{
c8384bb0
TK
475 if (rate >= M41T80_SQW_MAX_FREQ)
476 return M41T80_SQW_MAX_FREQ;
477 if (rate >= M41T80_SQW_MAX_FREQ / 4)
478 return M41T80_SQW_MAX_FREQ / 4;
479 if (!rate)
480 return 0;
481 return 1 << ilog2(rate);
1373e77b
GB
482}
483
484static int m41t80_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
485 unsigned long parent_rate)
486{
487 struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw);
488 struct i2c_client *client = m41t80->client;
489 int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ?
490 M41T80_REG_WDAY : M41T80_REG_SQW;
491 int reg, ret, val = 0;
492
05a03bf2
TK
493 if (rate >= M41T80_SQW_MAX_FREQ)
494 val = 1;
495 else if (rate >= M41T80_SQW_MAX_FREQ / 4)
496 val = 2;
497 else if (rate)
498 val = 15 - ilog2(rate);
1373e77b
GB
499
500 reg = i2c_smbus_read_byte_data(client, reg_sqw);
501 if (reg < 0)
502 return reg;
503
504 reg = (reg & 0x0f) | (val << 4);
505
506 ret = i2c_smbus_write_byte_data(client, reg_sqw, reg);
2cb90ed3
TK
507 if (!ret)
508 m41t80->freq = m41t80_decode_freq(val);
de6042d2 509 return ret;
1373e77b
GB
510}
511
512static int m41t80_sqw_control(struct clk_hw *hw, bool enable)
513{
514 struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw);
515 struct i2c_client *client = m41t80->client;
516 int ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
517
518 if (ret < 0)
519 return ret;
520
521 if (enable)
522 ret |= M41T80_ALMON_SQWE;
523 else
524 ret &= ~M41T80_ALMON_SQWE;
525
13bb1d78
TK
526 ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, ret);
527 if (!ret)
528 m41t80->sqwe = enable;
529 return ret;
1373e77b
GB
530}
531
532static int m41t80_sqw_prepare(struct clk_hw *hw)
533{
534 return m41t80_sqw_control(hw, 1);
535}
536
537static void m41t80_sqw_unprepare(struct clk_hw *hw)
538{
539 m41t80_sqw_control(hw, 0);
540}
541
542static int m41t80_sqw_is_prepared(struct clk_hw *hw)
543{
13bb1d78 544 return sqw_to_m41t80_data(hw)->sqwe;
1373e77b
GB
545}
546
547static const struct clk_ops m41t80_sqw_ops = {
548 .prepare = m41t80_sqw_prepare,
549 .unprepare = m41t80_sqw_unprepare,
550 .is_prepared = m41t80_sqw_is_prepared,
551 .recalc_rate = m41t80_sqw_recalc_rate,
552 .round_rate = m41t80_sqw_round_rate,
553 .set_rate = m41t80_sqw_set_rate,
554};
555
556static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80)
557{
558 struct i2c_client *client = m41t80->client;
559 struct device_node *node = client->dev.of_node;
560 struct clk *clk;
561 struct clk_init_data init;
562 int ret;
563
564 /* First disable the clock */
565 ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
566 if (ret < 0)
567 return ERR_PTR(ret);
568 ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
569 ret & ~(M41T80_ALMON_SQWE));
570 if (ret < 0)
571 return ERR_PTR(ret);
572
573 init.name = "m41t80-sqw";
574 init.ops = &m41t80_sqw_ops;
575 init.flags = 0;
576 init.parent_names = NULL;
577 init.num_parents = 0;
578 m41t80->sqw.init = &init;
2cb90ed3 579 m41t80->freq = m41t80_get_freq(m41t80);
1373e77b
GB
580
581 /* optional override of the clockname */
582 of_property_read_string(node, "clock-output-names", &init.name);
583
584 /* register the clock */
585 clk = clk_register(&client->dev, &m41t80->sqw);
586 if (!IS_ERR(clk))
587 of_clk_add_provider(node, of_clk_src_simple_get, clk);
588
589 return clk;
590}
591#endif
592
617780d2
AN
593#ifdef CONFIG_RTC_DRV_M41T80_WDT
594/*
595 *****************************************************************************
596 *
597 * Watchdog Driver
598 *
599 *****************************************************************************
600 */
601static struct i2c_client *save_client;
602
603/* Default margin */
604#define WD_TIMO 60 /* 1..31 seconds */
605
606static int wdt_margin = WD_TIMO;
607module_param(wdt_margin, int, 0);
608MODULE_PARM_DESC(wdt_margin, "Watchdog timeout in seconds (default 60s)");
609
610static unsigned long wdt_is_open;
611static int boot_flag;
612
613/**
614 * wdt_ping:
615 *
616 * Reload counter one with the watchdog timeout. We don't bother reloading
617 * the cascade counter.
618 */
619static void wdt_ping(void)
620{
621 unsigned char i2c_data[2];
622 struct i2c_msg msgs1[1] = {
623 {
624 .addr = save_client->addr,
625 .flags = 0,
626 .len = 2,
627 .buf = i2c_data,
628 },
629 };
d3a126fc
SF
630 struct m41t80_data *clientdata = i2c_get_clientdata(save_client);
631
617780d2
AN
632 i2c_data[0] = 0x09; /* watchdog register */
633
634 if (wdt_margin > 31)
635 i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */
636 else
637 /*
638 * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02)
639 */
fc99b901 640 i2c_data[1] = wdt_margin << 2 | 0x82;
617780d2 641
d3a126fc
SF
642 /*
643 * M41T65 has three bits for watchdog resolution. Don't set bit 7, as
644 * that would be an invalid resolution.
645 */
646 if (clientdata->features & M41T80_FEATURE_WD)
647 i2c_data[1] &= ~M41T80_WATCHDOG_RB2;
648
617780d2
AN
649 i2c_transfer(save_client->adapter, msgs1, 1);
650}
651
652/**
653 * wdt_disable:
654 *
655 * disables watchdog.
656 */
657static void wdt_disable(void)
658{
659 unsigned char i2c_data[2], i2c_buf[0x10];
660 struct i2c_msg msgs0[2] = {
661 {
662 .addr = save_client->addr,
663 .flags = 0,
664 .len = 1,
665 .buf = i2c_data,
666 },
667 {
668 .addr = save_client->addr,
669 .flags = I2C_M_RD,
670 .len = 1,
671 .buf = i2c_buf,
672 },
673 };
674 struct i2c_msg msgs1[1] = {
675 {
676 .addr = save_client->addr,
677 .flags = 0,
678 .len = 2,
679 .buf = i2c_data,
680 },
681 };
682
683 i2c_data[0] = 0x09;
684 i2c_transfer(save_client->adapter, msgs0, 2);
685
686 i2c_data[0] = 0x09;
687 i2c_data[1] = 0x00;
688 i2c_transfer(save_client->adapter, msgs1, 1);
689}
690
691/**
692 * wdt_write:
693 * @file: file handle to the watchdog
694 * @buf: buffer to write (unused as data does not matter here
695 * @count: count of bytes
696 * @ppos: pointer to the position to write. No seeks allowed
697 *
698 * A write to a watchdog device is defined as a keepalive signal. Any
699 * write of data will do, as we we don't define content meaning.
700 */
701static ssize_t wdt_write(struct file *file, const char __user *buf,
702 size_t count, loff_t *ppos)
703{
617780d2
AN
704 if (count) {
705 wdt_ping();
706 return 1;
707 }
708 return 0;
709}
710
711static ssize_t wdt_read(struct file *file, char __user *buf,
712 size_t count, loff_t *ppos)
713{
714 return 0;
715}
716
717/**
718 * wdt_ioctl:
719 * @inode: inode of the device
720 * @file: file handle to the device
721 * @cmd: watchdog command
722 * @arg: argument pointer
723 *
724 * The watchdog API defines a common set of functions for all watchdogs
725 * according to their available features. We only actually usefully support
726 * querying capabilities and current status.
727 */
55929332 728static int wdt_ioctl(struct file *file, unsigned int cmd,
617780d2
AN
729 unsigned long arg)
730{
731 int new_margin, rv;
732 static struct watchdog_info ident = {
733 .options = WDIOF_POWERUNDER | WDIOF_KEEPALIVEPING |
734 WDIOF_SETTIMEOUT,
735 .firmware_version = 1,
736 .identity = "M41T80 WTD"
737 };
738
739 switch (cmd) {
740 case WDIOC_GETSUPPORT:
741 return copy_to_user((struct watchdog_info __user *)arg, &ident,
742 sizeof(ident)) ? -EFAULT : 0;
743
744 case WDIOC_GETSTATUS:
745 case WDIOC_GETBOOTSTATUS:
746 return put_user(boot_flag, (int __user *)arg);
747 case WDIOC_KEEPALIVE:
748 wdt_ping();
749 return 0;
750 case WDIOC_SETTIMEOUT:
751 if (get_user(new_margin, (int __user *)arg))
752 return -EFAULT;
753 /* Arbitrary, can't find the card's limits */
754 if (new_margin < 1 || new_margin > 124)
755 return -EINVAL;
756 wdt_margin = new_margin;
757 wdt_ping();
758 /* Fall */
759 case WDIOC_GETTIMEOUT:
760 return put_user(wdt_margin, (int __user *)arg);
761
762 case WDIOC_SETOPTIONS:
763 if (copy_from_user(&rv, (int __user *)arg, sizeof(int)))
764 return -EFAULT;
765
766 if (rv & WDIOS_DISABLECARD) {
a737e835 767 pr_info("disable watchdog\n");
617780d2
AN
768 wdt_disable();
769 }
770
771 if (rv & WDIOS_ENABLECARD) {
a737e835 772 pr_info("enable watchdog\n");
617780d2
AN
773 wdt_ping();
774 }
775
776 return -EINVAL;
777 }
778 return -ENOTTY;
779}
780
55929332
AB
781static long wdt_unlocked_ioctl(struct file *file, unsigned int cmd,
782 unsigned long arg)
783{
784 int ret;
785
613655fa 786 mutex_lock(&m41t80_rtc_mutex);
55929332 787 ret = wdt_ioctl(file, cmd, arg);
613655fa 788 mutex_unlock(&m41t80_rtc_mutex);
55929332
AB
789
790 return ret;
791}
792
617780d2
AN
793/**
794 * wdt_open:
795 * @inode: inode of device
796 * @file: file handle to device
797 *
798 */
799static int wdt_open(struct inode *inode, struct file *file)
800{
801 if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) {
613655fa 802 mutex_lock(&m41t80_rtc_mutex);
41012735 803 if (test_and_set_bit(0, &wdt_is_open)) {
613655fa 804 mutex_unlock(&m41t80_rtc_mutex);
617780d2 805 return -EBUSY;
41012735 806 }
617780d2
AN
807 /*
808 * Activate
809 */
810 wdt_is_open = 1;
613655fa 811 mutex_unlock(&m41t80_rtc_mutex);
09eeb1f5 812 return nonseekable_open(inode, file);
617780d2
AN
813 }
814 return -ENODEV;
815}
816
817/**
818 * wdt_close:
819 * @inode: inode to board
820 * @file: file handle to board
821 *
822 */
823static int wdt_release(struct inode *inode, struct file *file)
824{
825 if (MINOR(inode->i_rdev) == WATCHDOG_MINOR)
826 clear_bit(0, &wdt_is_open);
827 return 0;
828}
829
830/**
831 * notify_sys:
832 * @this: our notifier block
833 * @code: the event being reported
834 * @unused: unused
835 *
836 * Our notifier is called on system shutdowns. We want to turn the card
837 * off at reboot otherwise the machine will reboot again during memory
838 * test or worse yet during the following fsck. This would suck, in fact
839 * trust me - if it happens it does suck.
840 */
841static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
842 void *unused)
843{
844 if (code == SYS_DOWN || code == SYS_HALT)
845 /* Disable Watchdog */
846 wdt_disable();
847 return NOTIFY_DONE;
848}
849
850static const struct file_operations wdt_fops = {
851 .owner = THIS_MODULE,
852 .read = wdt_read,
55929332 853 .unlocked_ioctl = wdt_unlocked_ioctl,
617780d2
AN
854 .write = wdt_write,
855 .open = wdt_open,
856 .release = wdt_release,
6038f373 857 .llseek = no_llseek,
617780d2
AN
858};
859
860static struct miscdevice wdt_dev = {
861 .minor = WATCHDOG_MINOR,
862 .name = "watchdog",
863 .fops = &wdt_fops,
864};
865
866/*
867 * The WDT card needs to learn about soft shutdowns in order to
868 * turn the timebomb registers off.
869 */
870static struct notifier_block wdt_notifier = {
871 .notifier_call = wdt_notify_sys,
872};
873#endif /* CONFIG_RTC_DRV_M41T80_WDT */
874
caaff562
AN
875/*
876 *****************************************************************************
877 *
878 * Driver Interface
879 *
880 *****************************************************************************
881 */
ef6b3125 882
d2653e92
JD
883static int m41t80_probe(struct i2c_client *client,
884 const struct i2c_device_id *id)
caaff562 885{
f2b84ee8 886 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
3760f736 887 int rc = 0;
caaff562 888 struct rtc_time tm;
9c6dfed9 889 struct m41t80_data *m41t80_data = NULL;
d4473b9b 890 bool wakeup_source = false;
caaff562 891
f2b84ee8
MJ
892 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK |
893 I2C_FUNC_SMBUS_BYTE_DATA)) {
894 dev_err(&adapter->dev, "doesn't support I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK\n");
c67fedfa 895 return -ENODEV;
f2b84ee8 896 }
caaff562 897
9c6dfed9
MJ
898 m41t80_data = devm_kzalloc(&client->dev, sizeof(*m41t80_data),
899 GFP_KERNEL);
900 if (!m41t80_data)
c67fedfa 901 return -ENOMEM;
caaff562 902
1373e77b 903 m41t80_data->client = client;
eb235c56
JMC
904 if (client->dev.of_node)
905 m41t80_data->features = (unsigned long)
906 of_device_get_match_data(&client->dev);
907 else
908 m41t80_data->features = id->driver_data;
9c6dfed9
MJ
909 i2c_set_clientdata(client, m41t80_data);
910
b606c20f
AB
911 m41t80_data->rtc = devm_rtc_allocate_device(&client->dev);
912 if (IS_ERR(m41t80_data->rtc))
913 return PTR_ERR(m41t80_data->rtc);
914
d4473b9b
EC
915#ifdef CONFIG_OF
916 wakeup_source = of_property_read_bool(client->dev.of_node,
917 "wakeup-source");
918#endif
9c6dfed9
MJ
919 if (client->irq > 0) {
920 rc = devm_request_threaded_irq(&client->dev, client->irq,
921 NULL, m41t80_handle_irq,
922 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
923 "m41t80", client);
924 if (rc) {
925 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
926 client->irq = 0;
d4473b9b 927 wakeup_source = false;
9c6dfed9
MJ
928 }
929 }
d4473b9b
EC
930 if (client->irq > 0 || wakeup_source) {
931 m41t80_rtc_ops.read_alarm = m41t80_read_alarm;
932 m41t80_rtc_ops.set_alarm = m41t80_set_alarm;
933 m41t80_rtc_ops.alarm_irq_enable = m41t80_alarm_irq_enable;
934 /* Enable the wakealarm */
935 device_init_wakeup(&client->dev, true);
936 }
a015dbc1 937
b606c20f 938 m41t80_data->rtc->ops = &m41t80_rtc_ops;
caaff562 939
d4473b9b
EC
940 if (client->irq <= 0) {
941 /* We cannot support UIE mode if we do not have an IRQ line */
b606c20f 942 m41t80_data->rtc->uie_unsupported = 1;
d4473b9b 943 }
caaff562
AN
944
945 /* Make sure HT (Halt Update) bit is cleared */
946 rc = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_HOUR);
caaff562 947
c67fedfa 948 if (rc >= 0 && rc & M41T80_ALHOUR_HT) {
9c6dfed9 949 if (m41t80_data->features & M41T80_FEATURE_HT) {
caaff562
AN
950 m41t80_get_datetime(client, &tm);
951 dev_info(&client->dev, "HT bit was set!\n");
952 dev_info(&client->dev,
fc99b901 953 "Power Down at %04i-%02i-%02i %02i:%02i:%02i\n",
caaff562
AN
954 tm.tm_year + 1900,
955 tm.tm_mon + 1, tm.tm_mday, tm.tm_hour,
956 tm.tm_min, tm.tm_sec);
957 }
c67fedfa 958 rc = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_HOUR,
fc99b901 959 rc & ~M41T80_ALHOUR_HT);
c67fedfa
WS
960 }
961
962 if (rc < 0) {
963 dev_err(&client->dev, "Can't clear HT bit\n");
85d77047 964 return rc;
caaff562
AN
965 }
966
967 /* Make sure ST (stop) bit is cleared */
968 rc = i2c_smbus_read_byte_data(client, M41T80_REG_SEC);
caaff562 969
c67fedfa
WS
970 if (rc >= 0 && rc & M41T80_SEC_ST)
971 rc = i2c_smbus_write_byte_data(client, M41T80_REG_SEC,
fc99b901 972 rc & ~M41T80_SEC_ST);
c67fedfa
WS
973 if (rc < 0) {
974 dev_err(&client->dev, "Can't clear ST bit\n");
85d77047 975 return rc;
caaff562
AN
976 }
977
617780d2 978#ifdef CONFIG_RTC_DRV_M41T80_WDT
9c6dfed9 979 if (m41t80_data->features & M41T80_FEATURE_HT) {
417607d0 980 save_client = client;
617780d2
AN
981 rc = misc_register(&wdt_dev);
982 if (rc)
c67fedfa 983 return rc;
617780d2
AN
984 rc = register_reboot_notifier(&wdt_notifier);
985 if (rc) {
986 misc_deregister(&wdt_dev);
c67fedfa 987 return rc;
617780d2 988 }
617780d2 989 }
1373e77b
GB
990#endif
991#ifdef CONFIG_COMMON_CLK
992 if (m41t80_data->features & M41T80_FEATURE_SQ)
993 m41t80_sqw_register_clk(m41t80_data);
617780d2 994#endif
b606c20f
AB
995
996 rc = rtc_register_device(m41t80_data->rtc);
997 if (rc)
998 return rc;
999
caaff562 1000 return 0;
caaff562
AN
1001}
1002
1003static int m41t80_remove(struct i2c_client *client)
1004{
4ebabb78 1005#ifdef CONFIG_RTC_DRV_M41T80_WDT
caaff562 1006 struct m41t80_data *clientdata = i2c_get_clientdata(client);
caaff562 1007
3760f736 1008 if (clientdata->features & M41T80_FEATURE_HT) {
617780d2
AN
1009 misc_deregister(&wdt_dev);
1010 unregister_reboot_notifier(&wdt_notifier);
1011 }
1012#endif
caaff562
AN
1013
1014 return 0;
1015}
1016
1017static struct i2c_driver m41t80_driver = {
1018 .driver = {
afe1ab4d 1019 .name = "rtc-m41t80",
eb235c56 1020 .of_match_table = of_match_ptr(m41t80_of_match),
ae036af8 1021 .pm = &m41t80_pm,
caaff562
AN
1022 },
1023 .probe = m41t80_probe,
1024 .remove = m41t80_remove,
3760f736 1025 .id_table = m41t80_id,
caaff562
AN
1026};
1027
0abc9201 1028module_i2c_driver(m41t80_driver);
caaff562
AN
1029
1030MODULE_AUTHOR("Alexander Bigga <ab@mycable.de>");
1031MODULE_DESCRIPTION("ST Microelectronics M41T80 series RTC I2C Client Driver");
1032MODULE_LICENSE("GPL");