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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
caaff562 AN |
2 | /* |
3 | * I2C client/driver for the ST M41T80 family of i2c rtc chips. | |
4 | * | |
5 | * Author: Alexander Bigga <ab@mycable.de> | |
6 | * | |
7 | * Based on m41t00.c by Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * 2006 (c) mycable GmbH | |
caaff562 AN |
10 | */ |
11 | ||
a737e835 JP |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
13 | ||
35aa64f3 | 14 | #include <linux/bcd.h> |
1373e77b | 15 | #include <linux/clk-provider.h> |
35aa64f3 | 16 | #include <linux/i2c.h> |
caaff562 | 17 | #include <linux/init.h> |
9fb1f68d | 18 | #include <linux/kernel.h> |
35aa64f3 | 19 | #include <linux/module.h> |
eb235c56 | 20 | #include <linux/of_device.h> |
35aa64f3 | 21 | #include <linux/rtc.h> |
caaff562 | 22 | #include <linux/slab.h> |
613655fa | 23 | #include <linux/mutex.h> |
caaff562 | 24 | #include <linux/string.h> |
617780d2 | 25 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
617780d2 AN |
26 | #include <linux/fs.h> |
27 | #include <linux/ioctl.h> | |
35aa64f3 MR |
28 | #include <linux/miscdevice.h> |
29 | #include <linux/reboot.h> | |
30 | #include <linux/watchdog.h> | |
617780d2 | 31 | #endif |
caaff562 | 32 | |
f2b84ee8 MJ |
33 | #define M41T80_REG_SSEC 0x00 |
34 | #define M41T80_REG_SEC 0x01 | |
35 | #define M41T80_REG_MIN 0x02 | |
36 | #define M41T80_REG_HOUR 0x03 | |
37 | #define M41T80_REG_WDAY 0x04 | |
38 | #define M41T80_REG_DAY 0x05 | |
39 | #define M41T80_REG_MON 0x06 | |
40 | #define M41T80_REG_YEAR 0x07 | |
41 | #define M41T80_REG_ALARM_MON 0x0a | |
42 | #define M41T80_REG_ALARM_DAY 0x0b | |
43 | #define M41T80_REG_ALARM_HOUR 0x0c | |
44 | #define M41T80_REG_ALARM_MIN 0x0d | |
45 | #define M41T80_REG_ALARM_SEC 0x0e | |
46 | #define M41T80_REG_FLAGS 0x0f | |
47 | #define M41T80_REG_SQW 0x13 | |
caaff562 AN |
48 | |
49 | #define M41T80_DATETIME_REG_SIZE (M41T80_REG_YEAR + 1) | |
50 | #define M41T80_ALARM_REG_SIZE \ | |
51 | (M41T80_REG_ALARM_SEC + 1 - M41T80_REG_ALARM_MON) | |
52 | ||
1373e77b GB |
53 | #define M41T80_SQW_MAX_FREQ 32768 |
54 | ||
54339f3b MJ |
55 | #define M41T80_SEC_ST BIT(7) /* ST: Stop Bit */ |
56 | #define M41T80_ALMON_AFE BIT(7) /* AFE: AF Enable Bit */ | |
57 | #define M41T80_ALMON_SQWE BIT(6) /* SQWE: SQW Enable Bit */ | |
58 | #define M41T80_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */ | |
05a7f27a | 59 | #define M41T80_FLAGS_OF BIT(2) /* OF: Oscillator Failure Bit */ |
54339f3b MJ |
60 | #define M41T80_FLAGS_AF BIT(6) /* AF: Alarm Flag Bit */ |
61 | #define M41T80_FLAGS_BATT_LOW BIT(4) /* BL: Battery Low Bit */ | |
62 | #define M41T80_WATCHDOG_RB2 BIT(7) /* RB: Watchdog resolution */ | |
63 | #define M41T80_WATCHDOG_RB1 BIT(1) /* RB: Watchdog resolution */ | |
64 | #define M41T80_WATCHDOG_RB0 BIT(0) /* RB: Watchdog resolution */ | |
caaff562 | 65 | |
54339f3b MJ |
66 | #define M41T80_FEATURE_HT BIT(0) /* Halt feature */ |
67 | #define M41T80_FEATURE_BL BIT(1) /* Battery low indicator */ | |
68 | #define M41T80_FEATURE_SQ BIT(2) /* Squarewave feature */ | |
69 | #define M41T80_FEATURE_WD BIT(3) /* Extra watchdog resolution */ | |
70 | #define M41T80_FEATURE_SQ_ALT BIT(4) /* RSx bits are in reg 4 */ | |
caaff562 | 71 | |
3760f736 | 72 | static const struct i2c_device_id m41t80_id[] = { |
f30281f4 | 73 | { "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT }, |
d3a126fc SF |
74 | { "m41t65", M41T80_FEATURE_HT | M41T80_FEATURE_WD }, |
75 | { "m41t80", M41T80_FEATURE_SQ }, | |
76 | { "m41t81", M41T80_FEATURE_HT | M41T80_FEATURE_SQ}, | |
77 | { "m41t81s", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
78 | { "m41t82", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
79 | { "m41t83", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
80 | { "m41st84", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
81 | { "m41st85", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
82 | { "m41st87", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
6b1a5235 | 83 | { "rv4162", M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT }, |
3760f736 | 84 | { } |
caaff562 | 85 | }; |
3760f736 | 86 | MODULE_DEVICE_TABLE(i2c, m41t80_id); |
caaff562 | 87 | |
2717c59e | 88 | static const __maybe_unused struct of_device_id m41t80_of_match[] = { |
eb235c56 JMC |
89 | { |
90 | .compatible = "st,m41t62", | |
91 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT) | |
92 | }, | |
93 | { | |
94 | .compatible = "st,m41t65", | |
95 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_WD) | |
96 | }, | |
97 | { | |
98 | .compatible = "st,m41t80", | |
99 | .data = (void *)(M41T80_FEATURE_SQ) | |
100 | }, | |
101 | { | |
102 | .compatible = "st,m41t81", | |
103 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_SQ) | |
104 | }, | |
105 | { | |
106 | .compatible = "st,m41t81s", | |
107 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
108 | }, | |
109 | { | |
110 | .compatible = "st,m41t82", | |
111 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
112 | }, | |
113 | { | |
114 | .compatible = "st,m41t83", | |
115 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
116 | }, | |
117 | { | |
118 | .compatible = "st,m41t84", | |
119 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
120 | }, | |
121 | { | |
122 | .compatible = "st,m41t85", | |
123 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
124 | }, | |
125 | { | |
126 | .compatible = "st,m41t87", | |
127 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
128 | }, | |
a897bf13 AB |
129 | { |
130 | .compatible = "microcrystal,rv4162", | |
131 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT) | |
132 | }, | |
133 | /* DT compatibility only, do not use compatibles below: */ | |
eb235c56 JMC |
134 | { |
135 | .compatible = "st,rv4162", | |
136 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT) | |
137 | }, | |
138 | { | |
139 | .compatible = "rv4162", | |
140 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT) | |
141 | }, | |
142 | { } | |
143 | }; | |
144 | MODULE_DEVICE_TABLE(of, m41t80_of_match); | |
145 | ||
caaff562 | 146 | struct m41t80_data { |
eb235c56 | 147 | unsigned long features; |
1373e77b | 148 | struct i2c_client *client; |
caaff562 | 149 | struct rtc_device *rtc; |
1373e77b GB |
150 | #ifdef CONFIG_COMMON_CLK |
151 | struct clk_hw sqw; | |
2cb90ed3 | 152 | unsigned long freq; |
13bb1d78 | 153 | unsigned int sqwe; |
1373e77b | 154 | #endif |
caaff562 AN |
155 | }; |
156 | ||
9c6dfed9 MJ |
157 | static irqreturn_t m41t80_handle_irq(int irq, void *dev_id) |
158 | { | |
159 | struct i2c_client *client = dev_id; | |
160 | struct m41t80_data *m41t80 = i2c_get_clientdata(client); | |
9c6dfed9 MJ |
161 | unsigned long events = 0; |
162 | int flags, flags_afe; | |
163 | ||
06c6e321 | 164 | rtc_lock(m41t80->rtc); |
9c6dfed9 MJ |
165 | |
166 | flags_afe = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
167 | if (flags_afe < 0) { | |
06c6e321 | 168 | rtc_unlock(m41t80->rtc); |
9c6dfed9 MJ |
169 | return IRQ_NONE; |
170 | } | |
171 | ||
172 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
173 | if (flags <= 0) { | |
06c6e321 | 174 | rtc_unlock(m41t80->rtc); |
9c6dfed9 MJ |
175 | return IRQ_NONE; |
176 | } | |
177 | ||
178 | if (flags & M41T80_FLAGS_AF) { | |
179 | flags &= ~M41T80_FLAGS_AF; | |
180 | flags_afe &= ~M41T80_ALMON_AFE; | |
181 | events |= RTC_AF; | |
182 | } | |
183 | ||
184 | if (events) { | |
185 | rtc_update_irq(m41t80->rtc, 1, events); | |
186 | i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, flags); | |
187 | i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
188 | flags_afe); | |
189 | } | |
190 | ||
06c6e321 | 191 | rtc_unlock(m41t80->rtc); |
9c6dfed9 MJ |
192 | |
193 | return IRQ_HANDLED; | |
194 | } | |
195 | ||
e2c8e1a9 | 196 | static int m41t80_rtc_read_time(struct device *dev, struct rtc_time *tm) |
caaff562 | 197 | { |
e2c8e1a9 | 198 | struct i2c_client *client = to_i2c_client(dev); |
f2b84ee8 | 199 | unsigned char buf[8]; |
05a7f27a MJ |
200 | int err, flags; |
201 | ||
202 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
203 | if (flags < 0) | |
204 | return flags; | |
205 | ||
206 | if (flags & M41T80_FLAGS_OF) { | |
207 | dev_err(&client->dev, "Oscillator failure, data is invalid.\n"); | |
208 | return -EINVAL; | |
209 | } | |
caaff562 | 210 | |
f2b84ee8 MJ |
211 | err = i2c_smbus_read_i2c_block_data(client, M41T80_REG_SSEC, |
212 | sizeof(buf), buf); | |
213 | if (err < 0) { | |
214 | dev_err(&client->dev, "Unable to read date\n"); | |
f1bd154d | 215 | return err; |
caaff562 AN |
216 | } |
217 | ||
fe20ba70 AB |
218 | tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f); |
219 | tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); | |
220 | tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f); | |
221 | tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f); | |
caaff562 | 222 | tm->tm_wday = buf[M41T80_REG_WDAY] & 0x07; |
fe20ba70 | 223 | tm->tm_mon = bcd2bin(buf[M41T80_REG_MON] & 0x1f) - 1; |
caaff562 AN |
224 | |
225 | /* assume 20YY not 19YY, and ignore the Century Bit */ | |
fe20ba70 | 226 | tm->tm_year = bcd2bin(buf[M41T80_REG_YEAR]) + 100; |
22652ba7 | 227 | return 0; |
caaff562 AN |
228 | } |
229 | ||
e2c8e1a9 | 230 | static int m41t80_rtc_set_time(struct device *dev, struct rtc_time *tm) |
caaff562 | 231 | { |
e2c8e1a9 | 232 | struct i2c_client *client = to_i2c_client(dev); |
0f546b05 | 233 | struct m41t80_data *clientdata = i2c_get_clientdata(client); |
f2b84ee8 | 234 | unsigned char buf[8]; |
05a7f27a | 235 | int err, flags; |
caaff562 | 236 | |
caaff562 | 237 | buf[M41T80_REG_SSEC] = 0; |
f2b84ee8 MJ |
238 | buf[M41T80_REG_SEC] = bin2bcd(tm->tm_sec); |
239 | buf[M41T80_REG_MIN] = bin2bcd(tm->tm_min); | |
240 | buf[M41T80_REG_HOUR] = bin2bcd(tm->tm_hour); | |
241 | buf[M41T80_REG_DAY] = bin2bcd(tm->tm_mday); | |
242 | buf[M41T80_REG_MON] = bin2bcd(tm->tm_mon + 1); | |
243 | buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year - 100); | |
244 | buf[M41T80_REG_WDAY] = tm->tm_wday; | |
245 | ||
0f546b05 GB |
246 | /* If the square wave output is controlled in the weekday register */ |
247 | if (clientdata->features & M41T80_FEATURE_SQ_ALT) { | |
248 | int val; | |
249 | ||
250 | val = i2c_smbus_read_byte_data(client, M41T80_REG_WDAY); | |
251 | if (val < 0) | |
252 | return val; | |
253 | ||
254 | buf[M41T80_REG_WDAY] |= (val & 0xf0); | |
255 | } | |
256 | ||
f2b84ee8 MJ |
257 | err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_SSEC, |
258 | sizeof(buf), buf); | |
259 | if (err < 0) { | |
260 | dev_err(&client->dev, "Unable to write to date registers\n"); | |
261 | return err; | |
bcebd81d | 262 | } |
caaff562 | 263 | |
05a7f27a MJ |
264 | /* Clear the OF bit of Flags Register */ |
265 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
266 | if (flags < 0) | |
267 | return flags; | |
268 | ||
f1bd154d MR |
269 | err = i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, |
270 | flags & ~M41T80_FLAGS_OF); | |
271 | if (err < 0) { | |
05a7f27a | 272 | dev_err(&client->dev, "Unable to write flags register\n"); |
f1bd154d | 273 | return err; |
05a7f27a MJ |
274 | } |
275 | ||
f2b84ee8 | 276 | return err; |
caaff562 AN |
277 | } |
278 | ||
caaff562 AN |
279 | static int m41t80_rtc_proc(struct device *dev, struct seq_file *seq) |
280 | { | |
281 | struct i2c_client *client = to_i2c_client(dev); | |
282 | struct m41t80_data *clientdata = i2c_get_clientdata(client); | |
f1bd154d | 283 | int reg; |
caaff562 | 284 | |
3760f736 | 285 | if (clientdata->features & M41T80_FEATURE_BL) { |
caaff562 | 286 | reg = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); |
f1bd154d MR |
287 | if (reg < 0) |
288 | return reg; | |
caaff562 AN |
289 | seq_printf(seq, "battery\t\t: %s\n", |
290 | (reg & M41T80_FLAGS_BATT_LOW) ? "exhausted" : "ok"); | |
291 | } | |
292 | return 0; | |
293 | } | |
caaff562 | 294 | |
9c6dfed9 MJ |
295 | static int m41t80_alarm_irq_enable(struct device *dev, unsigned int enabled) |
296 | { | |
297 | struct i2c_client *client = to_i2c_client(dev); | |
298 | int flags, retval; | |
299 | ||
300 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
301 | if (flags < 0) | |
302 | return flags; | |
303 | ||
304 | if (enabled) | |
305 | flags |= M41T80_ALMON_AFE; | |
306 | else | |
307 | flags &= ~M41T80_ALMON_AFE; | |
308 | ||
309 | retval = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, flags); | |
310 | if (retval < 0) { | |
e89487fe | 311 | dev_err(dev, "Unable to enable alarm IRQ %d\n", retval); |
9c6dfed9 MJ |
312 | return retval; |
313 | } | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int m41t80_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
318 | { | |
319 | struct i2c_client *client = to_i2c_client(dev); | |
320 | u8 alarmvals[5]; | |
321 | int ret, err; | |
322 | ||
323 | alarmvals[0] = bin2bcd(alrm->time.tm_mon + 1); | |
324 | alarmvals[1] = bin2bcd(alrm->time.tm_mday); | |
325 | alarmvals[2] = bin2bcd(alrm->time.tm_hour); | |
326 | alarmvals[3] = bin2bcd(alrm->time.tm_min); | |
327 | alarmvals[4] = bin2bcd(alrm->time.tm_sec); | |
328 | ||
329 | /* Clear AF and AFE flags */ | |
330 | ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
331 | if (ret < 0) | |
332 | return ret; | |
333 | err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
334 | ret & ~(M41T80_ALMON_AFE)); | |
335 | if (err < 0) { | |
336 | dev_err(dev, "Unable to clear AFE bit\n"); | |
337 | return err; | |
338 | } | |
339 | ||
2de9261c GB |
340 | /* Keep SQWE bit value */ |
341 | alarmvals[0] |= (ret & M41T80_ALMON_SQWE); | |
342 | ||
9c6dfed9 MJ |
343 | ret = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); |
344 | if (ret < 0) | |
345 | return ret; | |
346 | ||
347 | err = i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, | |
348 | ret & ~(M41T80_FLAGS_AF)); | |
349 | if (err < 0) { | |
350 | dev_err(dev, "Unable to clear AF bit\n"); | |
351 | return err; | |
352 | } | |
353 | ||
354 | /* Write the alarm */ | |
355 | err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_ALARM_MON, | |
356 | 5, alarmvals); | |
357 | if (err) | |
358 | return err; | |
359 | ||
360 | /* Enable the alarm interrupt */ | |
361 | if (alrm->enabled) { | |
362 | alarmvals[0] |= M41T80_ALMON_AFE; | |
363 | err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
364 | alarmvals[0]); | |
365 | if (err) | |
366 | return err; | |
367 | } | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static int m41t80_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
373 | { | |
374 | struct i2c_client *client = to_i2c_client(dev); | |
375 | u8 alarmvals[5]; | |
376 | int flags, ret; | |
377 | ||
378 | ret = i2c_smbus_read_i2c_block_data(client, M41T80_REG_ALARM_MON, | |
379 | 5, alarmvals); | |
380 | if (ret != 5) | |
381 | return ret < 0 ? ret : -EIO; | |
382 | ||
383 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
384 | if (flags < 0) | |
385 | return flags; | |
386 | ||
387 | alrm->time.tm_sec = bcd2bin(alarmvals[4] & 0x7f); | |
388 | alrm->time.tm_min = bcd2bin(alarmvals[3] & 0x7f); | |
389 | alrm->time.tm_hour = bcd2bin(alarmvals[2] & 0x3f); | |
9c6dfed9 | 390 | alrm->time.tm_mday = bcd2bin(alarmvals[1] & 0x3f); |
3cc9ffbb | 391 | alrm->time.tm_mon = bcd2bin(alarmvals[0] & 0x3f) - 1; |
9c6dfed9 MJ |
392 | |
393 | alrm->enabled = !!(alarmvals[0] & M41T80_ALMON_AFE); | |
394 | alrm->pending = (flags & M41T80_FLAGS_AF) && alrm->enabled; | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
3948a866 | 399 | static const struct rtc_class_ops m41t80_rtc_ops = { |
caaff562 AN |
400 | .read_time = m41t80_rtc_read_time, |
401 | .set_time = m41t80_rtc_set_time, | |
caaff562 | 402 | .proc = m41t80_rtc_proc, |
3948a866 AB |
403 | .read_alarm = m41t80_read_alarm, |
404 | .set_alarm = m41t80_set_alarm, | |
405 | .alarm_irq_enable = m41t80_alarm_irq_enable, | |
caaff562 AN |
406 | }; |
407 | ||
ae036af8 SC |
408 | #ifdef CONFIG_PM_SLEEP |
409 | static int m41t80_suspend(struct device *dev) | |
410 | { | |
411 | struct i2c_client *client = to_i2c_client(dev); | |
412 | ||
413 | if (client->irq >= 0 && device_may_wakeup(dev)) | |
414 | enable_irq_wake(client->irq); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | static int m41t80_resume(struct device *dev) | |
420 | { | |
421 | struct i2c_client *client = to_i2c_client(dev); | |
422 | ||
423 | if (client->irq >= 0 && device_may_wakeup(dev)) | |
424 | disable_irq_wake(client->irq); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | #endif | |
429 | ||
430 | static SIMPLE_DEV_PM_OPS(m41t80_pm, m41t80_suspend, m41t80_resume); | |
431 | ||
1373e77b GB |
432 | #ifdef CONFIG_COMMON_CLK |
433 | #define sqw_to_m41t80_data(_hw) container_of(_hw, struct m41t80_data, sqw) | |
434 | ||
2cb90ed3 TK |
435 | static unsigned long m41t80_decode_freq(int setting) |
436 | { | |
437 | return (setting == 0) ? 0 : (setting == 1) ? M41T80_SQW_MAX_FREQ : | |
438 | M41T80_SQW_MAX_FREQ >> setting; | |
439 | } | |
440 | ||
441 | static unsigned long m41t80_get_freq(struct m41t80_data *m41t80) | |
1373e77b | 442 | { |
1373e77b GB |
443 | struct i2c_client *client = m41t80->client; |
444 | int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ? | |
445 | M41T80_REG_WDAY : M41T80_REG_SQW; | |
446 | int ret = i2c_smbus_read_byte_data(client, reg_sqw); | |
1373e77b GB |
447 | |
448 | if (ret < 0) | |
449 | return 0; | |
2cb90ed3 TK |
450 | return m41t80_decode_freq(ret >> 4); |
451 | } | |
1373e77b | 452 | |
2cb90ed3 TK |
453 | static unsigned long m41t80_sqw_recalc_rate(struct clk_hw *hw, |
454 | unsigned long parent_rate) | |
455 | { | |
456 | return sqw_to_m41t80_data(hw)->freq; | |
1373e77b GB |
457 | } |
458 | ||
459 | static long m41t80_sqw_round_rate(struct clk_hw *hw, unsigned long rate, | |
460 | unsigned long *prate) | |
461 | { | |
c8384bb0 TK |
462 | if (rate >= M41T80_SQW_MAX_FREQ) |
463 | return M41T80_SQW_MAX_FREQ; | |
464 | if (rate >= M41T80_SQW_MAX_FREQ / 4) | |
465 | return M41T80_SQW_MAX_FREQ / 4; | |
466 | if (!rate) | |
467 | return 0; | |
468 | return 1 << ilog2(rate); | |
1373e77b GB |
469 | } |
470 | ||
471 | static int m41t80_sqw_set_rate(struct clk_hw *hw, unsigned long rate, | |
472 | unsigned long parent_rate) | |
473 | { | |
474 | struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw); | |
475 | struct i2c_client *client = m41t80->client; | |
476 | int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ? | |
477 | M41T80_REG_WDAY : M41T80_REG_SQW; | |
478 | int reg, ret, val = 0; | |
479 | ||
05a03bf2 TK |
480 | if (rate >= M41T80_SQW_MAX_FREQ) |
481 | val = 1; | |
482 | else if (rate >= M41T80_SQW_MAX_FREQ / 4) | |
483 | val = 2; | |
484 | else if (rate) | |
485 | val = 15 - ilog2(rate); | |
1373e77b GB |
486 | |
487 | reg = i2c_smbus_read_byte_data(client, reg_sqw); | |
488 | if (reg < 0) | |
489 | return reg; | |
490 | ||
491 | reg = (reg & 0x0f) | (val << 4); | |
492 | ||
493 | ret = i2c_smbus_write_byte_data(client, reg_sqw, reg); | |
2cb90ed3 TK |
494 | if (!ret) |
495 | m41t80->freq = m41t80_decode_freq(val); | |
de6042d2 | 496 | return ret; |
1373e77b GB |
497 | } |
498 | ||
499 | static int m41t80_sqw_control(struct clk_hw *hw, bool enable) | |
500 | { | |
501 | struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw); | |
502 | struct i2c_client *client = m41t80->client; | |
503 | int ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
504 | ||
505 | if (ret < 0) | |
506 | return ret; | |
507 | ||
508 | if (enable) | |
509 | ret |= M41T80_ALMON_SQWE; | |
510 | else | |
511 | ret &= ~M41T80_ALMON_SQWE; | |
512 | ||
13bb1d78 TK |
513 | ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, ret); |
514 | if (!ret) | |
515 | m41t80->sqwe = enable; | |
516 | return ret; | |
1373e77b GB |
517 | } |
518 | ||
519 | static int m41t80_sqw_prepare(struct clk_hw *hw) | |
520 | { | |
521 | return m41t80_sqw_control(hw, 1); | |
522 | } | |
523 | ||
524 | static void m41t80_sqw_unprepare(struct clk_hw *hw) | |
525 | { | |
526 | m41t80_sqw_control(hw, 0); | |
527 | } | |
528 | ||
529 | static int m41t80_sqw_is_prepared(struct clk_hw *hw) | |
530 | { | |
13bb1d78 | 531 | return sqw_to_m41t80_data(hw)->sqwe; |
1373e77b GB |
532 | } |
533 | ||
534 | static const struct clk_ops m41t80_sqw_ops = { | |
535 | .prepare = m41t80_sqw_prepare, | |
536 | .unprepare = m41t80_sqw_unprepare, | |
537 | .is_prepared = m41t80_sqw_is_prepared, | |
538 | .recalc_rate = m41t80_sqw_recalc_rate, | |
539 | .round_rate = m41t80_sqw_round_rate, | |
540 | .set_rate = m41t80_sqw_set_rate, | |
541 | }; | |
542 | ||
543 | static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80) | |
544 | { | |
545 | struct i2c_client *client = m41t80->client; | |
546 | struct device_node *node = client->dev.of_node; | |
547 | struct clk *clk; | |
548 | struct clk_init_data init; | |
549 | int ret; | |
550 | ||
551 | /* First disable the clock */ | |
552 | ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
553 | if (ret < 0) | |
554 | return ERR_PTR(ret); | |
555 | ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
556 | ret & ~(M41T80_ALMON_SQWE)); | |
557 | if (ret < 0) | |
558 | return ERR_PTR(ret); | |
559 | ||
560 | init.name = "m41t80-sqw"; | |
561 | init.ops = &m41t80_sqw_ops; | |
562 | init.flags = 0; | |
563 | init.parent_names = NULL; | |
564 | init.num_parents = 0; | |
565 | m41t80->sqw.init = &init; | |
2cb90ed3 | 566 | m41t80->freq = m41t80_get_freq(m41t80); |
1373e77b GB |
567 | |
568 | /* optional override of the clockname */ | |
569 | of_property_read_string(node, "clock-output-names", &init.name); | |
570 | ||
571 | /* register the clock */ | |
572 | clk = clk_register(&client->dev, &m41t80->sqw); | |
573 | if (!IS_ERR(clk)) | |
574 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
575 | ||
576 | return clk; | |
577 | } | |
578 | #endif | |
579 | ||
617780d2 AN |
580 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
581 | /* | |
582 | ***************************************************************************** | |
583 | * | |
584 | * Watchdog Driver | |
585 | * | |
586 | ***************************************************************************** | |
587 | */ | |
76384f31 | 588 | static DEFINE_MUTEX(m41t80_rtc_mutex); |
617780d2 AN |
589 | static struct i2c_client *save_client; |
590 | ||
591 | /* Default margin */ | |
592 | #define WD_TIMO 60 /* 1..31 seconds */ | |
593 | ||
594 | static int wdt_margin = WD_TIMO; | |
595 | module_param(wdt_margin, int, 0); | |
596 | MODULE_PARM_DESC(wdt_margin, "Watchdog timeout in seconds (default 60s)"); | |
597 | ||
598 | static unsigned long wdt_is_open; | |
599 | static int boot_flag; | |
600 | ||
601 | /** | |
602 | * wdt_ping: | |
603 | * | |
604 | * Reload counter one with the watchdog timeout. We don't bother reloading | |
605 | * the cascade counter. | |
606 | */ | |
607 | static void wdt_ping(void) | |
608 | { | |
609 | unsigned char i2c_data[2]; | |
610 | struct i2c_msg msgs1[1] = { | |
611 | { | |
612 | .addr = save_client->addr, | |
613 | .flags = 0, | |
614 | .len = 2, | |
615 | .buf = i2c_data, | |
616 | }, | |
617 | }; | |
d3a126fc SF |
618 | struct m41t80_data *clientdata = i2c_get_clientdata(save_client); |
619 | ||
617780d2 AN |
620 | i2c_data[0] = 0x09; /* watchdog register */ |
621 | ||
622 | if (wdt_margin > 31) | |
623 | i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */ | |
624 | else | |
625 | /* | |
626 | * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02) | |
627 | */ | |
fc99b901 | 628 | i2c_data[1] = wdt_margin << 2 | 0x82; |
617780d2 | 629 | |
d3a126fc SF |
630 | /* |
631 | * M41T65 has three bits for watchdog resolution. Don't set bit 7, as | |
632 | * that would be an invalid resolution. | |
633 | */ | |
634 | if (clientdata->features & M41T80_FEATURE_WD) | |
635 | i2c_data[1] &= ~M41T80_WATCHDOG_RB2; | |
636 | ||
617780d2 AN |
637 | i2c_transfer(save_client->adapter, msgs1, 1); |
638 | } | |
639 | ||
640 | /** | |
641 | * wdt_disable: | |
642 | * | |
643 | * disables watchdog. | |
644 | */ | |
645 | static void wdt_disable(void) | |
646 | { | |
647 | unsigned char i2c_data[2], i2c_buf[0x10]; | |
648 | struct i2c_msg msgs0[2] = { | |
649 | { | |
650 | .addr = save_client->addr, | |
651 | .flags = 0, | |
652 | .len = 1, | |
653 | .buf = i2c_data, | |
654 | }, | |
655 | { | |
656 | .addr = save_client->addr, | |
657 | .flags = I2C_M_RD, | |
658 | .len = 1, | |
659 | .buf = i2c_buf, | |
660 | }, | |
661 | }; | |
662 | struct i2c_msg msgs1[1] = { | |
663 | { | |
664 | .addr = save_client->addr, | |
665 | .flags = 0, | |
666 | .len = 2, | |
667 | .buf = i2c_data, | |
668 | }, | |
669 | }; | |
670 | ||
671 | i2c_data[0] = 0x09; | |
672 | i2c_transfer(save_client->adapter, msgs0, 2); | |
673 | ||
674 | i2c_data[0] = 0x09; | |
675 | i2c_data[1] = 0x00; | |
676 | i2c_transfer(save_client->adapter, msgs1, 1); | |
677 | } | |
678 | ||
679 | /** | |
680 | * wdt_write: | |
681 | * @file: file handle to the watchdog | |
682 | * @buf: buffer to write (unused as data does not matter here | |
683 | * @count: count of bytes | |
684 | * @ppos: pointer to the position to write. No seeks allowed | |
685 | * | |
686 | * A write to a watchdog device is defined as a keepalive signal. Any | |
687 | * write of data will do, as we we don't define content meaning. | |
688 | */ | |
689 | static ssize_t wdt_write(struct file *file, const char __user *buf, | |
690 | size_t count, loff_t *ppos) | |
691 | { | |
617780d2 AN |
692 | if (count) { |
693 | wdt_ping(); | |
694 | return 1; | |
695 | } | |
696 | return 0; | |
697 | } | |
698 | ||
699 | static ssize_t wdt_read(struct file *file, char __user *buf, | |
700 | size_t count, loff_t *ppos) | |
701 | { | |
702 | return 0; | |
703 | } | |
704 | ||
705 | /** | |
706 | * wdt_ioctl: | |
617780d2 AN |
707 | * @file: file handle to the device |
708 | * @cmd: watchdog command | |
709 | * @arg: argument pointer | |
710 | * | |
711 | * The watchdog API defines a common set of functions for all watchdogs | |
712 | * according to their available features. We only actually usefully support | |
713 | * querying capabilities and current status. | |
714 | */ | |
55929332 | 715 | static int wdt_ioctl(struct file *file, unsigned int cmd, |
617780d2 AN |
716 | unsigned long arg) |
717 | { | |
718 | int new_margin, rv; | |
719 | static struct watchdog_info ident = { | |
720 | .options = WDIOF_POWERUNDER | WDIOF_KEEPALIVEPING | | |
721 | WDIOF_SETTIMEOUT, | |
722 | .firmware_version = 1, | |
723 | .identity = "M41T80 WTD" | |
724 | }; | |
725 | ||
726 | switch (cmd) { | |
727 | case WDIOC_GETSUPPORT: | |
728 | return copy_to_user((struct watchdog_info __user *)arg, &ident, | |
729 | sizeof(ident)) ? -EFAULT : 0; | |
730 | ||
731 | case WDIOC_GETSTATUS: | |
732 | case WDIOC_GETBOOTSTATUS: | |
733 | return put_user(boot_flag, (int __user *)arg); | |
734 | case WDIOC_KEEPALIVE: | |
735 | wdt_ping(); | |
736 | return 0; | |
737 | case WDIOC_SETTIMEOUT: | |
738 | if (get_user(new_margin, (int __user *)arg)) | |
739 | return -EFAULT; | |
740 | /* Arbitrary, can't find the card's limits */ | |
741 | if (new_margin < 1 || new_margin > 124) | |
742 | return -EINVAL; | |
743 | wdt_margin = new_margin; | |
744 | wdt_ping(); | |
df561f66 | 745 | fallthrough; |
617780d2 AN |
746 | case WDIOC_GETTIMEOUT: |
747 | return put_user(wdt_margin, (int __user *)arg); | |
748 | ||
749 | case WDIOC_SETOPTIONS: | |
750 | if (copy_from_user(&rv, (int __user *)arg, sizeof(int))) | |
751 | return -EFAULT; | |
752 | ||
753 | if (rv & WDIOS_DISABLECARD) { | |
a737e835 | 754 | pr_info("disable watchdog\n"); |
617780d2 AN |
755 | wdt_disable(); |
756 | } | |
757 | ||
758 | if (rv & WDIOS_ENABLECARD) { | |
a737e835 | 759 | pr_info("enable watchdog\n"); |
617780d2 AN |
760 | wdt_ping(); |
761 | } | |
762 | ||
763 | return -EINVAL; | |
764 | } | |
765 | return -ENOTTY; | |
766 | } | |
767 | ||
55929332 AB |
768 | static long wdt_unlocked_ioctl(struct file *file, unsigned int cmd, |
769 | unsigned long arg) | |
770 | { | |
771 | int ret; | |
772 | ||
613655fa | 773 | mutex_lock(&m41t80_rtc_mutex); |
55929332 | 774 | ret = wdt_ioctl(file, cmd, arg); |
613655fa | 775 | mutex_unlock(&m41t80_rtc_mutex); |
55929332 AB |
776 | |
777 | return ret; | |
778 | } | |
779 | ||
617780d2 AN |
780 | /** |
781 | * wdt_open: | |
782 | * @inode: inode of device | |
783 | * @file: file handle to device | |
784 | * | |
785 | */ | |
786 | static int wdt_open(struct inode *inode, struct file *file) | |
787 | { | |
6f24784f | 788 | if (iminor(inode) == WATCHDOG_MINOR) { |
613655fa | 789 | mutex_lock(&m41t80_rtc_mutex); |
41012735 | 790 | if (test_and_set_bit(0, &wdt_is_open)) { |
613655fa | 791 | mutex_unlock(&m41t80_rtc_mutex); |
617780d2 | 792 | return -EBUSY; |
41012735 | 793 | } |
617780d2 AN |
794 | /* |
795 | * Activate | |
796 | */ | |
797 | wdt_is_open = 1; | |
613655fa | 798 | mutex_unlock(&m41t80_rtc_mutex); |
c5bf68fe | 799 | return stream_open(inode, file); |
617780d2 AN |
800 | } |
801 | return -ENODEV; | |
802 | } | |
803 | ||
804 | /** | |
805 | * wdt_close: | |
806 | * @inode: inode to board | |
807 | * @file: file handle to board | |
808 | * | |
809 | */ | |
810 | static int wdt_release(struct inode *inode, struct file *file) | |
811 | { | |
6f24784f | 812 | if (iminor(inode) == WATCHDOG_MINOR) |
617780d2 AN |
813 | clear_bit(0, &wdt_is_open); |
814 | return 0; | |
815 | } | |
816 | ||
817 | /** | |
818 | * notify_sys: | |
819 | * @this: our notifier block | |
820 | * @code: the event being reported | |
821 | * @unused: unused | |
822 | * | |
823 | * Our notifier is called on system shutdowns. We want to turn the card | |
824 | * off at reboot otherwise the machine will reboot again during memory | |
825 | * test or worse yet during the following fsck. This would suck, in fact | |
826 | * trust me - if it happens it does suck. | |
827 | */ | |
828 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |
829 | void *unused) | |
830 | { | |
831 | if (code == SYS_DOWN || code == SYS_HALT) | |
832 | /* Disable Watchdog */ | |
833 | wdt_disable(); | |
834 | return NOTIFY_DONE; | |
835 | } | |
836 | ||
837 | static const struct file_operations wdt_fops = { | |
838 | .owner = THIS_MODULE, | |
839 | .read = wdt_read, | |
55929332 | 840 | .unlocked_ioctl = wdt_unlocked_ioctl, |
b6dfb247 | 841 | .compat_ioctl = compat_ptr_ioctl, |
617780d2 AN |
842 | .write = wdt_write, |
843 | .open = wdt_open, | |
844 | .release = wdt_release, | |
6038f373 | 845 | .llseek = no_llseek, |
617780d2 AN |
846 | }; |
847 | ||
848 | static struct miscdevice wdt_dev = { | |
849 | .minor = WATCHDOG_MINOR, | |
850 | .name = "watchdog", | |
851 | .fops = &wdt_fops, | |
852 | }; | |
853 | ||
854 | /* | |
855 | * The WDT card needs to learn about soft shutdowns in order to | |
856 | * turn the timebomb registers off. | |
857 | */ | |
858 | static struct notifier_block wdt_notifier = { | |
859 | .notifier_call = wdt_notify_sys, | |
860 | }; | |
861 | #endif /* CONFIG_RTC_DRV_M41T80_WDT */ | |
862 | ||
caaff562 AN |
863 | /* |
864 | ***************************************************************************** | |
865 | * | |
866 | * Driver Interface | |
867 | * | |
868 | ***************************************************************************** | |
869 | */ | |
ef6b3125 | 870 | |
d2653e92 JD |
871 | static int m41t80_probe(struct i2c_client *client, |
872 | const struct i2c_device_id *id) | |
caaff562 | 873 | { |
e5108df4 | 874 | struct i2c_adapter *adapter = client->adapter; |
3760f736 | 875 | int rc = 0; |
caaff562 | 876 | struct rtc_time tm; |
9c6dfed9 | 877 | struct m41t80_data *m41t80_data = NULL; |
d4473b9b | 878 | bool wakeup_source = false; |
caaff562 | 879 | |
f2b84ee8 MJ |
880 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK | |
881 | I2C_FUNC_SMBUS_BYTE_DATA)) { | |
882 | dev_err(&adapter->dev, "doesn't support I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK\n"); | |
c67fedfa | 883 | return -ENODEV; |
f2b84ee8 | 884 | } |
caaff562 | 885 | |
9c6dfed9 MJ |
886 | m41t80_data = devm_kzalloc(&client->dev, sizeof(*m41t80_data), |
887 | GFP_KERNEL); | |
888 | if (!m41t80_data) | |
c67fedfa | 889 | return -ENOMEM; |
caaff562 | 890 | |
1373e77b | 891 | m41t80_data->client = client; |
eb235c56 JMC |
892 | if (client->dev.of_node) |
893 | m41t80_data->features = (unsigned long) | |
894 | of_device_get_match_data(&client->dev); | |
895 | else | |
896 | m41t80_data->features = id->driver_data; | |
9c6dfed9 MJ |
897 | i2c_set_clientdata(client, m41t80_data); |
898 | ||
10d0c768 AB |
899 | m41t80_data->rtc = devm_rtc_allocate_device(&client->dev); |
900 | if (IS_ERR(m41t80_data->rtc)) | |
901 | return PTR_ERR(m41t80_data->rtc); | |
902 | ||
d4473b9b EC |
903 | #ifdef CONFIG_OF |
904 | wakeup_source = of_property_read_bool(client->dev.of_node, | |
905 | "wakeup-source"); | |
906 | #endif | |
9c6dfed9 MJ |
907 | if (client->irq > 0) { |
908 | rc = devm_request_threaded_irq(&client->dev, client->irq, | |
909 | NULL, m41t80_handle_irq, | |
910 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
911 | "m41t80", client); | |
912 | if (rc) { | |
913 | dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); | |
914 | client->irq = 0; | |
d4473b9b | 915 | wakeup_source = false; |
9c6dfed9 MJ |
916 | } |
917 | } | |
3948a866 | 918 | if (client->irq > 0 || wakeup_source) |
d4473b9b | 919 | device_init_wakeup(&client->dev, true); |
3948a866 AB |
920 | else |
921 | clear_bit(RTC_FEATURE_ALARM, m41t80_data->rtc->features); | |
a015dbc1 | 922 | |
10d0c768 | 923 | m41t80_data->rtc->ops = &m41t80_rtc_ops; |
cf79e7c3 AB |
924 | m41t80_data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; |
925 | m41t80_data->rtc->range_max = RTC_TIMESTAMP_END_2099; | |
caaff562 | 926 | |
d4473b9b EC |
927 | if (client->irq <= 0) { |
928 | /* We cannot support UIE mode if we do not have an IRQ line */ | |
10d0c768 | 929 | m41t80_data->rtc->uie_unsupported = 1; |
d4473b9b | 930 | } |
caaff562 AN |
931 | |
932 | /* Make sure HT (Halt Update) bit is cleared */ | |
933 | rc = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_HOUR); | |
caaff562 | 934 | |
c67fedfa | 935 | if (rc >= 0 && rc & M41T80_ALHOUR_HT) { |
9c6dfed9 | 936 | if (m41t80_data->features & M41T80_FEATURE_HT) { |
e2c8e1a9 | 937 | m41t80_rtc_read_time(&client->dev, &tm); |
caaff562 | 938 | dev_info(&client->dev, "HT bit was set!\n"); |
22b844ae | 939 | dev_info(&client->dev, "Power Down at %ptR\n", &tm); |
caaff562 | 940 | } |
c67fedfa | 941 | rc = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_HOUR, |
fc99b901 | 942 | rc & ~M41T80_ALHOUR_HT); |
c67fedfa WS |
943 | } |
944 | ||
945 | if (rc < 0) { | |
946 | dev_err(&client->dev, "Can't clear HT bit\n"); | |
85d77047 | 947 | return rc; |
caaff562 AN |
948 | } |
949 | ||
950 | /* Make sure ST (stop) bit is cleared */ | |
951 | rc = i2c_smbus_read_byte_data(client, M41T80_REG_SEC); | |
caaff562 | 952 | |
c67fedfa WS |
953 | if (rc >= 0 && rc & M41T80_SEC_ST) |
954 | rc = i2c_smbus_write_byte_data(client, M41T80_REG_SEC, | |
fc99b901 | 955 | rc & ~M41T80_SEC_ST); |
c67fedfa WS |
956 | if (rc < 0) { |
957 | dev_err(&client->dev, "Can't clear ST bit\n"); | |
85d77047 | 958 | return rc; |
caaff562 AN |
959 | } |
960 | ||
617780d2 | 961 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
9c6dfed9 | 962 | if (m41t80_data->features & M41T80_FEATURE_HT) { |
417607d0 | 963 | save_client = client; |
617780d2 AN |
964 | rc = misc_register(&wdt_dev); |
965 | if (rc) | |
c67fedfa | 966 | return rc; |
617780d2 AN |
967 | rc = register_reboot_notifier(&wdt_notifier); |
968 | if (rc) { | |
969 | misc_deregister(&wdt_dev); | |
c67fedfa | 970 | return rc; |
617780d2 | 971 | } |
617780d2 | 972 | } |
1373e77b GB |
973 | #endif |
974 | #ifdef CONFIG_COMMON_CLK | |
975 | if (m41t80_data->features & M41T80_FEATURE_SQ) | |
976 | m41t80_sqw_register_clk(m41t80_data); | |
617780d2 | 977 | #endif |
10d0c768 | 978 | |
fdcfd854 | 979 | rc = devm_rtc_register_device(m41t80_data->rtc); |
10d0c768 AB |
980 | if (rc) |
981 | return rc; | |
982 | ||
caaff562 | 983 | return 0; |
caaff562 AN |
984 | } |
985 | ||
986 | static int m41t80_remove(struct i2c_client *client) | |
987 | { | |
4ebabb78 | 988 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
caaff562 | 989 | struct m41t80_data *clientdata = i2c_get_clientdata(client); |
caaff562 | 990 | |
3760f736 | 991 | if (clientdata->features & M41T80_FEATURE_HT) { |
617780d2 AN |
992 | misc_deregister(&wdt_dev); |
993 | unregister_reboot_notifier(&wdt_notifier); | |
994 | } | |
995 | #endif | |
caaff562 AN |
996 | |
997 | return 0; | |
998 | } | |
999 | ||
1000 | static struct i2c_driver m41t80_driver = { | |
1001 | .driver = { | |
afe1ab4d | 1002 | .name = "rtc-m41t80", |
eb235c56 | 1003 | .of_match_table = of_match_ptr(m41t80_of_match), |
ae036af8 | 1004 | .pm = &m41t80_pm, |
caaff562 AN |
1005 | }, |
1006 | .probe = m41t80_probe, | |
1007 | .remove = m41t80_remove, | |
3760f736 | 1008 | .id_table = m41t80_id, |
caaff562 AN |
1009 | }; |
1010 | ||
0abc9201 | 1011 | module_i2c_driver(m41t80_driver); |
caaff562 AN |
1012 | |
1013 | MODULE_AUTHOR("Alexander Bigga <ab@mycable.de>"); | |
1014 | MODULE_DESCRIPTION("ST Microelectronics M41T80 series RTC I2C Client Driver"); | |
1015 | MODULE_LICENSE("GPL"); |