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CommitLineData
caaff562
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1/*
2 * I2C client/driver for the ST M41T80 family of i2c rtc chips.
3 *
4 * Author: Alexander Bigga <ab@mycable.de>
5 *
6 * Based on m41t00.c by Mark A. Greer <mgreer@mvista.com>
7 *
8 * 2006 (c) mycable GmbH
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
a737e835
JP
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
35aa64f3 18#include <linux/bcd.h>
1373e77b 19#include <linux/clk-provider.h>
35aa64f3 20#include <linux/i2c.h>
caaff562 21#include <linux/init.h>
9fb1f68d 22#include <linux/kernel.h>
35aa64f3 23#include <linux/module.h>
eb235c56 24#include <linux/of_device.h>
35aa64f3 25#include <linux/rtc.h>
caaff562 26#include <linux/slab.h>
613655fa 27#include <linux/mutex.h>
caaff562 28#include <linux/string.h>
617780d2 29#ifdef CONFIG_RTC_DRV_M41T80_WDT
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30#include <linux/fs.h>
31#include <linux/ioctl.h>
35aa64f3
MR
32#include <linux/miscdevice.h>
33#include <linux/reboot.h>
34#include <linux/watchdog.h>
617780d2 35#endif
caaff562 36
f2b84ee8
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37#define M41T80_REG_SSEC 0x00
38#define M41T80_REG_SEC 0x01
39#define M41T80_REG_MIN 0x02
40#define M41T80_REG_HOUR 0x03
41#define M41T80_REG_WDAY 0x04
42#define M41T80_REG_DAY 0x05
43#define M41T80_REG_MON 0x06
44#define M41T80_REG_YEAR 0x07
45#define M41T80_REG_ALARM_MON 0x0a
46#define M41T80_REG_ALARM_DAY 0x0b
47#define M41T80_REG_ALARM_HOUR 0x0c
48#define M41T80_REG_ALARM_MIN 0x0d
49#define M41T80_REG_ALARM_SEC 0x0e
50#define M41T80_REG_FLAGS 0x0f
51#define M41T80_REG_SQW 0x13
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52
53#define M41T80_DATETIME_REG_SIZE (M41T80_REG_YEAR + 1)
54#define M41T80_ALARM_REG_SIZE \
55 (M41T80_REG_ALARM_SEC + 1 - M41T80_REG_ALARM_MON)
56
1373e77b
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57#define M41T80_SQW_MAX_FREQ 32768
58
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59#define M41T80_SEC_ST BIT(7) /* ST: Stop Bit */
60#define M41T80_ALMON_AFE BIT(7) /* AFE: AF Enable Bit */
61#define M41T80_ALMON_SQWE BIT(6) /* SQWE: SQW Enable Bit */
62#define M41T80_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */
05a7f27a 63#define M41T80_FLAGS_OF BIT(2) /* OF: Oscillator Failure Bit */
54339f3b
MJ
64#define M41T80_FLAGS_AF BIT(6) /* AF: Alarm Flag Bit */
65#define M41T80_FLAGS_BATT_LOW BIT(4) /* BL: Battery Low Bit */
66#define M41T80_WATCHDOG_RB2 BIT(7) /* RB: Watchdog resolution */
67#define M41T80_WATCHDOG_RB1 BIT(1) /* RB: Watchdog resolution */
68#define M41T80_WATCHDOG_RB0 BIT(0) /* RB: Watchdog resolution */
caaff562 69
54339f3b
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70#define M41T80_FEATURE_HT BIT(0) /* Halt feature */
71#define M41T80_FEATURE_BL BIT(1) /* Battery low indicator */
72#define M41T80_FEATURE_SQ BIT(2) /* Squarewave feature */
73#define M41T80_FEATURE_WD BIT(3) /* Extra watchdog resolution */
74#define M41T80_FEATURE_SQ_ALT BIT(4) /* RSx bits are in reg 4 */
caaff562 75
613655fa 76static DEFINE_MUTEX(m41t80_rtc_mutex);
3760f736 77static const struct i2c_device_id m41t80_id[] = {
f30281f4 78 { "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT },
d3a126fc
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79 { "m41t65", M41T80_FEATURE_HT | M41T80_FEATURE_WD },
80 { "m41t80", M41T80_FEATURE_SQ },
81 { "m41t81", M41T80_FEATURE_HT | M41T80_FEATURE_SQ},
82 { "m41t81s", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
83 { "m41t82", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
84 { "m41t83", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
85 { "m41st84", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
86 { "m41st85", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
87 { "m41st87", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ },
6b1a5235 88 { "rv4162", M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT },
3760f736 89 { }
caaff562 90};
3760f736 91MODULE_DEVICE_TABLE(i2c, m41t80_id);
caaff562 92
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93static const struct of_device_id m41t80_of_match[] = {
94 {
95 .compatible = "st,m41t62",
96 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT)
97 },
98 {
99 .compatible = "st,m41t65",
100 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_WD)
101 },
102 {
103 .compatible = "st,m41t80",
104 .data = (void *)(M41T80_FEATURE_SQ)
105 },
106 {
107 .compatible = "st,m41t81",
108 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_SQ)
109 },
110 {
111 .compatible = "st,m41t81s",
112 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
113 },
114 {
115 .compatible = "st,m41t82",
116 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
117 },
118 {
119 .compatible = "st,m41t83",
120 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
121 },
122 {
123 .compatible = "st,m41t84",
124 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
125 },
126 {
127 .compatible = "st,m41t85",
128 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
129 },
130 {
131 .compatible = "st,m41t87",
132 .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ)
133 },
a897bf13
AB
134 {
135 .compatible = "microcrystal,rv4162",
136 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT)
137 },
138 /* DT compatibility only, do not use compatibles below: */
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JMC
139 {
140 .compatible = "st,rv4162",
141 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT)
142 },
143 {
144 .compatible = "rv4162",
145 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT)
146 },
147 { }
148};
149MODULE_DEVICE_TABLE(of, m41t80_of_match);
150
caaff562 151struct m41t80_data {
eb235c56 152 unsigned long features;
1373e77b 153 struct i2c_client *client;
caaff562 154 struct rtc_device *rtc;
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155#ifdef CONFIG_COMMON_CLK
156 struct clk_hw sqw;
157#endif
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158};
159
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160static irqreturn_t m41t80_handle_irq(int irq, void *dev_id)
161{
162 struct i2c_client *client = dev_id;
163 struct m41t80_data *m41t80 = i2c_get_clientdata(client);
164 struct mutex *lock = &m41t80->rtc->ops_lock;
165 unsigned long events = 0;
166 int flags, flags_afe;
167
168 mutex_lock(lock);
169
170 flags_afe = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
171 if (flags_afe < 0) {
172 mutex_unlock(lock);
173 return IRQ_NONE;
174 }
175
176 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
177 if (flags <= 0) {
178 mutex_unlock(lock);
179 return IRQ_NONE;
180 }
181
182 if (flags & M41T80_FLAGS_AF) {
183 flags &= ~M41T80_FLAGS_AF;
184 flags_afe &= ~M41T80_ALMON_AFE;
185 events |= RTC_AF;
186 }
187
188 if (events) {
189 rtc_update_irq(m41t80->rtc, 1, events);
190 i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, flags);
191 i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
192 flags_afe);
193 }
194
195 mutex_unlock(lock);
196
197 return IRQ_HANDLED;
198}
199
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200static int m41t80_get_datetime(struct i2c_client *client,
201 struct rtc_time *tm)
202{
f2b84ee8 203 unsigned char buf[8];
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204 int err, flags;
205
206 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
207 if (flags < 0)
208 return flags;
209
210 if (flags & M41T80_FLAGS_OF) {
211 dev_err(&client->dev, "Oscillator failure, data is invalid.\n");
212 return -EINVAL;
213 }
caaff562 214
f2b84ee8
MJ
215 err = i2c_smbus_read_i2c_block_data(client, M41T80_REG_SSEC,
216 sizeof(buf), buf);
217 if (err < 0) {
218 dev_err(&client->dev, "Unable to read date\n");
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219 return -EIO;
220 }
221
fe20ba70
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222 tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f);
223 tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f);
224 tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f);
225 tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f);
caaff562 226 tm->tm_wday = buf[M41T80_REG_WDAY] & 0x07;
fe20ba70 227 tm->tm_mon = bcd2bin(buf[M41T80_REG_MON] & 0x1f) - 1;
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228
229 /* assume 20YY not 19YY, and ignore the Century Bit */
fe20ba70 230 tm->tm_year = bcd2bin(buf[M41T80_REG_YEAR]) + 100;
b485fe5e 231 return rtc_valid_tm(tm);
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232}
233
234/* Sets the given date and time to the real time clock. */
235static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm)
236{
0f546b05 237 struct m41t80_data *clientdata = i2c_get_clientdata(client);
f2b84ee8 238 unsigned char buf[8];
05a7f27a 239 int err, flags;
caaff562 240
f2b84ee8
MJ
241 if (tm->tm_year < 100 || tm->tm_year > 199)
242 return -EINVAL;
caaff562 243
caaff562 244 buf[M41T80_REG_SSEC] = 0;
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MJ
245 buf[M41T80_REG_SEC] = bin2bcd(tm->tm_sec);
246 buf[M41T80_REG_MIN] = bin2bcd(tm->tm_min);
247 buf[M41T80_REG_HOUR] = bin2bcd(tm->tm_hour);
248 buf[M41T80_REG_DAY] = bin2bcd(tm->tm_mday);
249 buf[M41T80_REG_MON] = bin2bcd(tm->tm_mon + 1);
250 buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year - 100);
251 buf[M41T80_REG_WDAY] = tm->tm_wday;
252
0f546b05
GB
253 /* If the square wave output is controlled in the weekday register */
254 if (clientdata->features & M41T80_FEATURE_SQ_ALT) {
255 int val;
256
257 val = i2c_smbus_read_byte_data(client, M41T80_REG_WDAY);
258 if (val < 0)
259 return val;
260
261 buf[M41T80_REG_WDAY] |= (val & 0xf0);
262 }
263
f2b84ee8
MJ
264 err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_SSEC,
265 sizeof(buf), buf);
266 if (err < 0) {
267 dev_err(&client->dev, "Unable to write to date registers\n");
268 return err;
bcebd81d 269 }
caaff562 270
05a7f27a
MJ
271 /* Clear the OF bit of Flags Register */
272 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
273 if (flags < 0)
274 return flags;
275
276 if (i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS,
277 flags & ~M41T80_FLAGS_OF)) {
278 dev_err(&client->dev, "Unable to write flags register\n");
279 return -EIO;
280 }
281
f2b84ee8 282 return err;
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283}
284
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285static int m41t80_rtc_proc(struct device *dev, struct seq_file *seq)
286{
287 struct i2c_client *client = to_i2c_client(dev);
288 struct m41t80_data *clientdata = i2c_get_clientdata(client);
289 u8 reg;
290
3760f736 291 if (clientdata->features & M41T80_FEATURE_BL) {
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292 reg = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
293 seq_printf(seq, "battery\t\t: %s\n",
294 (reg & M41T80_FLAGS_BATT_LOW) ? "exhausted" : "ok");
295 }
296 return 0;
297}
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298
299static int m41t80_rtc_read_time(struct device *dev, struct rtc_time *tm)
300{
301 return m41t80_get_datetime(to_i2c_client(dev), tm);
302}
303
304static int m41t80_rtc_set_time(struct device *dev, struct rtc_time *tm)
305{
306 return m41t80_set_datetime(to_i2c_client(dev), tm);
307}
308
9c6dfed9
MJ
309static int m41t80_alarm_irq_enable(struct device *dev, unsigned int enabled)
310{
311 struct i2c_client *client = to_i2c_client(dev);
312 int flags, retval;
313
314 flags = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
315 if (flags < 0)
316 return flags;
317
318 if (enabled)
319 flags |= M41T80_ALMON_AFE;
320 else
321 flags &= ~M41T80_ALMON_AFE;
322
323 retval = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, flags);
324 if (retval < 0) {
e89487fe 325 dev_err(dev, "Unable to enable alarm IRQ %d\n", retval);
9c6dfed9
MJ
326 return retval;
327 }
328 return 0;
329}
330
331static int m41t80_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
332{
333 struct i2c_client *client = to_i2c_client(dev);
334 u8 alarmvals[5];
335 int ret, err;
336
337 alarmvals[0] = bin2bcd(alrm->time.tm_mon + 1);
338 alarmvals[1] = bin2bcd(alrm->time.tm_mday);
339 alarmvals[2] = bin2bcd(alrm->time.tm_hour);
340 alarmvals[3] = bin2bcd(alrm->time.tm_min);
341 alarmvals[4] = bin2bcd(alrm->time.tm_sec);
342
343 /* Clear AF and AFE flags */
344 ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
345 if (ret < 0)
346 return ret;
347 err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
348 ret & ~(M41T80_ALMON_AFE));
349 if (err < 0) {
350 dev_err(dev, "Unable to clear AFE bit\n");
351 return err;
352 }
353
2de9261c
GB
354 /* Keep SQWE bit value */
355 alarmvals[0] |= (ret & M41T80_ALMON_SQWE);
356
9c6dfed9
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357 ret = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
358 if (ret < 0)
359 return ret;
360
361 err = i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS,
362 ret & ~(M41T80_FLAGS_AF));
363 if (err < 0) {
364 dev_err(dev, "Unable to clear AF bit\n");
365 return err;
366 }
367
368 /* Write the alarm */
369 err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_ALARM_MON,
370 5, alarmvals);
371 if (err)
372 return err;
373
374 /* Enable the alarm interrupt */
375 if (alrm->enabled) {
376 alarmvals[0] |= M41T80_ALMON_AFE;
377 err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
378 alarmvals[0]);
379 if (err)
380 return err;
381 }
382
383 return 0;
384}
385
386static int m41t80_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
387{
388 struct i2c_client *client = to_i2c_client(dev);
389 u8 alarmvals[5];
390 int flags, ret;
391
392 ret = i2c_smbus_read_i2c_block_data(client, M41T80_REG_ALARM_MON,
393 5, alarmvals);
394 if (ret != 5)
395 return ret < 0 ? ret : -EIO;
396
397 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
398 if (flags < 0)
399 return flags;
400
401 alrm->time.tm_sec = bcd2bin(alarmvals[4] & 0x7f);
402 alrm->time.tm_min = bcd2bin(alarmvals[3] & 0x7f);
403 alrm->time.tm_hour = bcd2bin(alarmvals[2] & 0x3f);
9c6dfed9
MJ
404 alrm->time.tm_mday = bcd2bin(alarmvals[1] & 0x3f);
405 alrm->time.tm_mon = bcd2bin(alarmvals[0] & 0x3f);
9c6dfed9
MJ
406
407 alrm->enabled = !!(alarmvals[0] & M41T80_ALMON_AFE);
408 alrm->pending = (flags & M41T80_FLAGS_AF) && alrm->enabled;
409
410 return 0;
411}
412
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413static struct rtc_class_ops m41t80_rtc_ops = {
414 .read_time = m41t80_rtc_read_time,
415 .set_time = m41t80_rtc_set_time,
caaff562 416 .proc = m41t80_rtc_proc,
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AN
417};
418
ae036af8
SC
419#ifdef CONFIG_PM_SLEEP
420static int m41t80_suspend(struct device *dev)
421{
422 struct i2c_client *client = to_i2c_client(dev);
423
424 if (client->irq >= 0 && device_may_wakeup(dev))
425 enable_irq_wake(client->irq);
426
427 return 0;
428}
429
430static int m41t80_resume(struct device *dev)
431{
432 struct i2c_client *client = to_i2c_client(dev);
433
434 if (client->irq >= 0 && device_may_wakeup(dev))
435 disable_irq_wake(client->irq);
436
437 return 0;
438}
439#endif
440
441static SIMPLE_DEV_PM_OPS(m41t80_pm, m41t80_suspend, m41t80_resume);
442
ef6b3125
MJ
443static ssize_t flags_show(struct device *dev,
444 struct device_attribute *attr, char *buf)
caaff562
AN
445{
446 struct i2c_client *client = to_i2c_client(dev);
447 int val;
448
449 val = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS);
450 if (val < 0)
85d77047 451 return val;
caaff562
AN
452 return sprintf(buf, "%#x\n", val);
453}
ef6b3125 454static DEVICE_ATTR_RO(flags);
caaff562 455
caaff562
AN
456static struct attribute *attrs[] = {
457 &dev_attr_flags.attr,
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458 NULL,
459};
fc99b901 460
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461static struct attribute_group attr_group = {
462 .attrs = attrs,
463};
464
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GB
465#ifdef CONFIG_COMMON_CLK
466#define sqw_to_m41t80_data(_hw) container_of(_hw, struct m41t80_data, sqw)
467
468static unsigned long m41t80_sqw_recalc_rate(struct clk_hw *hw,
469 unsigned long parent_rate)
470{
471 struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw);
472 struct i2c_client *client = m41t80->client;
473 int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ?
474 M41T80_REG_WDAY : M41T80_REG_SQW;
475 int ret = i2c_smbus_read_byte_data(client, reg_sqw);
476 unsigned long val = M41T80_SQW_MAX_FREQ;
477
478 if (ret < 0)
479 return 0;
480
481 ret >>= 4;
482 if (ret == 0)
483 val = 0;
484 else if (ret > 1)
485 val = val / (1 << ret);
486
487 return val;
488}
489
490static long m41t80_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
491 unsigned long *prate)
492{
493 int i, freq = M41T80_SQW_MAX_FREQ;
494
495 if (freq <= rate)
496 return freq;
497
498 for (i = 2; i <= ilog2(M41T80_SQW_MAX_FREQ); i++) {
499 freq /= 1 << i;
500 if (freq <= rate)
501 return freq;
502 }
503
504 return 0;
505}
506
507static int m41t80_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
508 unsigned long parent_rate)
509{
510 struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw);
511 struct i2c_client *client = m41t80->client;
512 int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ?
513 M41T80_REG_WDAY : M41T80_REG_SQW;
514 int reg, ret, val = 0;
515
516 if (rate) {
517 if (!is_power_of_2(rate))
518 return -EINVAL;
519 val = ilog2(rate);
520 if (val == ilog2(M41T80_SQW_MAX_FREQ))
521 val = 1;
522 else if (val < (ilog2(M41T80_SQW_MAX_FREQ) - 1))
523 val = ilog2(M41T80_SQW_MAX_FREQ) - val;
524 else
525 return -EINVAL;
526 }
527
528 reg = i2c_smbus_read_byte_data(client, reg_sqw);
529 if (reg < 0)
530 return reg;
531
532 reg = (reg & 0x0f) | (val << 4);
533
534 ret = i2c_smbus_write_byte_data(client, reg_sqw, reg);
535 if (ret < 0)
536 return ret;
537
538 return -EINVAL;
539}
540
541static int m41t80_sqw_control(struct clk_hw *hw, bool enable)
542{
543 struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw);
544 struct i2c_client *client = m41t80->client;
545 int ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
546
547 if (ret < 0)
548 return ret;
549
550 if (enable)
551 ret |= M41T80_ALMON_SQWE;
552 else
553 ret &= ~M41T80_ALMON_SQWE;
554
555 return i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, ret);
556}
557
558static int m41t80_sqw_prepare(struct clk_hw *hw)
559{
560 return m41t80_sqw_control(hw, 1);
561}
562
563static void m41t80_sqw_unprepare(struct clk_hw *hw)
564{
565 m41t80_sqw_control(hw, 0);
566}
567
568static int m41t80_sqw_is_prepared(struct clk_hw *hw)
569{
570 struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw);
571 struct i2c_client *client = m41t80->client;
572 int ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
573
574 if (ret < 0)
575 return ret;
576
577 return !!(ret & M41T80_ALMON_SQWE);
578}
579
580static const struct clk_ops m41t80_sqw_ops = {
581 .prepare = m41t80_sqw_prepare,
582 .unprepare = m41t80_sqw_unprepare,
583 .is_prepared = m41t80_sqw_is_prepared,
584 .recalc_rate = m41t80_sqw_recalc_rate,
585 .round_rate = m41t80_sqw_round_rate,
586 .set_rate = m41t80_sqw_set_rate,
587};
588
589static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80)
590{
591 struct i2c_client *client = m41t80->client;
592 struct device_node *node = client->dev.of_node;
593 struct clk *clk;
594 struct clk_init_data init;
595 int ret;
596
597 /* First disable the clock */
598 ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON);
599 if (ret < 0)
600 return ERR_PTR(ret);
601 ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON,
602 ret & ~(M41T80_ALMON_SQWE));
603 if (ret < 0)
604 return ERR_PTR(ret);
605
606 init.name = "m41t80-sqw";
607 init.ops = &m41t80_sqw_ops;
608 init.flags = 0;
609 init.parent_names = NULL;
610 init.num_parents = 0;
611 m41t80->sqw.init = &init;
612
613 /* optional override of the clockname */
614 of_property_read_string(node, "clock-output-names", &init.name);
615
616 /* register the clock */
617 clk = clk_register(&client->dev, &m41t80->sqw);
618 if (!IS_ERR(clk))
619 of_clk_add_provider(node, of_clk_src_simple_get, clk);
620
621 return clk;
622}
623#endif
624
617780d2
AN
625#ifdef CONFIG_RTC_DRV_M41T80_WDT
626/*
627 *****************************************************************************
628 *
629 * Watchdog Driver
630 *
631 *****************************************************************************
632 */
633static struct i2c_client *save_client;
634
635/* Default margin */
636#define WD_TIMO 60 /* 1..31 seconds */
637
638static int wdt_margin = WD_TIMO;
639module_param(wdt_margin, int, 0);
640MODULE_PARM_DESC(wdt_margin, "Watchdog timeout in seconds (default 60s)");
641
642static unsigned long wdt_is_open;
643static int boot_flag;
644
645/**
646 * wdt_ping:
647 *
648 * Reload counter one with the watchdog timeout. We don't bother reloading
649 * the cascade counter.
650 */
651static void wdt_ping(void)
652{
653 unsigned char i2c_data[2];
654 struct i2c_msg msgs1[1] = {
655 {
656 .addr = save_client->addr,
657 .flags = 0,
658 .len = 2,
659 .buf = i2c_data,
660 },
661 };
d3a126fc
SF
662 struct m41t80_data *clientdata = i2c_get_clientdata(save_client);
663
617780d2
AN
664 i2c_data[0] = 0x09; /* watchdog register */
665
666 if (wdt_margin > 31)
667 i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */
668 else
669 /*
670 * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02)
671 */
fc99b901 672 i2c_data[1] = wdt_margin << 2 | 0x82;
617780d2 673
d3a126fc
SF
674 /*
675 * M41T65 has three bits for watchdog resolution. Don't set bit 7, as
676 * that would be an invalid resolution.
677 */
678 if (clientdata->features & M41T80_FEATURE_WD)
679 i2c_data[1] &= ~M41T80_WATCHDOG_RB2;
680
617780d2
AN
681 i2c_transfer(save_client->adapter, msgs1, 1);
682}
683
684/**
685 * wdt_disable:
686 *
687 * disables watchdog.
688 */
689static void wdt_disable(void)
690{
691 unsigned char i2c_data[2], i2c_buf[0x10];
692 struct i2c_msg msgs0[2] = {
693 {
694 .addr = save_client->addr,
695 .flags = 0,
696 .len = 1,
697 .buf = i2c_data,
698 },
699 {
700 .addr = save_client->addr,
701 .flags = I2C_M_RD,
702 .len = 1,
703 .buf = i2c_buf,
704 },
705 };
706 struct i2c_msg msgs1[1] = {
707 {
708 .addr = save_client->addr,
709 .flags = 0,
710 .len = 2,
711 .buf = i2c_data,
712 },
713 };
714
715 i2c_data[0] = 0x09;
716 i2c_transfer(save_client->adapter, msgs0, 2);
717
718 i2c_data[0] = 0x09;
719 i2c_data[1] = 0x00;
720 i2c_transfer(save_client->adapter, msgs1, 1);
721}
722
723/**
724 * wdt_write:
725 * @file: file handle to the watchdog
726 * @buf: buffer to write (unused as data does not matter here
727 * @count: count of bytes
728 * @ppos: pointer to the position to write. No seeks allowed
729 *
730 * A write to a watchdog device is defined as a keepalive signal. Any
731 * write of data will do, as we we don't define content meaning.
732 */
733static ssize_t wdt_write(struct file *file, const char __user *buf,
734 size_t count, loff_t *ppos)
735{
617780d2
AN
736 if (count) {
737 wdt_ping();
738 return 1;
739 }
740 return 0;
741}
742
743static ssize_t wdt_read(struct file *file, char __user *buf,
744 size_t count, loff_t *ppos)
745{
746 return 0;
747}
748
749/**
750 * wdt_ioctl:
751 * @inode: inode of the device
752 * @file: file handle to the device
753 * @cmd: watchdog command
754 * @arg: argument pointer
755 *
756 * The watchdog API defines a common set of functions for all watchdogs
757 * according to their available features. We only actually usefully support
758 * querying capabilities and current status.
759 */
55929332 760static int wdt_ioctl(struct file *file, unsigned int cmd,
617780d2
AN
761 unsigned long arg)
762{
763 int new_margin, rv;
764 static struct watchdog_info ident = {
765 .options = WDIOF_POWERUNDER | WDIOF_KEEPALIVEPING |
766 WDIOF_SETTIMEOUT,
767 .firmware_version = 1,
768 .identity = "M41T80 WTD"
769 };
770
771 switch (cmd) {
772 case WDIOC_GETSUPPORT:
773 return copy_to_user((struct watchdog_info __user *)arg, &ident,
774 sizeof(ident)) ? -EFAULT : 0;
775
776 case WDIOC_GETSTATUS:
777 case WDIOC_GETBOOTSTATUS:
778 return put_user(boot_flag, (int __user *)arg);
779 case WDIOC_KEEPALIVE:
780 wdt_ping();
781 return 0;
782 case WDIOC_SETTIMEOUT:
783 if (get_user(new_margin, (int __user *)arg))
784 return -EFAULT;
785 /* Arbitrary, can't find the card's limits */
786 if (new_margin < 1 || new_margin > 124)
787 return -EINVAL;
788 wdt_margin = new_margin;
789 wdt_ping();
790 /* Fall */
791 case WDIOC_GETTIMEOUT:
792 return put_user(wdt_margin, (int __user *)arg);
793
794 case WDIOC_SETOPTIONS:
795 if (copy_from_user(&rv, (int __user *)arg, sizeof(int)))
796 return -EFAULT;
797
798 if (rv & WDIOS_DISABLECARD) {
a737e835 799 pr_info("disable watchdog\n");
617780d2
AN
800 wdt_disable();
801 }
802
803 if (rv & WDIOS_ENABLECARD) {
a737e835 804 pr_info("enable watchdog\n");
617780d2
AN
805 wdt_ping();
806 }
807
808 return -EINVAL;
809 }
810 return -ENOTTY;
811}
812
55929332
AB
813static long wdt_unlocked_ioctl(struct file *file, unsigned int cmd,
814 unsigned long arg)
815{
816 int ret;
817
613655fa 818 mutex_lock(&m41t80_rtc_mutex);
55929332 819 ret = wdt_ioctl(file, cmd, arg);
613655fa 820 mutex_unlock(&m41t80_rtc_mutex);
55929332
AB
821
822 return ret;
823}
824
617780d2
AN
825/**
826 * wdt_open:
827 * @inode: inode of device
828 * @file: file handle to device
829 *
830 */
831static int wdt_open(struct inode *inode, struct file *file)
832{
833 if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) {
613655fa 834 mutex_lock(&m41t80_rtc_mutex);
41012735 835 if (test_and_set_bit(0, &wdt_is_open)) {
613655fa 836 mutex_unlock(&m41t80_rtc_mutex);
617780d2 837 return -EBUSY;
41012735 838 }
617780d2
AN
839 /*
840 * Activate
841 */
842 wdt_is_open = 1;
613655fa 843 mutex_unlock(&m41t80_rtc_mutex);
09eeb1f5 844 return nonseekable_open(inode, file);
617780d2
AN
845 }
846 return -ENODEV;
847}
848
849/**
850 * wdt_close:
851 * @inode: inode to board
852 * @file: file handle to board
853 *
854 */
855static int wdt_release(struct inode *inode, struct file *file)
856{
857 if (MINOR(inode->i_rdev) == WATCHDOG_MINOR)
858 clear_bit(0, &wdt_is_open);
859 return 0;
860}
861
862/**
863 * notify_sys:
864 * @this: our notifier block
865 * @code: the event being reported
866 * @unused: unused
867 *
868 * Our notifier is called on system shutdowns. We want to turn the card
869 * off at reboot otherwise the machine will reboot again during memory
870 * test or worse yet during the following fsck. This would suck, in fact
871 * trust me - if it happens it does suck.
872 */
873static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
874 void *unused)
875{
876 if (code == SYS_DOWN || code == SYS_HALT)
877 /* Disable Watchdog */
878 wdt_disable();
879 return NOTIFY_DONE;
880}
881
882static const struct file_operations wdt_fops = {
883 .owner = THIS_MODULE,
884 .read = wdt_read,
55929332 885 .unlocked_ioctl = wdt_unlocked_ioctl,
617780d2
AN
886 .write = wdt_write,
887 .open = wdt_open,
888 .release = wdt_release,
6038f373 889 .llseek = no_llseek,
617780d2
AN
890};
891
892static struct miscdevice wdt_dev = {
893 .minor = WATCHDOG_MINOR,
894 .name = "watchdog",
895 .fops = &wdt_fops,
896};
897
898/*
899 * The WDT card needs to learn about soft shutdowns in order to
900 * turn the timebomb registers off.
901 */
902static struct notifier_block wdt_notifier = {
903 .notifier_call = wdt_notify_sys,
904};
905#endif /* CONFIG_RTC_DRV_M41T80_WDT */
906
caaff562
AN
907/*
908 *****************************************************************************
909 *
910 * Driver Interface
911 *
912 *****************************************************************************
913 */
ef6b3125
MJ
914
915static void m41t80_remove_sysfs_group(void *_dev)
916{
917 struct device *dev = _dev;
918
919 sysfs_remove_group(&dev->kobj, &attr_group);
920}
921
d2653e92
JD
922static int m41t80_probe(struct i2c_client *client,
923 const struct i2c_device_id *id)
caaff562 924{
f2b84ee8 925 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
3760f736 926 int rc = 0;
caaff562
AN
927 struct rtc_device *rtc = NULL;
928 struct rtc_time tm;
9c6dfed9 929 struct m41t80_data *m41t80_data = NULL;
caaff562 930
f2b84ee8
MJ
931 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK |
932 I2C_FUNC_SMBUS_BYTE_DATA)) {
933 dev_err(&adapter->dev, "doesn't support I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK\n");
c67fedfa 934 return -ENODEV;
f2b84ee8 935 }
caaff562 936
9c6dfed9
MJ
937 m41t80_data = devm_kzalloc(&client->dev, sizeof(*m41t80_data),
938 GFP_KERNEL);
939 if (!m41t80_data)
c67fedfa 940 return -ENOMEM;
caaff562 941
1373e77b 942 m41t80_data->client = client;
eb235c56
JMC
943 if (client->dev.of_node)
944 m41t80_data->features = (unsigned long)
945 of_device_get_match_data(&client->dev);
946 else
947 m41t80_data->features = id->driver_data;
9c6dfed9
MJ
948 i2c_set_clientdata(client, m41t80_data);
949
950 if (client->irq > 0) {
951 rc = devm_request_threaded_irq(&client->dev, client->irq,
952 NULL, m41t80_handle_irq,
953 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
954 "m41t80", client);
955 if (rc) {
956 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
957 client->irq = 0;
958 } else {
959 m41t80_rtc_ops.read_alarm = m41t80_read_alarm;
960 m41t80_rtc_ops.set_alarm = m41t80_set_alarm;
961 m41t80_rtc_ops.alarm_irq_enable = m41t80_alarm_irq_enable;
3726a218
MJ
962 /* Enable the wakealarm */
963 device_init_wakeup(&client->dev, true);
9c6dfed9
MJ
964 }
965 }
a015dbc1 966
4ebabb78 967 rtc = devm_rtc_device_register(&client->dev, client->name,
fc99b901 968 &m41t80_rtc_ops, THIS_MODULE);
c67fedfa
WS
969 if (IS_ERR(rtc))
970 return PTR_ERR(rtc);
caaff562 971
9c6dfed9 972 m41t80_data->rtc = rtc;
caaff562
AN
973
974 /* Make sure HT (Halt Update) bit is cleared */
975 rc = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_HOUR);
caaff562 976
c67fedfa 977 if (rc >= 0 && rc & M41T80_ALHOUR_HT) {
9c6dfed9 978 if (m41t80_data->features & M41T80_FEATURE_HT) {
caaff562
AN
979 m41t80_get_datetime(client, &tm);
980 dev_info(&client->dev, "HT bit was set!\n");
981 dev_info(&client->dev,
fc99b901 982 "Power Down at %04i-%02i-%02i %02i:%02i:%02i\n",
caaff562
AN
983 tm.tm_year + 1900,
984 tm.tm_mon + 1, tm.tm_mday, tm.tm_hour,
985 tm.tm_min, tm.tm_sec);
986 }
c67fedfa 987 rc = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_HOUR,
fc99b901 988 rc & ~M41T80_ALHOUR_HT);
c67fedfa
WS
989 }
990
991 if (rc < 0) {
992 dev_err(&client->dev, "Can't clear HT bit\n");
85d77047 993 return rc;
caaff562
AN
994 }
995
996 /* Make sure ST (stop) bit is cleared */
997 rc = i2c_smbus_read_byte_data(client, M41T80_REG_SEC);
caaff562 998
c67fedfa
WS
999 if (rc >= 0 && rc & M41T80_SEC_ST)
1000 rc = i2c_smbus_write_byte_data(client, M41T80_REG_SEC,
fc99b901 1001 rc & ~M41T80_SEC_ST);
c67fedfa
WS
1002 if (rc < 0) {
1003 dev_err(&client->dev, "Can't clear ST bit\n");
85d77047 1004 return rc;
caaff562
AN
1005 }
1006
ef6b3125
MJ
1007 /* Export sysfs entries */
1008 rc = sysfs_create_group(&(&client->dev)->kobj, &attr_group);
1009 if (rc) {
1010 dev_err(&client->dev, "Failed to create sysfs group: %d\n", rc);
c67fedfa 1011 return rc;
ef6b3125
MJ
1012 }
1013
104b2d87
SM
1014 rc = devm_add_action_or_reset(&client->dev, m41t80_remove_sysfs_group,
1015 &client->dev);
ef6b3125 1016 if (rc) {
ef6b3125
MJ
1017 dev_err(&client->dev,
1018 "Failed to add sysfs cleanup action: %d\n", rc);
1019 return rc;
1020 }
caaff562 1021
617780d2 1022#ifdef CONFIG_RTC_DRV_M41T80_WDT
9c6dfed9 1023 if (m41t80_data->features & M41T80_FEATURE_HT) {
417607d0 1024 save_client = client;
617780d2
AN
1025 rc = misc_register(&wdt_dev);
1026 if (rc)
c67fedfa 1027 return rc;
617780d2
AN
1028 rc = register_reboot_notifier(&wdt_notifier);
1029 if (rc) {
1030 misc_deregister(&wdt_dev);
c67fedfa 1031 return rc;
617780d2 1032 }
617780d2 1033 }
1373e77b
GB
1034#endif
1035#ifdef CONFIG_COMMON_CLK
1036 if (m41t80_data->features & M41T80_FEATURE_SQ)
1037 m41t80_sqw_register_clk(m41t80_data);
617780d2 1038#endif
caaff562 1039 return 0;
caaff562
AN
1040}
1041
1042static int m41t80_remove(struct i2c_client *client)
1043{
4ebabb78 1044#ifdef CONFIG_RTC_DRV_M41T80_WDT
caaff562 1045 struct m41t80_data *clientdata = i2c_get_clientdata(client);
caaff562 1046
3760f736 1047 if (clientdata->features & M41T80_FEATURE_HT) {
617780d2
AN
1048 misc_deregister(&wdt_dev);
1049 unregister_reboot_notifier(&wdt_notifier);
1050 }
1051#endif
caaff562
AN
1052
1053 return 0;
1054}
1055
1056static struct i2c_driver m41t80_driver = {
1057 .driver = {
afe1ab4d 1058 .name = "rtc-m41t80",
eb235c56 1059 .of_match_table = of_match_ptr(m41t80_of_match),
ae036af8 1060 .pm = &m41t80_pm,
caaff562
AN
1061 },
1062 .probe = m41t80_probe,
1063 .remove = m41t80_remove,
3760f736 1064 .id_table = m41t80_id,
caaff562
AN
1065};
1066
0abc9201 1067module_i2c_driver(m41t80_driver);
caaff562
AN
1068
1069MODULE_AUTHOR("Alexander Bigga <ab@mycable.de>");
1070MODULE_DESCRIPTION("ST Microelectronics M41T80 series RTC I2C Client Driver");
1071MODULE_LICENSE("GPL");