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d00ed3cf DM |
1 | /* |
2 | * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/io.h> | |
13 | #include <linux/rtc.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d00ed3cf DM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/clk.h> | |
19 | ||
20 | #include <mach/hardware.h> | |
21 | ||
22 | #define RTC_INPUT_CLK_32768HZ (0x00 << 5) | |
23 | #define RTC_INPUT_CLK_32000HZ (0x01 << 5) | |
24 | #define RTC_INPUT_CLK_38400HZ (0x02 << 5) | |
25 | ||
26 | #define RTC_SW_BIT (1 << 0) | |
27 | #define RTC_ALM_BIT (1 << 2) | |
28 | #define RTC_1HZ_BIT (1 << 4) | |
29 | #define RTC_2HZ_BIT (1 << 7) | |
30 | #define RTC_SAM0_BIT (1 << 8) | |
31 | #define RTC_SAM1_BIT (1 << 9) | |
32 | #define RTC_SAM2_BIT (1 << 10) | |
33 | #define RTC_SAM3_BIT (1 << 11) | |
34 | #define RTC_SAM4_BIT (1 << 12) | |
35 | #define RTC_SAM5_BIT (1 << 13) | |
36 | #define RTC_SAM6_BIT (1 << 14) | |
37 | #define RTC_SAM7_BIT (1 << 15) | |
38 | #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ | |
39 | RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ | |
40 | RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) | |
41 | ||
42 | #define RTC_ENABLE_BIT (1 << 7) | |
43 | ||
44 | #define MAX_PIE_NUM 9 | |
45 | #define MAX_PIE_FREQ 512 | |
46 | static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { | |
47 | { 2, RTC_2HZ_BIT }, | |
48 | { 4, RTC_SAM0_BIT }, | |
49 | { 8, RTC_SAM1_BIT }, | |
50 | { 16, RTC_SAM2_BIT }, | |
51 | { 32, RTC_SAM3_BIT }, | |
52 | { 64, RTC_SAM4_BIT }, | |
53 | { 128, RTC_SAM5_BIT }, | |
54 | { 256, RTC_SAM6_BIT }, | |
55 | { MAX_PIE_FREQ, RTC_SAM7_BIT }, | |
56 | }; | |
57 | ||
d00ed3cf DM |
58 | #define MXC_RTC_TIME 0 |
59 | #define MXC_RTC_ALARM 1 | |
60 | ||
61 | #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ | |
62 | #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ | |
63 | #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ | |
64 | #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ | |
65 | #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ | |
66 | #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ | |
67 | #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ | |
68 | #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ | |
69 | #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ | |
70 | #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ | |
71 | #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ | |
72 | #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ | |
73 | #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ | |
74 | ||
75 | struct rtc_plat_data { | |
76 | struct rtc_device *rtc; | |
77 | void __iomem *ioaddr; | |
78 | int irq; | |
79 | struct clk *clk; | |
d00ed3cf DM |
80 | struct rtc_time g_rtc_alarm; |
81 | }; | |
82 | ||
83 | /* | |
84 | * This function is used to obtain the RTC time or the alarm value in | |
85 | * second. | |
86 | */ | |
87 | static u32 get_alarm_or_time(struct device *dev, int time_alarm) | |
88 | { | |
89 | struct platform_device *pdev = to_platform_device(dev); | |
90 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
91 | void __iomem *ioaddr = pdata->ioaddr; | |
92 | u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; | |
93 | ||
94 | switch (time_alarm) { | |
95 | case MXC_RTC_TIME: | |
96 | day = readw(ioaddr + RTC_DAYR); | |
97 | hr_min = readw(ioaddr + RTC_HOURMIN); | |
98 | sec = readw(ioaddr + RTC_SECOND); | |
99 | break; | |
100 | case MXC_RTC_ALARM: | |
101 | day = readw(ioaddr + RTC_DAYALARM); | |
102 | hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; | |
103 | sec = readw(ioaddr + RTC_ALRM_SEC); | |
104 | break; | |
105 | } | |
106 | ||
107 | hr = hr_min >> 8; | |
108 | min = hr_min & 0xff; | |
109 | ||
110 | return (((day * 24 + hr) * 60) + min) * 60 + sec; | |
111 | } | |
112 | ||
113 | /* | |
114 | * This function sets the RTC alarm value or the time value. | |
115 | */ | |
116 | static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time) | |
117 | { | |
118 | u32 day, hr, min, sec, temp; | |
119 | struct platform_device *pdev = to_platform_device(dev); | |
120 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
121 | void __iomem *ioaddr = pdata->ioaddr; | |
122 | ||
123 | day = time / 86400; | |
124 | time -= day * 86400; | |
125 | ||
126 | /* time is within a day now */ | |
127 | hr = time / 3600; | |
128 | time -= hr * 3600; | |
129 | ||
130 | /* time is within an hour now */ | |
131 | min = time / 60; | |
132 | sec = time - min * 60; | |
133 | ||
134 | temp = (hr << 8) + min; | |
135 | ||
136 | switch (time_alarm) { | |
137 | case MXC_RTC_TIME: | |
138 | writew(day, ioaddr + RTC_DAYR); | |
139 | writew(sec, ioaddr + RTC_SECOND); | |
140 | writew(temp, ioaddr + RTC_HOURMIN); | |
141 | break; | |
142 | case MXC_RTC_ALARM: | |
143 | writew(day, ioaddr + RTC_DAYALARM); | |
144 | writew(sec, ioaddr + RTC_ALRM_SEC); | |
145 | writew(temp, ioaddr + RTC_ALRM_HM); | |
146 | break; | |
147 | } | |
148 | } | |
149 | ||
150 | /* | |
151 | * This function updates the RTC alarm registers and then clears all the | |
152 | * interrupt status bits. | |
153 | */ | |
154 | static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) | |
155 | { | |
156 | struct rtc_time alarm_tm, now_tm; | |
157 | unsigned long now, time; | |
d00ed3cf DM |
158 | struct platform_device *pdev = to_platform_device(dev); |
159 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
160 | void __iomem *ioaddr = pdata->ioaddr; | |
161 | ||
162 | now = get_alarm_or_time(dev, MXC_RTC_TIME); | |
163 | rtc_time_to_tm(now, &now_tm); | |
164 | alarm_tm.tm_year = now_tm.tm_year; | |
165 | alarm_tm.tm_mon = now_tm.tm_mon; | |
166 | alarm_tm.tm_mday = now_tm.tm_mday; | |
167 | alarm_tm.tm_hour = alrm->tm_hour; | |
168 | alarm_tm.tm_min = alrm->tm_min; | |
169 | alarm_tm.tm_sec = alrm->tm_sec; | |
d00ed3cf DM |
170 | rtc_tm_to_time(&alarm_tm, &time); |
171 | ||
d00ed3cf DM |
172 | /* clear all the interrupt status bits */ |
173 | writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); | |
174 | set_alarm_or_time(dev, MXC_RTC_ALARM, time); | |
175 | ||
c92182ee YK |
176 | return 0; |
177 | } | |
178 | ||
179 | static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, | |
180 | unsigned int enabled) | |
181 | { | |
182 | struct platform_device *pdev = to_platform_device(dev); | |
183 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
184 | void __iomem *ioaddr = pdata->ioaddr; | |
185 | u32 reg; | |
186 | ||
187 | spin_lock_irq(&pdata->rtc->irq_lock); | |
188 | reg = readw(ioaddr + RTC_RTCIENR); | |
189 | ||
190 | if (enabled) | |
191 | reg |= bit; | |
192 | else | |
193 | reg &= ~bit; | |
194 | ||
195 | writew(reg, ioaddr + RTC_RTCIENR); | |
196 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
d00ed3cf DM |
197 | } |
198 | ||
199 | /* This function is the RTC interrupt service routine. */ | |
200 | static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) | |
201 | { | |
202 | struct platform_device *pdev = dev_id; | |
203 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
204 | void __iomem *ioaddr = pdata->ioaddr; | |
205 | u32 status; | |
206 | u32 events = 0; | |
207 | ||
208 | spin_lock_irq(&pdata->rtc->irq_lock); | |
209 | status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); | |
210 | /* clear interrupt sources */ | |
211 | writew(status, ioaddr + RTC_RTCISR); | |
212 | ||
d00ed3cf | 213 | /* update irq data & counter */ |
c92182ee | 214 | if (status & RTC_ALM_BIT) { |
d00ed3cf | 215 | events |= (RTC_AF | RTC_IRQF); |
c92182ee YK |
216 | /* RTC alarm should be one-shot */ |
217 | mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0); | |
218 | } | |
d00ed3cf DM |
219 | |
220 | if (status & RTC_1HZ_BIT) | |
221 | events |= (RTC_UF | RTC_IRQF); | |
222 | ||
223 | if (status & PIT_ALL_ON) | |
224 | events |= (RTC_PF | RTC_IRQF); | |
225 | ||
d00ed3cf DM |
226 | rtc_update_irq(pdata->rtc, 1, events); |
227 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
228 | ||
229 | return IRQ_HANDLED; | |
230 | } | |
231 | ||
232 | /* | |
233 | * Clear all interrupts and release the IRQ | |
234 | */ | |
235 | static void mxc_rtc_release(struct device *dev) | |
236 | { | |
237 | struct platform_device *pdev = to_platform_device(dev); | |
238 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
239 | void __iomem *ioaddr = pdata->ioaddr; | |
240 | ||
241 | spin_lock_irq(&pdata->rtc->irq_lock); | |
242 | ||
243 | /* Disable all rtc interrupts */ | |
244 | writew(0, ioaddr + RTC_RTCIENR); | |
245 | ||
246 | /* Clear all interrupt status */ | |
247 | writew(0xffffffff, ioaddr + RTC_RTCISR); | |
248 | ||
249 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
250 | } | |
251 | ||
d00ed3cf DM |
252 | static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
253 | { | |
254 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); | |
255 | return 0; | |
256 | } | |
257 | ||
d00ed3cf DM |
258 | /* |
259 | * This function reads the current RTC time into tm in Gregorian date. | |
260 | */ | |
261 | static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
262 | { | |
263 | u32 val; | |
264 | ||
265 | /* Avoid roll-over from reading the different registers */ | |
266 | do { | |
267 | val = get_alarm_or_time(dev, MXC_RTC_TIME); | |
268 | } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
269 | ||
270 | rtc_time_to_tm(val, tm); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | /* | |
276 | * This function sets the internal RTC time based on tm in Gregorian date. | |
277 | */ | |
278 | static int mxc_rtc_set_mmss(struct device *dev, unsigned long time) | |
279 | { | |
7287be1d YK |
280 | /* |
281 | * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only | |
282 | */ | |
283 | if (cpu_is_mx1()) { | |
284 | struct rtc_time tm; | |
285 | ||
286 | rtc_time_to_tm(time, &tm); | |
287 | tm.tm_year = 70; | |
288 | rtc_tm_to_time(&tm, &time); | |
289 | } | |
290 | ||
d00ed3cf DM |
291 | /* Avoid roll-over from reading the different registers */ |
292 | do { | |
293 | set_alarm_or_time(dev, MXC_RTC_TIME, time); | |
294 | } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | /* | |
300 | * This function reads the current alarm value into the passed in 'alrm' | |
301 | * argument. It updates the alrm's pending field value based on the whether | |
302 | * an alarm interrupt occurs or not. | |
303 | */ | |
304 | static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
305 | { | |
306 | struct platform_device *pdev = to_platform_device(dev); | |
307 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
308 | void __iomem *ioaddr = pdata->ioaddr; | |
309 | ||
310 | rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); | |
311 | alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | /* | |
317 | * This function sets the RTC alarm based on passed in alrm. | |
318 | */ | |
319 | static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
320 | { | |
321 | struct platform_device *pdev = to_platform_device(dev); | |
322 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
323 | int ret; | |
324 | ||
c92182ee | 325 | ret = rtc_update_alarm(dev, &alrm->time); |
d00ed3cf DM |
326 | if (ret) |
327 | return ret; | |
328 | ||
329 | memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); | |
330 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
335 | /* RTC layer */ | |
336 | static struct rtc_class_ops mxc_rtc_ops = { | |
337 | .release = mxc_rtc_release, | |
338 | .read_time = mxc_rtc_read_time, | |
339 | .set_mmss = mxc_rtc_set_mmss, | |
340 | .read_alarm = mxc_rtc_read_alarm, | |
341 | .set_alarm = mxc_rtc_set_alarm, | |
342 | .alarm_irq_enable = mxc_rtc_alarm_irq_enable, | |
d00ed3cf DM |
343 | }; |
344 | ||
345 | static int __init mxc_rtc_probe(struct platform_device *pdev) | |
346 | { | |
d00ed3cf DM |
347 | struct resource *res; |
348 | struct rtc_device *rtc; | |
349 | struct rtc_plat_data *pdata = NULL; | |
350 | u32 reg; | |
c783a29e VZ |
351 | unsigned long rate; |
352 | int ret; | |
d00ed3cf DM |
353 | |
354 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
355 | if (!res) | |
356 | return -ENODEV; | |
357 | ||
c783a29e | 358 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
d00ed3cf DM |
359 | if (!pdata) |
360 | return -ENOMEM; | |
361 | ||
c783a29e VZ |
362 | if (!devm_request_mem_region(&pdev->dev, res->start, |
363 | resource_size(res), pdev->name)) | |
364 | return -EBUSY; | |
365 | ||
366 | pdata->ioaddr = devm_ioremap(&pdev->dev, res->start, | |
367 | resource_size(res)); | |
d00ed3cf | 368 | |
5cf8f57d VZ |
369 | pdata->clk = clk_get(&pdev->dev, "rtc"); |
370 | if (IS_ERR(pdata->clk)) { | |
371 | dev_err(&pdev->dev, "unable to get clock!\n"); | |
372 | ret = PTR_ERR(pdata->clk); | |
49908e73 AB |
373 | goto exit_free_pdata; |
374 | } | |
d00ed3cf | 375 | |
5cf8f57d VZ |
376 | clk_enable(pdata->clk); |
377 | rate = clk_get_rate(pdata->clk); | |
d00ed3cf DM |
378 | |
379 | if (rate == 32768) | |
380 | reg = RTC_INPUT_CLK_32768HZ; | |
381 | else if (rate == 32000) | |
382 | reg = RTC_INPUT_CLK_32000HZ; | |
383 | else if (rate == 38400) | |
384 | reg = RTC_INPUT_CLK_38400HZ; | |
385 | else { | |
c783a29e | 386 | dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate); |
d00ed3cf | 387 | ret = -EINVAL; |
5cf8f57d | 388 | goto exit_put_clk; |
d00ed3cf DM |
389 | } |
390 | ||
391 | reg |= RTC_ENABLE_BIT; | |
392 | writew(reg, (pdata->ioaddr + RTC_RTCCTL)); | |
393 | if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { | |
394 | dev_err(&pdev->dev, "hardware module can't be enabled!\n"); | |
395 | ret = -EIO; | |
5cf8f57d | 396 | goto exit_put_clk; |
d00ed3cf DM |
397 | } |
398 | ||
d00ed3cf DM |
399 | platform_set_drvdata(pdev, pdata); |
400 | ||
401 | /* Configure and enable the RTC */ | |
402 | pdata->irq = platform_get_irq(pdev, 0); | |
403 | ||
404 | if (pdata->irq >= 0 && | |
c783a29e VZ |
405 | devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, |
406 | IRQF_SHARED, pdev->name, pdev) < 0) { | |
d00ed3cf DM |
407 | dev_warn(&pdev->dev, "interrupt not available.\n"); |
408 | pdata->irq = -1; | |
409 | } | |
410 | ||
c92182ee YK |
411 | if (pdata->irq >=0) |
412 | device_init_wakeup(&pdev->dev, 1); | |
413 | ||
5f54c8a0 WS |
414 | rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops, |
415 | THIS_MODULE); | |
416 | if (IS_ERR(rtc)) { | |
417 | ret = PTR_ERR(rtc); | |
418 | goto exit_clr_drvdata; | |
419 | } | |
420 | ||
421 | pdata->rtc = rtc; | |
422 | ||
d00ed3cf DM |
423 | return 0; |
424 | ||
5f54c8a0 WS |
425 | exit_clr_drvdata: |
426 | platform_set_drvdata(pdev, NULL); | |
d00ed3cf | 427 | exit_put_clk: |
c783a29e | 428 | clk_disable(pdata->clk); |
d00ed3cf DM |
429 | clk_put(pdata->clk); |
430 | ||
431 | exit_free_pdata: | |
d00ed3cf DM |
432 | |
433 | return ret; | |
434 | } | |
435 | ||
436 | static int __exit mxc_rtc_remove(struct platform_device *pdev) | |
437 | { | |
438 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
439 | ||
440 | rtc_device_unregister(pdata->rtc); | |
441 | ||
d00ed3cf DM |
442 | clk_disable(pdata->clk); |
443 | clk_put(pdata->clk); | |
d00ed3cf DM |
444 | platform_set_drvdata(pdev, NULL); |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
c92182ee YK |
449 | #ifdef CONFIG_PM |
450 | static int mxc_rtc_suspend(struct device *dev) | |
451 | { | |
452 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); | |
453 | ||
454 | if (device_may_wakeup(dev)) | |
455 | enable_irq_wake(pdata->irq); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static int mxc_rtc_resume(struct device *dev) | |
461 | { | |
462 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); | |
463 | ||
464 | if (device_may_wakeup(dev)) | |
465 | disable_irq_wake(pdata->irq); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | static struct dev_pm_ops mxc_rtc_pm_ops = { | |
471 | .suspend = mxc_rtc_suspend, | |
472 | .resume = mxc_rtc_resume, | |
473 | }; | |
474 | #endif | |
475 | ||
d00ed3cf DM |
476 | static struct platform_driver mxc_rtc_driver = { |
477 | .driver = { | |
478 | .name = "mxc_rtc", | |
c92182ee YK |
479 | #ifdef CONFIG_PM |
480 | .pm = &mxc_rtc_pm_ops, | |
481 | #endif | |
d00ed3cf DM |
482 | .owner = THIS_MODULE, |
483 | }, | |
484 | .remove = __exit_p(mxc_rtc_remove), | |
485 | }; | |
486 | ||
487 | static int __init mxc_rtc_init(void) | |
488 | { | |
489 | return platform_driver_probe(&mxc_rtc_driver, mxc_rtc_probe); | |
490 | } | |
491 | ||
492 | static void __exit mxc_rtc_exit(void) | |
493 | { | |
494 | platform_driver_unregister(&mxc_rtc_driver); | |
495 | } | |
496 | ||
497 | module_init(mxc_rtc_init); | |
498 | module_exit(mxc_rtc_exit); | |
499 | ||
500 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); | |
501 | MODULE_DESCRIPTION("RTC driver for Freescale MXC"); | |
502 | MODULE_LICENSE("GPL"); | |
503 |