[mirror_ubuntu-artful-kernel.git] / drivers / rtc / rtc-mxc.c

/*
 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512
static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
	{ 2,		RTC_2HZ_BIT },
	{ 4,		RTC_SAM0_BIT },
	{ 8,		RTC_SAM1_BIT },
	{ 16,		RTC_SAM2_BIT },
	{ 32,		RTC_SAM3_BIT },
	{ 64,		RTC_SAM4_BIT },
	{ 128,		RTC_SAM5_BIT },
	{ 256,		RTC_SAM6_BIT },
	{ MAX_PIE_FREQ,	RTC_SAM7_BIT },
};

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

enum imx_rtc_type {
	IMX1_RTC,
	IMX21_RTC,
};

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk_ref;
	struct clk *clk_ipg;
	struct rtc_time g_rtc_alarm;
	enum imx_rtc_type devtype;
};

static const struct platform_device_id imx_rtc_devtype[] = {
	{
		.name = "imx1-rtc",
		.driver_data = IMX1_RTC,
	}, {
		.name = "imx21-rtc",
		.driver_data = IMX21_RTC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);

#ifdef CONFIG_OF
static const struct of_device_id imx_rtc_dt_ids[] = {
	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	{}
};
MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
#endif

static inline int is_imx1_rtc(struct rtc_plat_data *data)
{
	return data->devtype == IMX1_RTC;
}

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
{
	u32 tod, day, hr, min, sec, temp;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = div_s64_rem(time, 86400, &tod);

	/* time is within a day now */
	hr = tod / 3600;
	tod -= hr * 3600;

	/* time is within an hour now */
	min = tod / 60;
	sec = tod - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	time64_t time;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	time = rtc_tm_to_time64(alrm);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & RTC_1HZ_BIT)
		events |= (RTC_UF | RTC_IRQF);

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

/*
 * Clear all interrupts and release the IRQ
 */
static void mxc_rtc_release(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	spin_lock_irq(&pdata->rtc->irq_lock);

	/* Disable all rtc interrupts */
	writew(0, ioaddr + RTC_RTCIENR);

	/* Clear all interrupt status */
	writew(0xffffffff, ioaddr + RTC_RTCISR);

	spin_unlock_irq(&pdata->rtc->irq_lock);
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	time64_t val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time64_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	/*
	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	 */
	if (is_imx1_rtc(pdata)) {
		struct rtc_time tm;

		rtc_time64_to_tm(time, &tm);
		tm.tm_year = 70;
		time = rtc_tm_to_time64(&tm);
	}

	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	rtc_update_alarm(dev, &alrm->time);

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static struct rtc_class_ops mxc_rtc_ops = {
	.release		= mxc_rtc_release,
	.read_time		= mxc_rtc_read_time,
	.set_mmss64		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;
	const struct of_device_id *of_id;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	if (of_id)
		pdata->devtype = (enum imx_rtc_type)of_id->data;
	else
		pdata->devtype = pdev->id_entry->driver_data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(pdata->clk_ipg)) {
		dev_err(&pdev->dev, "unable to get ipg clock!\n");
		return PTR_ERR(pdata->clk_ipg);
	}

	ret = clk_prepare_enable(pdata->clk_ipg);
	if (ret)
		return ret;

	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	if (IS_ERR(pdata->clk_ref)) {
		dev_err(&pdev->dev, "unable to get ref clock!\n");
		ret = PTR_ERR(pdata->clk_ref);
		goto exit_put_clk_ipg;
	}

	ret = clk_prepare_enable(pdata->clk_ref);
	if (ret)
		goto exit_put_clk_ipg;

	rate = clk_get_rate(pdata->clk_ref);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk_ref;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk_ref;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >= 0)
		device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
				  THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		goto exit_put_clk_ref;
	}

	pdata->rtc = rtc;

	return 0;

exit_put_clk_ref:
	clk_disable_unprepare(pdata->clk_ref);
exit_put_clk_ipg:
	clk_disable_unprepare(pdata->clk_ipg);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk_ref);
	clk_disable_unprepare(pdata->clk_ipg);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mxc_rtc_suspend(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pdata->irq);

	return 0;
}

static int mxc_rtc_resume(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pdata->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
		   .of_match_table = of_match_ptr(imx_rtc_dt_ids),
		   .pm		= &mxc_rtc_pm_ops,
	},
	.id_table = imx_rtc_devtype,
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver)

MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
d00ed3cf DM	1	/*
	2	* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/rtc.h>
	14	#include <linux/module.h>
5a0e3ad6	15	#include <linux/slab.h>
d00ed3cf DM	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk.h>
cec13c26 PR	19	#include <linux/of.h>
cec13c26 PR	20	#include <linux/of_device.h>
d00ed3cf	21
d00ed3cf DM	22	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	23	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	24	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	25
	26	#define RTC_SW_BIT (1 << 0)
	27	#define RTC_ALM_BIT (1 << 2)
	28	#define RTC_1HZ_BIT (1 << 4)
	29	#define RTC_2HZ_BIT (1 << 7)
	30	#define RTC_SAM0_BIT (1 << 8)
	31	#define RTC_SAM1_BIT (1 << 9)
	32	#define RTC_SAM2_BIT (1 << 10)
	33	#define RTC_SAM3_BIT (1 << 11)
	34	#define RTC_SAM4_BIT (1 << 12)
	35	#define RTC_SAM5_BIT (1 << 13)
	36	#define RTC_SAM6_BIT (1 << 14)
	37	#define RTC_SAM7_BIT (1 << 15)
	38	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	39	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	40	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	41
	42	#define RTC_ENABLE_BIT (1 << 7)
	43
	44	#define MAX_PIE_NUM 9
	45	#define MAX_PIE_FREQ 512
	46	static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
	47	{ 2, RTC_2HZ_BIT },
	48	{ 4, RTC_SAM0_BIT },
	49	{ 8, RTC_SAM1_BIT },
	50	{ 16, RTC_SAM2_BIT },
	51	{ 32, RTC_SAM3_BIT },
	52	{ 64, RTC_SAM4_BIT },
	53	{ 128, RTC_SAM5_BIT },
	54	{ 256, RTC_SAM6_BIT },
	55	{ MAX_PIE_FREQ, RTC_SAM7_BIT },
	56	};
	57
d00ed3cf DM	58	#define MXC_RTC_TIME 0
	59	#define MXC_RTC_ALARM 1
	60
	61	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	62	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	63	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	64	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	65	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	66	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	67	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	68	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	69	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	70	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	71	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	72	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	73	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	74
bb1d34a2 SG	75	enum imx_rtc_type {
	76	IMX1_RTC,
	77	IMX21_RTC,
	78	};
	79
d00ed3cf DM	80	struct rtc_plat_data {
	81	struct rtc_device *rtc;
	82	void __iomem *ioaddr;
	83	int irq;
8f5fe778 PR	84	struct clk *clk_ref;
8f5fe778 PR	85	struct clk *clk_ipg;
d00ed3cf	86	struct rtc_time g_rtc_alarm;
bb1d34a2	87	enum imx_rtc_type devtype;
d00ed3cf DM	88	};
d00ed3cf DM	89
cd6ba00a	90	static const struct platform_device_id imx_rtc_devtype[] = {
bb1d34a2 SG	91	{
	92	.name = "imx1-rtc",
	93	.driver_data = IMX1_RTC,
	94	}, {
	95	.name = "imx21-rtc",
	96	.driver_data = IMX21_RTC,
	97	}, {
	98	/* sentinel */
	99	}
	100	};
	101	MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
	102
cec13c26 PR	103	#ifdef CONFIG_OF
	104	static const struct of_device_id imx_rtc_dt_ids[] = {
	105	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	106	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	107	{}
	108	};
	109	MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
	110	#endif
	111
bb1d34a2 SG	112	static inline int is_imx1_rtc(struct rtc_plat_data *data)
	113	{
	114	return data->devtype == IMX1_RTC;
	115	}
	116
d00ed3cf DM	117	/*
	118	* This function is used to obtain the RTC time or the alarm value in
	119	* second.
	120	*/
a015b8aa	121	static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
d00ed3cf DM	122	{
	123	struct platform_device *pdev = to_platform_device(dev);
	124	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	125	void __iomem *ioaddr = pdata->ioaddr;
	126	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	127
	128	switch (time_alarm) {
	129	case MXC_RTC_TIME:
	130	day = readw(ioaddr + RTC_DAYR);
	131	hr_min = readw(ioaddr + RTC_HOURMIN);
	132	sec = readw(ioaddr + RTC_SECOND);
	133	break;
	134	case MXC_RTC_ALARM:
	135	day = readw(ioaddr + RTC_DAYALARM);
	136	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	137	sec = readw(ioaddr + RTC_ALRM_SEC);
	138	break;
	139	}
	140
	141	hr = hr_min >> 8;
	142	min = hr_min & 0xff;
	143
a015b8aa	144	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
d00ed3cf DM	145	}
	146
	147	/*
	148	* This function sets the RTC alarm value or the time value.
	149	*/
a015b8aa	150	static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
d00ed3cf	151	{
a015b8aa	152	u32 tod, day, hr, min, sec, temp;
d00ed3cf DM	153	struct platform_device *pdev = to_platform_device(dev);
	154	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	155	void __iomem *ioaddr = pdata->ioaddr;
	156
a015b8aa	157	day = div_s64_rem(time, 86400, &tod);
d00ed3cf DM	158
d00ed3cf DM	159	/* time is within a day now */
a015b8aa XP	160	hr = tod / 3600;
a015b8aa XP	161	tod -= hr * 3600;
d00ed3cf DM	162
d00ed3cf DM	163	/* time is within an hour now */
a015b8aa XP	164	min = tod / 60;
a015b8aa XP	165	sec = tod - min * 60;
d00ed3cf DM	166
	167	temp = (hr << 8) + min;
	168
	169	switch (time_alarm) {
	170	case MXC_RTC_TIME:
	171	writew(day, ioaddr + RTC_DAYR);
	172	writew(sec, ioaddr + RTC_SECOND);
	173	writew(temp, ioaddr + RTC_HOURMIN);
	174	break;
	175	case MXC_RTC_ALARM:
	176	writew(day, ioaddr + RTC_DAYALARM);
	177	writew(sec, ioaddr + RTC_ALRM_SEC);
	178	writew(temp, ioaddr + RTC_ALRM_HM);
	179	break;
	180	}
	181	}
	182
	183	/*
	184	* This function updates the RTC alarm registers and then clears all the
	185	* interrupt status bits.
	186	*/
482494a8	187	static void rtc_update_alarm(struct device dev, struct rtc_time alrm)
d00ed3cf	188	{
a015b8aa	189	time64_t time;
d00ed3cf DM	190	struct platform_device *pdev = to_platform_device(dev);
	191	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	192	void __iomem *ioaddr = pdata->ioaddr;
	193
a015b8aa	194	time = rtc_tm_to_time64(alrm);
d00ed3cf	195
d00ed3cf DM	196	/* clear all the interrupt status bits */
	197	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	198	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
c92182ee YK	199	}
	200
	201	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	202	unsigned int enabled)
	203	{
	204	struct platform_device *pdev = to_platform_device(dev);
	205	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	206	void __iomem *ioaddr = pdata->ioaddr;
	207	u32 reg;
	208
	209	spin_lock_irq(&pdata->rtc->irq_lock);
	210	reg = readw(ioaddr + RTC_RTCIENR);
	211
	212	if (enabled)
	213	reg \|= bit;
	214	else
	215	reg &= ~bit;
	216
	217	writew(reg, ioaddr + RTC_RTCIENR);
	218	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	219	}
	220
	221	/* This function is the RTC interrupt service routine. */
	222	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	223	{
	224	struct platform_device *pdev = dev_id;
	225	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	226	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	227	unsigned long flags;
d00ed3cf DM	228	u32 status;
	229	u32 events = 0;
	230
b59f6d1f	231	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	232	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	233	/* clear interrupt sources */
	234	writew(status, ioaddr + RTC_RTCISR);
	235
d00ed3cf	236	/* update irq data & counter */
c92182ee	237	if (status & RTC_ALM_BIT) {
d00ed3cf	238	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	239	/* RTC alarm should be one-shot */
	240	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	241	}
d00ed3cf DM	242
	243	if (status & RTC_1HZ_BIT)
	244	events \|= (RTC_UF \| RTC_IRQF);
	245
	246	if (status & PIT_ALL_ON)
	247	events \|= (RTC_PF \| RTC_IRQF);
	248
d00ed3cf	249	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	250	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	251
	252	return IRQ_HANDLED;
	253	}
	254
	255	/*
	256	* Clear all interrupts and release the IRQ
	257	*/
	258	static void mxc_rtc_release(struct device *dev)
	259	{
	260	struct platform_device *pdev = to_platform_device(dev);
	261	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	262	void __iomem *ioaddr = pdata->ioaddr;
	263
	264	spin_lock_irq(&pdata->rtc->irq_lock);
	265
	266	/* Disable all rtc interrupts */
	267	writew(0, ioaddr + RTC_RTCIENR);
	268
	269	/* Clear all interrupt status */
	270	writew(0xffffffff, ioaddr + RTC_RTCISR);
	271
	272	spin_unlock_irq(&pdata->rtc->irq_lock);
	273	}
	274
d00ed3cf DM	275	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	276	{
	277	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	278	return 0;
	279	}
	280
d00ed3cf DM	281	/*
	282	* This function reads the current RTC time into tm in Gregorian date.
	283	*/
	284	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	285	{
a015b8aa	286	time64_t val;
d00ed3cf DM	287
	288	/* Avoid roll-over from reading the different registers */
	289	do {
	290	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	291	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	292
a015b8aa	293	rtc_time64_to_tm(val, tm);
d00ed3cf DM	294
	295	return 0;
	296	}
	297
	298	/*
	299	* This function sets the internal RTC time based on tm in Gregorian date.
	300	*/
933623c3	301	static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
d00ed3cf	302	{
bb1d34a2 SG	303	struct platform_device *pdev = to_platform_device(dev);
	304	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	305
7287be1d YK	306	/*
	307	* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	308	*/
bb1d34a2	309	if (is_imx1_rtc(pdata)) {
7287be1d YK	310	struct rtc_time tm;
7287be1d YK	311
933623c3	312	rtc_time64_to_tm(time, &tm);
7287be1d	313	tm.tm_year = 70;
933623c3	314	time = rtc_tm_to_time64(&tm);
7287be1d YK	315	}
7287be1d YK	316
d00ed3cf DM	317	/* Avoid roll-over from reading the different registers */
	318	do {
	319	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	320	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	321
	322	return 0;
	323	}
	324
	325	/*
	326	* This function reads the current alarm value into the passed in 'alrm'
	327	* argument. It updates the alrm's pending field value based on the whether
	328	* an alarm interrupt occurs or not.
	329	*/
	330	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	331	{
	332	struct platform_device *pdev = to_platform_device(dev);
	333	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	334	void __iomem *ioaddr = pdata->ioaddr;
	335
a015b8aa	336	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
d00ed3cf DM	337	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	338
	339	return 0;
	340	}
	341
	342	/*
	343	* This function sets the RTC alarm based on passed in alrm.
	344	*/
	345	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	346	{
	347	struct platform_device *pdev = to_platform_device(dev);
	348	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
d00ed3cf	349
482494a8	350	rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	351
	352	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	353	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	354
	355	return 0;
	356	}
	357
	358	/* RTC layer */
	359	static struct rtc_class_ops mxc_rtc_ops = {
	360	.release = mxc_rtc_release,
	361	.read_time = mxc_rtc_read_time,
933623c3	362	.set_mmss64 = mxc_rtc_set_mmss,
d00ed3cf DM	363	.read_alarm = mxc_rtc_read_alarm,
	364	.set_alarm = mxc_rtc_set_alarm,
	365	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	366	};
d00ed3cf DM	367
5a167f45	368	static int mxc_rtc_probe(struct platform_device *pdev)
d00ed3cf	369	{
d00ed3cf DM	370	struct resource *res;
	371	struct rtc_device *rtc;
	372	struct rtc_plat_data *pdata = NULL;
	373	u32 reg;
c783a29e VZ	374	unsigned long rate;
c783a29e VZ	375	int ret;
cec13c26	376	const struct of_device_id *of_id;
d00ed3cf	377
c783a29e	378	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	379	if (!pdata)
	380	return -ENOMEM;
	381
cec13c26 PR	382	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	383	if (of_id)
	384	pdata->devtype = (enum imx_rtc_type)of_id->data;
	385	else
	386	pdata->devtype = pdev->id_entry->driver_data;
bb1d34a2	387
7c1d69ee JL	388	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	389	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	390	if (IS_ERR(pdata->ioaddr))
	391	return PTR_ERR(pdata->ioaddr);
d00ed3cf	392
8f5fe778 PR	393	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	394	if (IS_ERR(pdata->clk_ipg)) {
	395	dev_err(&pdev->dev, "unable to get ipg clock!\n");
	396	return PTR_ERR(pdata->clk_ipg);
49908e73	397	}
d00ed3cf	398
8f5fe778	399	ret = clk_prepare_enable(pdata->clk_ipg);
1b3d2243 FE	400	if (ret)
	401	return ret;
	402
8f5fe778 PR	403	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	404	if (IS_ERR(pdata->clk_ref)) {
	405	dev_err(&pdev->dev, "unable to get ref clock!\n");
	406	ret = PTR_ERR(pdata->clk_ref);
	407	goto exit_put_clk_ipg;
	408	}
	409
	410	ret = clk_prepare_enable(pdata->clk_ref);
	411	if (ret)
	412	goto exit_put_clk_ipg;
	413
	414	rate = clk_get_rate(pdata->clk_ref);
d00ed3cf DM	415
	416	if (rate == 32768)
	417	reg = RTC_INPUT_CLK_32768HZ;
	418	else if (rate == 32000)
	419	reg = RTC_INPUT_CLK_32000HZ;
	420	else if (rate == 38400)
	421	reg = RTC_INPUT_CLK_38400HZ;
	422	else {
c783a29e	423	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	424	ret = -EINVAL;
8f5fe778	425	goto exit_put_clk_ref;
d00ed3cf DM	426	}
	427
	428	reg \|= RTC_ENABLE_BIT;
	429	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	430	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	431	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	432	ret = -EIO;
8f5fe778	433	goto exit_put_clk_ref;
d00ed3cf DM	434	}
d00ed3cf DM	435
d00ed3cf DM	436	platform_set_drvdata(pdev, pdata);
	437
	438	/* Configure and enable the RTC */
	439	pdata->irq = platform_get_irq(pdev, 0);
	440
	441	if (pdata->irq >= 0 &&
c783a29e VZ	442	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	443	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	444	dev_warn(&pdev->dev, "interrupt not available.\n");
	445	pdata->irq = -1;
	446	}
	447
4a8282d0	448	if (pdata->irq >= 0)
c92182ee YK	449	device_init_wakeup(&pdev->dev, 1);
c92182ee YK	450
033ca3ad	451	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
5f54c8a0 WS	452	THIS_MODULE);
	453	if (IS_ERR(rtc)) {
	454	ret = PTR_ERR(rtc);
8f5fe778	455	goto exit_put_clk_ref;
5f54c8a0 WS	456	}
	457
	458	pdata->rtc = rtc;
	459
d00ed3cf DM	460	return 0;
d00ed3cf DM	461
8f5fe778 PR	462	exit_put_clk_ref:
	463	clk_disable_unprepare(pdata->clk_ref);
	464	exit_put_clk_ipg:
	465	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf	466
d00ed3cf DM	467	return ret;
	468	}
	469
5a167f45	470	static int mxc_rtc_remove(struct platform_device *pdev)
d00ed3cf DM	471	{
	472	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	473
8f5fe778 PR	474	clk_disable_unprepare(pdata->clk_ref);
8f5fe778 PR	475	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf DM	476
	477	return 0;
	478	}
	479
75634cc4	480	#ifdef CONFIG_PM_SLEEP
c92182ee YK	481	static int mxc_rtc_suspend(struct device *dev)
	482	{
	483	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	484
	485	if (device_may_wakeup(dev))
	486	enable_irq_wake(pdata->irq);
	487
	488	return 0;
	489	}
	490
	491	static int mxc_rtc_resume(struct device *dev)
	492	{
	493	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	494
	495	if (device_may_wakeup(dev))
	496	disable_irq_wake(pdata->irq);
	497
	498	return 0;
	499	}
c92182ee YK	500	#endif
c92182ee YK	501
75634cc4 JH	502	static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
75634cc4 JH	503
d00ed3cf DM	504	static struct platform_driver mxc_rtc_driver = {
	505	.driver = {
	506	.name = "mxc_rtc",
cec13c26	507	.of_match_table = of_match_ptr(imx_rtc_dt_ids),
c92182ee	508	.pm = &mxc_rtc_pm_ops,
d00ed3cf	509	},
bb1d34a2	510	.id_table = imx_rtc_devtype,
be8b6d51	511	.probe = mxc_rtc_probe,
5a167f45	512	.remove = mxc_rtc_remove,
d00ed3cf DM	513	};
d00ed3cf DM	514
be8b6d51	515	module_platform_driver(mxc_rtc_driver)
d00ed3cf DM	516
	517	MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
	518	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	519	MODULE_LICENSE("GPL");
	520