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75d01b75 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
d00ed3cf DM |
4 | |
5 | #include <linux/io.h> | |
6 | #include <linux/rtc.h> | |
7 | #include <linux/module.h> | |
5a0e3ad6 | 8 | #include <linux/slab.h> |
d00ed3cf DM |
9 | #include <linux/interrupt.h> |
10 | #include <linux/platform_device.h> | |
bc0e731f | 11 | #include <linux/pm_wakeirq.h> |
d00ed3cf | 12 | #include <linux/clk.h> |
cec13c26 PR |
13 | #include <linux/of.h> |
14 | #include <linux/of_device.h> | |
d00ed3cf | 15 | |
d00ed3cf DM |
16 | #define RTC_INPUT_CLK_32768HZ (0x00 << 5) |
17 | #define RTC_INPUT_CLK_32000HZ (0x01 << 5) | |
18 | #define RTC_INPUT_CLK_38400HZ (0x02 << 5) | |
19 | ||
20 | #define RTC_SW_BIT (1 << 0) | |
21 | #define RTC_ALM_BIT (1 << 2) | |
22 | #define RTC_1HZ_BIT (1 << 4) | |
23 | #define RTC_2HZ_BIT (1 << 7) | |
24 | #define RTC_SAM0_BIT (1 << 8) | |
25 | #define RTC_SAM1_BIT (1 << 9) | |
26 | #define RTC_SAM2_BIT (1 << 10) | |
27 | #define RTC_SAM3_BIT (1 << 11) | |
28 | #define RTC_SAM4_BIT (1 << 12) | |
29 | #define RTC_SAM5_BIT (1 << 13) | |
30 | #define RTC_SAM6_BIT (1 << 14) | |
31 | #define RTC_SAM7_BIT (1 << 15) | |
32 | #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ | |
33 | RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ | |
34 | RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) | |
35 | ||
36 | #define RTC_ENABLE_BIT (1 << 7) | |
37 | ||
38 | #define MAX_PIE_NUM 9 | |
39 | #define MAX_PIE_FREQ 512 | |
d00ed3cf | 40 | |
d00ed3cf DM |
41 | #define MXC_RTC_TIME 0 |
42 | #define MXC_RTC_ALARM 1 | |
43 | ||
44 | #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ | |
45 | #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ | |
46 | #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ | |
47 | #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ | |
48 | #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ | |
49 | #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ | |
50 | #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ | |
51 | #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ | |
52 | #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ | |
53 | #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ | |
54 | #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ | |
55 | #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ | |
56 | #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ | |
57 | ||
bb1d34a2 SG |
58 | enum imx_rtc_type { |
59 | IMX1_RTC, | |
60 | IMX21_RTC, | |
61 | }; | |
62 | ||
d00ed3cf DM |
63 | struct rtc_plat_data { |
64 | struct rtc_device *rtc; | |
65 | void __iomem *ioaddr; | |
66 | int irq; | |
8f5fe778 PR |
67 | struct clk *clk_ref; |
68 | struct clk *clk_ipg; | |
d00ed3cf | 69 | struct rtc_time g_rtc_alarm; |
bb1d34a2 | 70 | enum imx_rtc_type devtype; |
d00ed3cf DM |
71 | }; |
72 | ||
cec13c26 PR |
73 | static const struct of_device_id imx_rtc_dt_ids[] = { |
74 | { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC }, | |
75 | { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC }, | |
76 | {} | |
77 | }; | |
78 | MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids); | |
cec13c26 | 79 | |
bb1d34a2 SG |
80 | static inline int is_imx1_rtc(struct rtc_plat_data *data) |
81 | { | |
82 | return data->devtype == IMX1_RTC; | |
83 | } | |
84 | ||
d00ed3cf DM |
85 | /* |
86 | * This function is used to obtain the RTC time or the alarm value in | |
87 | * second. | |
88 | */ | |
a015b8aa | 89 | static time64_t get_alarm_or_time(struct device *dev, int time_alarm) |
d00ed3cf | 90 | { |
85368bb9 | 91 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); |
d00ed3cf DM |
92 | void __iomem *ioaddr = pdata->ioaddr; |
93 | u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; | |
94 | ||
95 | switch (time_alarm) { | |
96 | case MXC_RTC_TIME: | |
97 | day = readw(ioaddr + RTC_DAYR); | |
98 | hr_min = readw(ioaddr + RTC_HOURMIN); | |
99 | sec = readw(ioaddr + RTC_SECOND); | |
100 | break; | |
101 | case MXC_RTC_ALARM: | |
102 | day = readw(ioaddr + RTC_DAYALARM); | |
103 | hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; | |
104 | sec = readw(ioaddr + RTC_ALRM_SEC); | |
105 | break; | |
106 | } | |
107 | ||
108 | hr = hr_min >> 8; | |
109 | min = hr_min & 0xff; | |
110 | ||
a015b8aa | 111 | return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec; |
d00ed3cf DM |
112 | } |
113 | ||
114 | /* | |
115 | * This function sets the RTC alarm value or the time value. | |
116 | */ | |
a015b8aa | 117 | static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time) |
d00ed3cf | 118 | { |
a015b8aa | 119 | u32 tod, day, hr, min, sec, temp; |
85368bb9 | 120 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); |
d00ed3cf DM |
121 | void __iomem *ioaddr = pdata->ioaddr; |
122 | ||
a015b8aa | 123 | day = div_s64_rem(time, 86400, &tod); |
d00ed3cf DM |
124 | |
125 | /* time is within a day now */ | |
a015b8aa XP |
126 | hr = tod / 3600; |
127 | tod -= hr * 3600; | |
d00ed3cf DM |
128 | |
129 | /* time is within an hour now */ | |
a015b8aa XP |
130 | min = tod / 60; |
131 | sec = tod - min * 60; | |
d00ed3cf DM |
132 | |
133 | temp = (hr << 8) + min; | |
134 | ||
135 | switch (time_alarm) { | |
136 | case MXC_RTC_TIME: | |
137 | writew(day, ioaddr + RTC_DAYR); | |
138 | writew(sec, ioaddr + RTC_SECOND); | |
139 | writew(temp, ioaddr + RTC_HOURMIN); | |
140 | break; | |
141 | case MXC_RTC_ALARM: | |
142 | writew(day, ioaddr + RTC_DAYALARM); | |
143 | writew(sec, ioaddr + RTC_ALRM_SEC); | |
144 | writew(temp, ioaddr + RTC_ALRM_HM); | |
145 | break; | |
146 | } | |
147 | } | |
148 | ||
149 | /* | |
150 | * This function updates the RTC alarm registers and then clears all the | |
151 | * interrupt status bits. | |
152 | */ | |
482494a8 | 153 | static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm) |
d00ed3cf | 154 | { |
a015b8aa | 155 | time64_t time; |
85368bb9 | 156 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); |
d00ed3cf DM |
157 | void __iomem *ioaddr = pdata->ioaddr; |
158 | ||
a015b8aa | 159 | time = rtc_tm_to_time64(alrm); |
d00ed3cf | 160 | |
d00ed3cf DM |
161 | /* clear all the interrupt status bits */ |
162 | writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); | |
163 | set_alarm_or_time(dev, MXC_RTC_ALARM, time); | |
c92182ee YK |
164 | } |
165 | ||
166 | static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, | |
167 | unsigned int enabled) | |
168 | { | |
85368bb9 | 169 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); |
c92182ee YK |
170 | void __iomem *ioaddr = pdata->ioaddr; |
171 | u32 reg; | |
b0a3fa44 | 172 | unsigned long flags; |
c92182ee | 173 | |
b0a3fa44 | 174 | spin_lock_irqsave(&pdata->rtc->irq_lock, flags); |
c92182ee YK |
175 | reg = readw(ioaddr + RTC_RTCIENR); |
176 | ||
177 | if (enabled) | |
178 | reg |= bit; | |
179 | else | |
180 | reg &= ~bit; | |
181 | ||
182 | writew(reg, ioaddr + RTC_RTCIENR); | |
b0a3fa44 | 183 | spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags); |
d00ed3cf DM |
184 | } |
185 | ||
186 | /* This function is the RTC interrupt service routine. */ | |
187 | static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) | |
188 | { | |
189 | struct platform_device *pdev = dev_id; | |
190 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
191 | void __iomem *ioaddr = pdata->ioaddr; | |
192 | u32 status; | |
193 | u32 events = 0; | |
194 | ||
3f2d3018 | 195 | spin_lock(&pdata->rtc->irq_lock); |
d00ed3cf DM |
196 | status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); |
197 | /* clear interrupt sources */ | |
198 | writew(status, ioaddr + RTC_RTCISR); | |
199 | ||
d00ed3cf | 200 | /* update irq data & counter */ |
c92182ee | 201 | if (status & RTC_ALM_BIT) { |
d00ed3cf | 202 | events |= (RTC_AF | RTC_IRQF); |
c92182ee YK |
203 | /* RTC alarm should be one-shot */ |
204 | mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0); | |
205 | } | |
d00ed3cf | 206 | |
d00ed3cf DM |
207 | if (status & PIT_ALL_ON) |
208 | events |= (RTC_PF | RTC_IRQF); | |
209 | ||
d00ed3cf | 210 | rtc_update_irq(pdata->rtc, 1, events); |
3f2d3018 | 211 | spin_unlock(&pdata->rtc->irq_lock); |
d00ed3cf DM |
212 | |
213 | return IRQ_HANDLED; | |
214 | } | |
215 | ||
d00ed3cf DM |
216 | static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
217 | { | |
218 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); | |
219 | return 0; | |
220 | } | |
221 | ||
d00ed3cf DM |
222 | /* |
223 | * This function reads the current RTC time into tm in Gregorian date. | |
224 | */ | |
225 | static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
226 | { | |
a015b8aa | 227 | time64_t val; |
d00ed3cf DM |
228 | |
229 | /* Avoid roll-over from reading the different registers */ | |
230 | do { | |
231 | val = get_alarm_or_time(dev, MXC_RTC_TIME); | |
232 | } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
233 | ||
a015b8aa | 234 | rtc_time64_to_tm(val, tm); |
d00ed3cf DM |
235 | |
236 | return 0; | |
237 | } | |
238 | ||
239 | /* | |
240 | * This function sets the internal RTC time based on tm in Gregorian date. | |
241 | */ | |
02bc7235 | 242 | static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) |
d00ed3cf | 243 | { |
02bc7235 AB |
244 | time64_t time = rtc_tm_to_time64(tm); |
245 | ||
d00ed3cf DM |
246 | /* Avoid roll-over from reading the different registers */ |
247 | do { | |
248 | set_alarm_or_time(dev, MXC_RTC_TIME, time); | |
249 | } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | /* | |
255 | * This function reads the current alarm value into the passed in 'alrm' | |
256 | * argument. It updates the alrm's pending field value based on the whether | |
257 | * an alarm interrupt occurs or not. | |
258 | */ | |
259 | static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
260 | { | |
85368bb9 | 261 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); |
d00ed3cf DM |
262 | void __iomem *ioaddr = pdata->ioaddr; |
263 | ||
a015b8aa | 264 | rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); |
d00ed3cf DM |
265 | alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | /* | |
271 | * This function sets the RTC alarm based on passed in alrm. | |
272 | */ | |
273 | static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
274 | { | |
85368bb9 | 275 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); |
d00ed3cf | 276 | |
482494a8 | 277 | rtc_update_alarm(dev, &alrm->time); |
d00ed3cf DM |
278 | |
279 | memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); | |
280 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | /* RTC layer */ | |
8bc57e7f | 286 | static const struct rtc_class_ops mxc_rtc_ops = { |
d00ed3cf | 287 | .read_time = mxc_rtc_read_time, |
02bc7235 | 288 | .set_time = mxc_rtc_set_time, |
d00ed3cf DM |
289 | .read_alarm = mxc_rtc_read_alarm, |
290 | .set_alarm = mxc_rtc_set_alarm, | |
291 | .alarm_irq_enable = mxc_rtc_alarm_irq_enable, | |
d00ed3cf DM |
292 | }; |
293 | ||
fdc9f0ea AH |
294 | static void mxc_rtc_action(void *p) |
295 | { | |
296 | struct rtc_plat_data *pdata = p; | |
297 | ||
298 | clk_disable_unprepare(pdata->clk_ref); | |
299 | clk_disable_unprepare(pdata->clk_ipg); | |
300 | } | |
301 | ||
5a167f45 | 302 | static int mxc_rtc_probe(struct platform_device *pdev) |
d00ed3cf | 303 | { |
d00ed3cf DM |
304 | struct rtc_device *rtc; |
305 | struct rtc_plat_data *pdata = NULL; | |
306 | u32 reg; | |
c783a29e VZ |
307 | unsigned long rate; |
308 | int ret; | |
d00ed3cf | 309 | |
c783a29e | 310 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
d00ed3cf DM |
311 | if (!pdata) |
312 | return -ENOMEM; | |
313 | ||
ba7aa630 | 314 | pdata->devtype = (enum imx_rtc_type)of_device_get_match_data(&pdev->dev); |
bb1d34a2 | 315 | |
cf37fa79 | 316 | pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0); |
7c1d69ee JL |
317 | if (IS_ERR(pdata->ioaddr)) |
318 | return PTR_ERR(pdata->ioaddr); | |
d00ed3cf | 319 | |
ebc2ec4e AB |
320 | rtc = devm_rtc_allocate_device(&pdev->dev); |
321 | if (IS_ERR(rtc)) | |
322 | return PTR_ERR(rtc); | |
323 | ||
324 | pdata->rtc = rtc; | |
325 | rtc->ops = &mxc_rtc_ops; | |
83888df4 AB |
326 | if (is_imx1_rtc(pdata)) { |
327 | struct rtc_time tm; | |
328 | ||
329 | /* 9bit days + hours minutes seconds */ | |
330 | rtc->range_max = (1 << 9) * 86400 - 1; | |
331 | ||
332 | /* | |
333 | * Set the start date as beginning of the current year. This can | |
334 | * be overridden using device tree. | |
335 | */ | |
336 | rtc_time64_to_tm(ktime_get_real_seconds(), &tm); | |
337 | rtc->start_secs = mktime64(tm.tm_year, 1, 1, 0, 0, 0); | |
338 | rtc->set_start_time = true; | |
339 | } else { | |
340 | /* 16bit days + hours minutes seconds */ | |
341 | rtc->range_max = (1 << 16) * 86400ULL - 1; | |
342 | } | |
ebc2ec4e | 343 | |
8f5fe778 PR |
344 | pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
345 | if (IS_ERR(pdata->clk_ipg)) { | |
346 | dev_err(&pdev->dev, "unable to get ipg clock!\n"); | |
347 | return PTR_ERR(pdata->clk_ipg); | |
49908e73 | 348 | } |
d00ed3cf | 349 | |
8f5fe778 | 350 | ret = clk_prepare_enable(pdata->clk_ipg); |
1b3d2243 FE |
351 | if (ret) |
352 | return ret; | |
353 | ||
8f5fe778 PR |
354 | pdata->clk_ref = devm_clk_get(&pdev->dev, "ref"); |
355 | if (IS_ERR(pdata->clk_ref)) { | |
fdc9f0ea | 356 | clk_disable_unprepare(pdata->clk_ipg); |
8f5fe778 | 357 | dev_err(&pdev->dev, "unable to get ref clock!\n"); |
fdc9f0ea | 358 | return PTR_ERR(pdata->clk_ref); |
8f5fe778 PR |
359 | } |
360 | ||
361 | ret = clk_prepare_enable(pdata->clk_ref); | |
fdc9f0ea AH |
362 | if (ret) { |
363 | clk_disable_unprepare(pdata->clk_ipg); | |
364 | return ret; | |
365 | } | |
366 | ||
367 | ret = devm_add_action_or_reset(&pdev->dev, mxc_rtc_action, pdata); | |
8f5fe778 | 368 | if (ret) |
fdc9f0ea | 369 | return ret; |
8f5fe778 PR |
370 | |
371 | rate = clk_get_rate(pdata->clk_ref); | |
d00ed3cf DM |
372 | |
373 | if (rate == 32768) | |
374 | reg = RTC_INPUT_CLK_32768HZ; | |
375 | else if (rate == 32000) | |
376 | reg = RTC_INPUT_CLK_32000HZ; | |
377 | else if (rate == 38400) | |
378 | reg = RTC_INPUT_CLK_38400HZ; | |
379 | else { | |
c783a29e | 380 | dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate); |
fdc9f0ea | 381 | return -EINVAL; |
d00ed3cf DM |
382 | } |
383 | ||
384 | reg |= RTC_ENABLE_BIT; | |
385 | writew(reg, (pdata->ioaddr + RTC_RTCCTL)); | |
386 | if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { | |
387 | dev_err(&pdev->dev, "hardware module can't be enabled!\n"); | |
fdc9f0ea | 388 | return -EIO; |
d00ed3cf DM |
389 | } |
390 | ||
d00ed3cf DM |
391 | platform_set_drvdata(pdev, pdata); |
392 | ||
393 | /* Configure and enable the RTC */ | |
394 | pdata->irq = platform_get_irq(pdev, 0); | |
395 | ||
396 | if (pdata->irq >= 0 && | |
c783a29e VZ |
397 | devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, |
398 | IRQF_SHARED, pdev->name, pdev) < 0) { | |
d00ed3cf DM |
399 | dev_warn(&pdev->dev, "interrupt not available.\n"); |
400 | pdata->irq = -1; | |
401 | } | |
402 | ||
bc0e731f | 403 | if (pdata->irq >= 0) { |
c92182ee | 404 | device_init_wakeup(&pdev->dev, 1); |
bc0e731f AH |
405 | ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq); |
406 | if (ret) | |
407 | dev_err(&pdev->dev, "failed to enable irq wake\n"); | |
408 | } | |
c92182ee | 409 | |
fdcfd854 | 410 | ret = devm_rtc_register_device(rtc); |
d00ed3cf | 411 | |
d00ed3cf DM |
412 | return ret; |
413 | } | |
414 | ||
d00ed3cf DM |
415 | static struct platform_driver mxc_rtc_driver = { |
416 | .driver = { | |
417 | .name = "mxc_rtc", | |
cec13c26 | 418 | .of_match_table = of_match_ptr(imx_rtc_dt_ids), |
d00ed3cf | 419 | }, |
be8b6d51 | 420 | .probe = mxc_rtc_probe, |
d00ed3cf DM |
421 | }; |
422 | ||
be8b6d51 | 423 | module_platform_driver(mxc_rtc_driver) |
d00ed3cf DM |
424 | |
425 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); | |
426 | MODULE_DESCRIPTION("RTC driver for Freescale MXC"); | |
427 | MODULE_LICENSE("GPL"); | |
428 |