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Commit | Line | Data |
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db68b189 | 1 | /* |
10211ae3 | 2 | * TI OMAP Real Time Clock interface for Linux |
db68b189 DB |
3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
0125138d | 8 | * Copyright (C) 2014 Johan Hovold <johan@kernel.org> |
db68b189 DB |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
97ea1906 MN |
16 | #include <dt-bindings/gpio/gpio.h> |
17 | #include <linux/bcd.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/delay.h> | |
db68b189 | 20 | #include <linux/init.h> |
97ea1906 | 21 | #include <linux/io.h> |
db68b189 | 22 | #include <linux/ioport.h> |
97ea1906 MN |
23 | #include <linux/kernel.h> |
24 | #include <linux/module.h> | |
9e0344dc AM |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
97ea1906 MN |
27 | #include <linux/pinctrl/pinctrl.h> |
28 | #include <linux/pinctrl/pinconf.h> | |
29 | #include <linux/pinctrl/pinconf-generic.h> | |
30 | #include <linux/platform_device.h> | |
fc9bd902 | 31 | #include <linux/pm_runtime.h> |
97ea1906 | 32 | #include <linux/rtc.h> |
db68b189 | 33 | |
10211ae3 JH |
34 | /* |
35 | * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock | |
db68b189 DB |
36 | * with century-range alarm matching, driven by the 32kHz clock. |
37 | * | |
38 | * The main user-visible ways it differs from PC RTCs are by omitting | |
39 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
40 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
41 | * | |
42 | * Board-specific wiring options include using split power mode with | |
43 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
44 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
45 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
46 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
47 | */ |
48 | ||
db68b189 DB |
49 | /* RTC registers */ |
50 | #define OMAP_RTC_SECONDS_REG 0x00 | |
51 | #define OMAP_RTC_MINUTES_REG 0x04 | |
52 | #define OMAP_RTC_HOURS_REG 0x08 | |
53 | #define OMAP_RTC_DAYS_REG 0x0C | |
54 | #define OMAP_RTC_MONTHS_REG 0x10 | |
55 | #define OMAP_RTC_YEARS_REG 0x14 | |
56 | #define OMAP_RTC_WEEKS_REG 0x18 | |
57 | ||
58 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
59 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
60 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
61 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
62 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
63 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
64 | ||
65 | #define OMAP_RTC_CTRL_REG 0x40 | |
66 | #define OMAP_RTC_STATUS_REG 0x44 | |
67 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
68 | ||
69 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
70 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
71 | #define OMAP_RTC_OSC_REG 0x54 | |
72 | ||
b6ee15ef AB |
73 | #define OMAP_RTC_SCRATCH0_REG 0x60 |
74 | #define OMAP_RTC_SCRATCH1_REG 0x64 | |
75 | #define OMAP_RTC_SCRATCH2_REG 0x68 | |
76 | ||
cab1458c AM |
77 | #define OMAP_RTC_KICK0_REG 0x6c |
78 | #define OMAP_RTC_KICK1_REG 0x70 | |
79 | ||
8af750e3 HG |
80 | #define OMAP_RTC_IRQWAKEEN 0x7c |
81 | ||
222a12fc JH |
82 | #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 |
83 | #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 | |
84 | #define OMAP_RTC_ALARM2_HOURS_REG 0x88 | |
85 | #define OMAP_RTC_ALARM2_DAYS_REG 0x8c | |
86 | #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 | |
87 | #define OMAP_RTC_ALARM2_YEARS_REG 0x94 | |
88 | ||
89 | #define OMAP_RTC_PMIC_REG 0x98 | |
90 | ||
db68b189 | 91 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
92 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
93 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
94 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
95 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
96 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
97 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
98 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
99 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
100 | |
101 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a | 102 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
222a12fc | 103 | #define OMAP_RTC_STATUS_ALARM2 BIT(7) |
92adb96a SN |
104 | #define OMAP_RTC_STATUS_ALARM BIT(6) |
105 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
106 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
107 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
108 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
109 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
110 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
111 | |
112 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
222a12fc | 113 | #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) |
92adb96a SN |
114 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
115 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 116 | |
cd914bba SN |
117 | /* OMAP_RTC_OSC_REG bit fields: */ |
118 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
399cf0f6 | 119 | #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) |
3984903a | 120 | #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) |
cd914bba | 121 | |
8af750e3 | 122 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 123 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 124 | |
222a12fc JH |
125 | /* OMAP_RTC_PMIC bit fields: */ |
126 | #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) | |
97ea1906 MN |
127 | #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x) |
128 | #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x) | |
222a12fc | 129 | |
cab1458c AM |
130 | /* OMAP_RTC_KICKER values */ |
131 | #define KICK0_VALUE 0x83e70b13 | |
132 | #define KICK1_VALUE 0x95a4f1e0 | |
133 | ||
9c28bd07 LV |
134 | struct omap_rtc; |
135 | ||
2153f949 JH |
136 | struct omap_rtc_device_type { |
137 | bool has_32kclk_en; | |
2153f949 | 138 | bool has_irqwakeen; |
222a12fc | 139 | bool has_pmic_mode; |
9291e340 | 140 | bool has_power_up_reset; |
9c28bd07 LV |
141 | void (*lock)(struct omap_rtc *rtc); |
142 | void (*unlock)(struct omap_rtc *rtc); | |
2153f949 | 143 | }; |
cd914bba | 144 | |
55ba953a JH |
145 | struct omap_rtc { |
146 | struct rtc_device *rtc; | |
147 | void __iomem *base; | |
532409aa | 148 | struct clk *clk; |
55ba953a JH |
149 | int irq_alarm; |
150 | int irq_timer; | |
151 | u8 interrupts_reg; | |
222a12fc | 152 | bool is_pmic_controller; |
399cf0f6 | 153 | bool has_ext_clk; |
efce21fc | 154 | bool is_suspending; |
2153f949 | 155 | const struct omap_rtc_device_type *type; |
97ea1906 | 156 | struct pinctrl_dev *pctldev; |
55ba953a | 157 | }; |
db68b189 | 158 | |
55ba953a JH |
159 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
160 | { | |
161 | return readb(rtc->base + reg); | |
162 | } | |
cab1458c | 163 | |
c253a896 JH |
164 | static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) |
165 | { | |
166 | return readl(rtc->base + reg); | |
167 | } | |
168 | ||
55ba953a JH |
169 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
170 | { | |
171 | writeb(val, rtc->base + reg); | |
172 | } | |
db68b189 | 173 | |
55ba953a JH |
174 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
175 | { | |
176 | writel(val, rtc->base + reg); | |
177 | } | |
db68b189 | 178 | |
9c28bd07 LV |
179 | static void am3352_rtc_unlock(struct omap_rtc *rtc) |
180 | { | |
181 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); | |
182 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
183 | } | |
184 | ||
185 | static void am3352_rtc_lock(struct omap_rtc *rtc) | |
186 | { | |
187 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
188 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0); | |
189 | } | |
190 | ||
191 | static void default_rtc_unlock(struct omap_rtc *rtc) | |
192 | { | |
193 | } | |
194 | ||
195 | static void default_rtc_lock(struct omap_rtc *rtc) | |
196 | { | |
197 | } | |
198 | ||
10211ae3 JH |
199 | /* |
200 | * We rely on the rtc framework to handle locking (rtc->ops_lock), | |
db68b189 DB |
201 | * so the only other requirement is that register accesses which |
202 | * require BUSY to be clear are made with IRQs locally disabled | |
203 | */ | |
55ba953a | 204 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 | 205 | { |
10211ae3 JH |
206 | int count; |
207 | u8 status; | |
db68b189 DB |
208 | |
209 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
210 | for (count = 0; count < 50; count++) { | |
55ba953a | 211 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
10211ae3 | 212 | if (!(status & OMAP_RTC_STATUS_BUSY)) |
db68b189 DB |
213 | break; |
214 | udelay(1); | |
215 | } | |
216 | /* now we have ~15 usec to read/write various registers */ | |
217 | } | |
218 | ||
55ba953a | 219 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 220 | { |
10211ae3 JH |
221 | struct omap_rtc *rtc = dev_id; |
222 | unsigned long events = 0; | |
223 | u8 irq_data; | |
db68b189 | 224 | |
55ba953a | 225 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
226 | |
227 | /* alarm irq? */ | |
228 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
9c28bd07 | 229 | rtc->type->unlock(rtc); |
55ba953a | 230 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
9c28bd07 | 231 | rtc->type->lock(rtc); |
db68b189 DB |
232 | events |= RTC_IRQF | RTC_AF; |
233 | } | |
234 | ||
235 | /* 1/sec periodic/update irq? */ | |
236 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
237 | events |= RTC_IRQF | RTC_UF; | |
238 | ||
55ba953a | 239 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
240 | |
241 | return IRQ_HANDLED; | |
242 | } | |
243 | ||
16380c15 JS |
244 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
245 | { | |
55ba953a | 246 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 247 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
248 | |
249 | local_irq_disable(); | |
55ba953a JH |
250 | rtc_wait_not_busy(rtc); |
251 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
2153f949 | 252 | if (rtc->type->has_irqwakeen) |
55ba953a | 253 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
254 | |
255 | if (enabled) { | |
16380c15 | 256 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
257 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
258 | } else { | |
16380c15 | 259 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
260 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
261 | } | |
55ba953a | 262 | rtc_wait_not_busy(rtc); |
9c28bd07 | 263 | rtc->type->unlock(rtc); |
55ba953a | 264 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 265 | if (rtc->type->has_irqwakeen) |
55ba953a | 266 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 267 | rtc->type->lock(rtc); |
16380c15 JS |
268 | local_irq_enable(); |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
db68b189 DB |
273 | /* this hardware doesn't support "don't care" alarm fields */ |
274 | static int tm2bcd(struct rtc_time *tm) | |
275 | { | |
276 | if (rtc_valid_tm(tm) != 0) | |
277 | return -EINVAL; | |
278 | ||
fe20ba70 AB |
279 | tm->tm_sec = bin2bcd(tm->tm_sec); |
280 | tm->tm_min = bin2bcd(tm->tm_min); | |
281 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
282 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 283 | |
fe20ba70 | 284 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
285 | |
286 | /* epoch == 1900 */ | |
287 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
288 | return -EINVAL; | |
fe20ba70 | 289 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
290 | |
291 | return 0; | |
292 | } | |
293 | ||
294 | static void bcd2tm(struct rtc_time *tm) | |
295 | { | |
fe20ba70 AB |
296 | tm->tm_sec = bcd2bin(tm->tm_sec); |
297 | tm->tm_min = bcd2bin(tm->tm_min); | |
298 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
299 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
300 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 301 | /* epoch == 1900 */ |
fe20ba70 | 302 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
303 | } |
304 | ||
cbbe326f | 305 | static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) |
db68b189 | 306 | { |
55ba953a JH |
307 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
308 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
309 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
310 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
311 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
312 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
cbbe326f JH |
313 | } |
314 | ||
315 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
316 | { | |
317 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
db68b189 | 318 | |
cbbe326f JH |
319 | /* we don't report wday/yday/isdst ... */ |
320 | local_irq_disable(); | |
321 | rtc_wait_not_busy(rtc); | |
322 | omap_rtc_read_time_raw(rtc, tm); | |
db68b189 DB |
323 | local_irq_enable(); |
324 | ||
325 | bcd2tm(tm); | |
10211ae3 | 326 | |
db68b189 DB |
327 | return 0; |
328 | } | |
329 | ||
330 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
331 | { | |
55ba953a JH |
332 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
333 | ||
db68b189 DB |
334 | if (tm2bcd(tm) < 0) |
335 | return -EINVAL; | |
10211ae3 | 336 | |
db68b189 | 337 | local_irq_disable(); |
55ba953a | 338 | rtc_wait_not_busy(rtc); |
db68b189 | 339 | |
9c28bd07 | 340 | rtc->type->unlock(rtc); |
55ba953a JH |
341 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
342 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
343 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
344 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
345 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
346 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
9c28bd07 | 347 | rtc->type->lock(rtc); |
db68b189 DB |
348 | |
349 | local_irq_enable(); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
355 | { | |
55ba953a | 356 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
10211ae3 | 357 | u8 interrupts; |
55ba953a | 358 | |
db68b189 | 359 | local_irq_disable(); |
55ba953a | 360 | rtc_wait_not_busy(rtc); |
db68b189 | 361 | |
55ba953a JH |
362 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
363 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
364 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
365 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
366 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
367 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
368 | |
369 | local_irq_enable(); | |
370 | ||
371 | bcd2tm(&alm->time); | |
10211ae3 JH |
372 | |
373 | interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
374 | alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); | |
db68b189 DB |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
379 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
380 | { | |
55ba953a | 381 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 382 | u8 reg, irqwake_reg = 0; |
db68b189 | 383 | |
db68b189 DB |
384 | if (tm2bcd(&alm->time) < 0) |
385 | return -EINVAL; | |
386 | ||
387 | local_irq_disable(); | |
55ba953a | 388 | rtc_wait_not_busy(rtc); |
db68b189 | 389 | |
9c28bd07 | 390 | rtc->type->unlock(rtc); |
55ba953a JH |
391 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
392 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
393 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
394 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
395 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
396 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 397 | |
55ba953a | 398 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
2153f949 | 399 | if (rtc->type->has_irqwakeen) |
55ba953a | 400 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
401 | |
402 | if (alm->enabled) { | |
db68b189 | 403 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
404 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
405 | } else { | |
db68b189 | 406 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
407 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
408 | } | |
55ba953a | 409 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 410 | if (rtc->type->has_irqwakeen) |
55ba953a | 411 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 412 | rtc->type->lock(rtc); |
db68b189 DB |
413 | |
414 | local_irq_enable(); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
222a12fc JH |
419 | static struct omap_rtc *omap_rtc_power_off_rtc; |
420 | ||
421 | /* | |
422 | * omap_rtc_poweroff: RTC-controlled power off | |
423 | * | |
424 | * The RTC can be used to control an external PMIC via the pmic_power_en pin, | |
425 | * which can be configured to transition to OFF on ALARM2 events. | |
426 | * | |
427 | * Notes: | |
428 | * The two-second alarm offset is the shortest offset possible as the alarm | |
429 | * registers must be set before the next timer update and the offset | |
430 | * calculation is too heavy for everything to be done within a single access | |
431 | * period (~15 us). | |
432 | * | |
433 | * Called with local interrupts disabled. | |
434 | */ | |
435 | static void omap_rtc_power_off(void) | |
436 | { | |
437 | struct omap_rtc *rtc = omap_rtc_power_off_rtc; | |
438 | struct rtc_time tm; | |
439 | unsigned long now; | |
440 | u32 val; | |
441 | ||
9c28bd07 | 442 | rtc->type->unlock(rtc); |
222a12fc JH |
443 | /* enable pmic_power_en control */ |
444 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
445 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); | |
446 | ||
447 | /* set alarm two seconds from now */ | |
448 | omap_rtc_read_time_raw(rtc, &tm); | |
449 | bcd2tm(&tm); | |
450 | rtc_tm_to_time(&tm, &now); | |
451 | rtc_time_to_tm(now + 2, &tm); | |
452 | ||
453 | if (tm2bcd(&tm) < 0) { | |
454 | dev_err(&rtc->rtc->dev, "power off failed\n"); | |
455 | return; | |
456 | } | |
457 | ||
458 | rtc_wait_not_busy(rtc); | |
459 | ||
460 | rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); | |
461 | rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); | |
462 | rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); | |
463 | rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); | |
464 | rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); | |
465 | rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); | |
466 | ||
467 | /* | |
468 | * enable ALARM2 interrupt | |
469 | * | |
470 | * NOTE: this fails on AM3352 if rtc_write (writeb) is used | |
471 | */ | |
472 | val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
473 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, | |
474 | val | OMAP_RTC_INTERRUPTS_IT_ALARM2); | |
9c28bd07 | 475 | rtc->type->lock(rtc); |
222a12fc JH |
476 | |
477 | /* | |
478 | * Wait for alarm to trigger (within two seconds) and external PMIC to | |
479 | * power off the system. Add a 500 ms margin for external latencies | |
480 | * (e.g. debounce circuits). | |
481 | */ | |
482 | mdelay(2500); | |
483 | } | |
484 | ||
34c7b3ac | 485 | static const struct rtc_class_ops omap_rtc_ops = { |
db68b189 DB |
486 | .read_time = omap_rtc_read_time, |
487 | .set_time = omap_rtc_set_time, | |
488 | .read_alarm = omap_rtc_read_alarm, | |
489 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 490 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
491 | }; |
492 | ||
2153f949 | 493 | static const struct omap_rtc_device_type omap_rtc_default_type = { |
9291e340 | 494 | .has_power_up_reset = true, |
9c28bd07 LV |
495 | .lock = default_rtc_lock, |
496 | .unlock = default_rtc_unlock, | |
2153f949 JH |
497 | }; |
498 | ||
499 | static const struct omap_rtc_device_type omap_rtc_am3352_type = { | |
500 | .has_32kclk_en = true, | |
2153f949 | 501 | .has_irqwakeen = true, |
222a12fc | 502 | .has_pmic_mode = true, |
9c28bd07 LV |
503 | .lock = am3352_rtc_lock, |
504 | .unlock = am3352_rtc_unlock, | |
2153f949 JH |
505 | }; |
506 | ||
507 | static const struct omap_rtc_device_type omap_rtc_da830_type = { | |
9c28bd07 LV |
508 | .lock = am3352_rtc_lock, |
509 | .unlock = am3352_rtc_unlock, | |
2153f949 | 510 | }; |
9e0344dc | 511 | |
2153f949 | 512 | static const struct platform_device_id omap_rtc_id_table[] = { |
cab1458c | 513 | { |
a430ca22 | 514 | .name = "omap_rtc", |
2153f949 JH |
515 | .driver_data = (kernel_ulong_t)&omap_rtc_default_type, |
516 | }, { | |
8af750e3 | 517 | .name = "am3352-rtc", |
2153f949 JH |
518 | .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, |
519 | }, { | |
cab1458c | 520 | .name = "da830-rtc", |
2153f949 JH |
521 | .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, |
522 | }, { | |
523 | /* sentinel */ | |
524 | } | |
cab1458c | 525 | }; |
2153f949 | 526 | MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); |
cab1458c | 527 | |
9e0344dc | 528 | static const struct of_device_id omap_rtc_of_match[] = { |
2153f949 JH |
529 | { |
530 | .compatible = "ti,am3352-rtc", | |
531 | .data = &omap_rtc_am3352_type, | |
532 | }, { | |
533 | .compatible = "ti,da830-rtc", | |
534 | .data = &omap_rtc_da830_type, | |
535 | }, { | |
536 | /* sentinel */ | |
537 | } | |
9e0344dc AM |
538 | }; |
539 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
540 | ||
97ea1906 MN |
541 | static const struct pinctrl_pin_desc rtc_pins_desc[] = { |
542 | PINCTRL_PIN(0, "ext_wakeup0"), | |
543 | PINCTRL_PIN(1, "ext_wakeup1"), | |
544 | PINCTRL_PIN(2, "ext_wakeup2"), | |
545 | PINCTRL_PIN(3, "ext_wakeup3"), | |
546 | }; | |
547 | ||
548 | static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
549 | { | |
550 | return 0; | |
551 | } | |
552 | ||
553 | static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
554 | unsigned int group) | |
555 | { | |
556 | return NULL; | |
557 | } | |
558 | ||
559 | static const struct pinctrl_ops rtc_pinctrl_ops = { | |
560 | .get_groups_count = rtc_pinctrl_get_groups_count, | |
561 | .get_group_name = rtc_pinctrl_get_group_name, | |
562 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
563 | .dt_free_map = pinconf_generic_dt_free_map, | |
564 | }; | |
565 | ||
566 | enum rtc_pin_config_param { | |
567 | PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1, | |
568 | }; | |
569 | ||
570 | static const struct pinconf_generic_params rtc_params[] = { | |
571 | {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0}, | |
572 | }; | |
573 | ||
574 | #ifdef CONFIG_DEBUG_FS | |
575 | static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = { | |
576 | PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false), | |
577 | }; | |
578 | #endif | |
579 | ||
580 | static int rtc_pinconf_get(struct pinctrl_dev *pctldev, | |
581 | unsigned int pin, unsigned long *config) | |
582 | { | |
583 | struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); | |
584 | unsigned int param = pinconf_to_config_param(*config); | |
585 | u32 val; | |
586 | u16 arg = 0; | |
587 | ||
588 | rtc->type->unlock(rtc); | |
589 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
590 | rtc->type->lock(rtc); | |
591 | ||
592 | switch (param) { | |
593 | case PIN_CONFIG_INPUT_ENABLE: | |
594 | if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin))) | |
595 | return -EINVAL; | |
596 | break; | |
597 | case PIN_CONFIG_ACTIVE_HIGH: | |
598 | if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin)) | |
599 | return -EINVAL; | |
600 | break; | |
601 | default: | |
602 | return -ENOTSUPP; | |
603 | }; | |
604 | ||
605 | *config = pinconf_to_config_packed(param, arg); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int rtc_pinconf_set(struct pinctrl_dev *pctldev, | |
611 | unsigned int pin, unsigned long *configs, | |
612 | unsigned int num_configs) | |
613 | { | |
614 | struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); | |
615 | u32 val; | |
616 | unsigned int param; | |
58957d2e | 617 | u32 param_val; |
97ea1906 MN |
618 | int i; |
619 | ||
620 | rtc->type->unlock(rtc); | |
621 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
622 | rtc->type->lock(rtc); | |
623 | ||
624 | /* active low by default */ | |
625 | val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin); | |
626 | ||
627 | for (i = 0; i < num_configs; i++) { | |
628 | param = pinconf_to_config_param(configs[i]); | |
629 | param_val = pinconf_to_config_argument(configs[i]); | |
630 | ||
631 | switch (param) { | |
632 | case PIN_CONFIG_INPUT_ENABLE: | |
633 | if (param_val) | |
634 | val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin); | |
635 | else | |
636 | val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin); | |
637 | break; | |
638 | case PIN_CONFIG_ACTIVE_HIGH: | |
639 | val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin); | |
640 | break; | |
641 | default: | |
642 | dev_err(&rtc->rtc->dev, "Property %u not supported\n", | |
643 | param); | |
644 | return -ENOTSUPP; | |
645 | } | |
646 | } | |
647 | ||
648 | rtc->type->unlock(rtc); | |
649 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val); | |
650 | rtc->type->lock(rtc); | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | static const struct pinconf_ops rtc_pinconf_ops = { | |
656 | .is_generic = true, | |
657 | .pin_config_get = rtc_pinconf_get, | |
658 | .pin_config_set = rtc_pinconf_set, | |
659 | }; | |
660 | ||
661 | static struct pinctrl_desc rtc_pinctrl_desc = { | |
662 | .pins = rtc_pins_desc, | |
663 | .npins = ARRAY_SIZE(rtc_pins_desc), | |
664 | .pctlops = &rtc_pinctrl_ops, | |
665 | .confops = &rtc_pinconf_ops, | |
666 | .custom_params = rtc_params, | |
667 | .num_custom_params = ARRAY_SIZE(rtc_params), | |
668 | #ifdef CONFIG_DEBUG_FS | |
669 | .custom_conf_items = rtc_conf_items, | |
670 | #endif | |
671 | .owner = THIS_MODULE, | |
672 | }; | |
673 | ||
b6ee15ef AB |
674 | static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val, |
675 | size_t bytes) | |
676 | { | |
677 | struct omap_rtc *rtc = priv; | |
678 | u32 *val = _val; | |
679 | int i; | |
680 | ||
681 | for (i = 0; i < bytes / 4; i++) | |
682 | val[i] = rtc_readl(rtc, | |
683 | OMAP_RTC_SCRATCH0_REG + offset + (i * 4)); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val, | |
689 | size_t bytes) | |
690 | { | |
691 | struct omap_rtc *rtc = priv; | |
692 | u32 *val = _val; | |
693 | int i; | |
694 | ||
695 | rtc->type->unlock(rtc); | |
696 | for (i = 0; i < bytes / 4; i++) | |
697 | rtc_writel(rtc, | |
698 | OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]); | |
699 | rtc->type->lock(rtc); | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | static struct nvmem_config omap_rtc_nvmem_config = { | |
705 | .name = "omap_rtc_scratch", | |
706 | .word_size = 4, | |
707 | .stride = 4, | |
708 | .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG, | |
709 | .reg_read = omap_rtc_scratch_read, | |
710 | .reg_write = omap_rtc_scratch_write, | |
711 | }; | |
712 | ||
5d9094b6 | 713 | static int omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 714 | { |
10211ae3 JH |
715 | struct omap_rtc *rtc; |
716 | struct resource *res; | |
717 | u8 reg, mask, new_ctrl; | |
cab1458c | 718 | const struct platform_device_id *id_entry; |
9e0344dc | 719 | const struct of_device_id *of_id; |
437b37a6 | 720 | int ret; |
9e0344dc | 721 | |
55ba953a JH |
722 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
723 | if (!rtc) | |
724 | return -ENOMEM; | |
725 | ||
9e0344dc | 726 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
2153f949 JH |
727 | if (of_id) { |
728 | rtc->type = of_id->data; | |
222a12fc JH |
729 | rtc->is_pmic_controller = rtc->type->has_pmic_mode && |
730 | of_property_read_bool(pdev->dev.of_node, | |
094d3ee3 | 731 | "system-power-controller"); |
2153f949 JH |
732 | } else { |
733 | id_entry = platform_get_device_id(pdev); | |
734 | rtc->type = (void *)id_entry->driver_data; | |
337b600f SN |
735 | } |
736 | ||
55ba953a JH |
737 | rtc->irq_timer = platform_get_irq(pdev, 0); |
738 | if (rtc->irq_timer <= 0) | |
db68b189 | 739 | return -ENOENT; |
db68b189 | 740 | |
55ba953a JH |
741 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
742 | if (rtc->irq_alarm <= 0) | |
db68b189 | 743 | return -ENOENT; |
db68b189 | 744 | |
399cf0f6 K |
745 | rtc->clk = devm_clk_get(&pdev->dev, "ext-clk"); |
746 | if (!IS_ERR(rtc->clk)) | |
747 | rtc->has_ext_clk = true; | |
748 | else | |
749 | rtc->clk = devm_clk_get(&pdev->dev, "int-clk"); | |
532409aa K |
750 | |
751 | if (!IS_ERR(rtc->clk)) | |
752 | clk_prepare_enable(rtc->clk); | |
753 | ||
db68b189 | 754 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
755 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
756 | if (IS_ERR(rtc->base)) | |
757 | return PTR_ERR(rtc->base); | |
758 | ||
759 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 760 | |
fc9bd902 VH |
761 | /* Enable the clock/module so that we can access the registers */ |
762 | pm_runtime_enable(&pdev->dev); | |
763 | pm_runtime_get_sync(&pdev->dev); | |
764 | ||
9c28bd07 | 765 | rtc->type->unlock(rtc); |
cab1458c | 766 | |
1ed8b5d2 JH |
767 | /* |
768 | * disable interrupts | |
769 | * | |
770 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 771 | */ |
55ba953a | 772 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 773 | |
cd914bba | 774 | /* enable RTC functional clock */ |
2153f949 | 775 | if (rtc->type->has_32kclk_en) { |
55ba953a JH |
776 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); |
777 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
778 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 779 | } |
cd914bba | 780 | |
db68b189 | 781 | /* clear old status */ |
55ba953a | 782 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
9291e340 JH |
783 | |
784 | mask = OMAP_RTC_STATUS_ALARM; | |
785 | ||
222a12fc JH |
786 | if (rtc->type->has_pmic_mode) |
787 | mask |= OMAP_RTC_STATUS_ALARM2; | |
788 | ||
9291e340 JH |
789 | if (rtc->type->has_power_up_reset) { |
790 | mask |= OMAP_RTC_STATUS_POWER_UP; | |
791 | if (reg & OMAP_RTC_STATUS_POWER_UP) | |
792 | dev_info(&pdev->dev, "RTC power up reset detected\n"); | |
db68b189 | 793 | } |
9291e340 JH |
794 | |
795 | if (reg & mask) | |
796 | rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); | |
db68b189 | 797 | |
db68b189 | 798 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 799 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
10211ae3 | 800 | if (reg & OMAP_RTC_CTRL_STOP) |
397b630a | 801 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
802 | |
803 | /* force to 24 hour mode */ | |
10211ae3 | 804 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
805 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
806 | ||
10211ae3 JH |
807 | /* |
808 | * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
db68b189 | 809 | * |
fa5b0782 SN |
810 | * - Device wake-up capability setting should come through chip |
811 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
812 | * flag in the platform device if the board is wired right for | |
813 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
814 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
815 | * |
816 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
817 | * rather than nPWRON_RESET, should forcibly enable split | |
818 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
819 | * is write-only, and always reads as zero...) | |
820 | */ | |
db68b189 | 821 | |
10211ae3 | 822 | if (new_ctrl & OMAP_RTC_CTRL_SPLIT) |
397b630a | 823 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
824 | |
825 | if (reg != new_ctrl) | |
55ba953a | 826 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 827 | |
399cf0f6 K |
828 | /* |
829 | * If we have the external clock then switch to it so we can keep | |
830 | * ticking across suspend. | |
831 | */ | |
832 | if (rtc->has_ext_clk) { | |
833 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); | |
3984903a LV |
834 | reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; |
835 | reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; | |
836 | rtc_writel(rtc, OMAP_RTC_OSC_REG, reg); | |
399cf0f6 K |
837 | } |
838 | ||
9c28bd07 LV |
839 | rtc->type->lock(rtc); |
840 | ||
4390ce00 JH |
841 | device_init_wakeup(&pdev->dev, true); |
842 | ||
57072758 | 843 | rtc->rtc = devm_rtc_allocate_device(&pdev->dev); |
55ba953a JH |
844 | if (IS_ERR(rtc->rtc)) { |
845 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
846 | goto err; |
847 | } | |
4390ce00 | 848 | |
57072758 | 849 | rtc->rtc->ops = &omap_rtc_ops; |
b6ee15ef AB |
850 | omap_rtc_nvmem_config.priv = rtc; |
851 | rtc->rtc->nvmem_config = &omap_rtc_nvmem_config; | |
57072758 | 852 | |
4390ce00 | 853 | /* handle periodic and alarm irqs */ |
55ba953a JH |
854 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
855 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
856 | if (ret) |
857 | goto err; | |
858 | ||
55ba953a JH |
859 | if (rtc->irq_timer != rtc->irq_alarm) { |
860 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
861 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
862 | if (ret) |
863 | goto err; | |
864 | } | |
865 | ||
222a12fc JH |
866 | if (rtc->is_pmic_controller) { |
867 | if (!pm_power_off) { | |
868 | omap_rtc_power_off_rtc = rtc; | |
869 | pm_power_off = omap_rtc_power_off; | |
870 | } | |
871 | } | |
872 | ||
97ea1906 MN |
873 | /* Support ext_wakeup pinconf */ |
874 | rtc_pinctrl_desc.name = dev_name(&pdev->dev); | |
875 | ||
876 | rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc); | |
877 | if (IS_ERR(rtc->pctldev)) { | |
878 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
26e480f7 AB |
879 | ret = PTR_ERR(rtc->pctldev); |
880 | goto err; | |
97ea1906 MN |
881 | } |
882 | ||
57072758 AB |
883 | ret = rtc_register_device(rtc->rtc); |
884 | if (ret) | |
885 | goto err; | |
886 | ||
db68b189 DB |
887 | return 0; |
888 | ||
437b37a6 | 889 | err: |
7ecd9a3f | 890 | device_init_wakeup(&pdev->dev, false); |
9c28bd07 | 891 | rtc->type->lock(rtc); |
fc9bd902 VH |
892 | pm_runtime_put_sync(&pdev->dev); |
893 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
894 | |
895 | return ret; | |
db68b189 DB |
896 | } |
897 | ||
b9de1a1d | 898 | static int omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 899 | { |
55ba953a | 900 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
399cf0f6 | 901 | u8 reg; |
db68b189 | 902 | |
222a12fc JH |
903 | if (pm_power_off == omap_rtc_power_off && |
904 | omap_rtc_power_off_rtc == rtc) { | |
905 | pm_power_off = NULL; | |
906 | omap_rtc_power_off_rtc = NULL; | |
907 | } | |
908 | ||
db68b189 DB |
909 | device_init_wakeup(&pdev->dev, 0); |
910 | ||
532409aa K |
911 | if (!IS_ERR(rtc->clk)) |
912 | clk_disable_unprepare(rtc->clk); | |
913 | ||
9c28bd07 | 914 | rtc->type->unlock(rtc); |
db68b189 | 915 | /* leave rtc running, but disable irqs */ |
55ba953a | 916 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 917 | |
399cf0f6 K |
918 | if (rtc->has_ext_clk) { |
919 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); | |
920 | reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC; | |
921 | rtc_write(rtc, OMAP_RTC_OSC_REG, reg); | |
922 | } | |
923 | ||
9c28bd07 | 924 | rtc->type->lock(rtc); |
fc9bd902 VH |
925 | |
926 | /* Disable the clock/module */ | |
927 | pm_runtime_put_sync(&pdev->dev); | |
928 | pm_runtime_disable(&pdev->dev); | |
929 | ||
97ea1906 MN |
930 | /* Remove ext_wakeup pinconf */ |
931 | pinctrl_unregister(rtc->pctldev); | |
932 | ||
db68b189 DB |
933 | return 0; |
934 | } | |
935 | ||
0c749eac | 936 | static int __maybe_unused omap_rtc_suspend(struct device *dev) |
db68b189 | 937 | { |
55ba953a JH |
938 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
939 | ||
940 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 | 941 | |
9c28bd07 | 942 | rtc->type->unlock(rtc); |
10211ae3 JH |
943 | /* |
944 | * FIXME: the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
945 | * source on some platforms, and in fact this enable() call is just |
946 | * saving a flag that's never used... | |
db68b189 | 947 | */ |
ab7f580b | 948 | if (device_may_wakeup(dev)) |
55ba953a | 949 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 950 | else |
55ba953a | 951 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
9c28bd07 | 952 | rtc->type->lock(rtc); |
db68b189 | 953 | |
efce21fc | 954 | rtc->is_suspending = true; |
fc9bd902 | 955 | |
db68b189 DB |
956 | return 0; |
957 | } | |
958 | ||
0c749eac | 959 | static int __maybe_unused omap_rtc_resume(struct device *dev) |
db68b189 | 960 | { |
55ba953a JH |
961 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
962 | ||
9c28bd07 | 963 | rtc->type->unlock(rtc); |
ab7f580b | 964 | if (device_may_wakeup(dev)) |
55ba953a | 965 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 966 | else |
55ba953a | 967 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
9c28bd07 | 968 | rtc->type->lock(rtc); |
ab7f580b | 969 | |
efce21fc TK |
970 | rtc->is_suspending = false; |
971 | ||
db68b189 DB |
972 | return 0; |
973 | } | |
db68b189 | 974 | |
0c749eac | 975 | static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev) |
efce21fc TK |
976 | { |
977 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
978 | ||
979 | if (rtc->is_suspending && !rtc->has_ext_clk) | |
980 | return -EBUSY; | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
efce21fc TK |
985 | static const struct dev_pm_ops omap_rtc_pm_ops = { |
986 | SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume) | |
0c749eac | 987 | SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL) |
efce21fc | 988 | }; |
04ebc359 | 989 | |
db68b189 DB |
990 | static void omap_rtc_shutdown(struct platform_device *pdev) |
991 | { | |
55ba953a | 992 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
8ad5c722 | 993 | u8 mask; |
55ba953a | 994 | |
8ad5c722 JH |
995 | /* |
996 | * Keep the ALARM interrupt enabled to allow the system to power up on | |
997 | * alarm events. | |
998 | */ | |
9c28bd07 | 999 | rtc->type->unlock(rtc); |
8ad5c722 JH |
1000 | mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
1001 | mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; | |
1002 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); | |
9c28bd07 | 1003 | rtc->type->lock(rtc); |
db68b189 DB |
1004 | } |
1005 | ||
db68b189 | 1006 | static struct platform_driver omap_rtc_driver = { |
5d9094b6 | 1007 | .probe = omap_rtc_probe, |
b9de1a1d | 1008 | .remove = omap_rtc_remove, |
db68b189 DB |
1009 | .shutdown = omap_rtc_shutdown, |
1010 | .driver = { | |
a430ca22 | 1011 | .name = "omap_rtc", |
04ebc359 | 1012 | .pm = &omap_rtc_pm_ops, |
616b7341 | 1013 | .of_match_table = omap_rtc_of_match, |
db68b189 | 1014 | }, |
2153f949 | 1015 | .id_table = omap_rtc_id_table, |
db68b189 DB |
1016 | }; |
1017 | ||
5d9094b6 | 1018 | module_platform_driver(omap_rtc_driver); |
db68b189 | 1019 | |
a430ca22 | 1020 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 DB |
1021 | MODULE_AUTHOR("George G. Davis (and others)"); |
1022 | MODULE_LICENSE("GPL"); |