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db68b189 | 1 | /* |
10211ae3 | 2 | * TI OMAP Real Time Clock interface for Linux |
db68b189 DB |
3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
0125138d | 8 | * Copyright (C) 2014 Johan Hovold <johan@kernel.org> |
db68b189 DB |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/rtc.h> | |
22 | #include <linux/bcd.h> | |
23 | #include <linux/platform_device.h> | |
9e0344dc AM |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
fc9bd902 | 26 | #include <linux/pm_runtime.h> |
4b30c9fc | 27 | #include <linux/io.h> |
532409aa | 28 | #include <linux/clk.h> |
db68b189 | 29 | |
10211ae3 JH |
30 | /* |
31 | * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock | |
db68b189 DB |
32 | * with century-range alarm matching, driven by the 32kHz clock. |
33 | * | |
34 | * The main user-visible ways it differs from PC RTCs are by omitting | |
35 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
36 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
37 | * | |
38 | * Board-specific wiring options include using split power mode with | |
39 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
40 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
41 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
42 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
43 | */ |
44 | ||
db68b189 DB |
45 | /* RTC registers */ |
46 | #define OMAP_RTC_SECONDS_REG 0x00 | |
47 | #define OMAP_RTC_MINUTES_REG 0x04 | |
48 | #define OMAP_RTC_HOURS_REG 0x08 | |
49 | #define OMAP_RTC_DAYS_REG 0x0C | |
50 | #define OMAP_RTC_MONTHS_REG 0x10 | |
51 | #define OMAP_RTC_YEARS_REG 0x14 | |
52 | #define OMAP_RTC_WEEKS_REG 0x18 | |
53 | ||
54 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
55 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
56 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
57 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
58 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
59 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
60 | ||
61 | #define OMAP_RTC_CTRL_REG 0x40 | |
62 | #define OMAP_RTC_STATUS_REG 0x44 | |
63 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
64 | ||
65 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
66 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
67 | #define OMAP_RTC_OSC_REG 0x54 | |
68 | ||
cab1458c AM |
69 | #define OMAP_RTC_KICK0_REG 0x6c |
70 | #define OMAP_RTC_KICK1_REG 0x70 | |
71 | ||
8af750e3 HG |
72 | #define OMAP_RTC_IRQWAKEEN 0x7c |
73 | ||
222a12fc JH |
74 | #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 |
75 | #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 | |
76 | #define OMAP_RTC_ALARM2_HOURS_REG 0x88 | |
77 | #define OMAP_RTC_ALARM2_DAYS_REG 0x8c | |
78 | #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 | |
79 | #define OMAP_RTC_ALARM2_YEARS_REG 0x94 | |
80 | ||
81 | #define OMAP_RTC_PMIC_REG 0x98 | |
82 | ||
db68b189 | 83 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
84 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
85 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
86 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
87 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
88 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
89 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
90 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
91 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
92 | |
93 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a | 94 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
222a12fc | 95 | #define OMAP_RTC_STATUS_ALARM2 BIT(7) |
92adb96a SN |
96 | #define OMAP_RTC_STATUS_ALARM BIT(6) |
97 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
98 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
99 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
100 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
101 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
102 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
103 | |
104 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
222a12fc | 105 | #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) |
92adb96a SN |
106 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
107 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 108 | |
cd914bba SN |
109 | /* OMAP_RTC_OSC_REG bit fields: */ |
110 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
111 | ||
8af750e3 | 112 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 113 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 114 | |
222a12fc JH |
115 | /* OMAP_RTC_PMIC bit fields: */ |
116 | #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) | |
117 | ||
cab1458c AM |
118 | /* OMAP_RTC_KICKER values */ |
119 | #define KICK0_VALUE 0x83e70b13 | |
120 | #define KICK1_VALUE 0x95a4f1e0 | |
121 | ||
9c28bd07 LV |
122 | struct omap_rtc; |
123 | ||
2153f949 JH |
124 | struct omap_rtc_device_type { |
125 | bool has_32kclk_en; | |
2153f949 | 126 | bool has_irqwakeen; |
222a12fc | 127 | bool has_pmic_mode; |
9291e340 | 128 | bool has_power_up_reset; |
9c28bd07 LV |
129 | void (*lock)(struct omap_rtc *rtc); |
130 | void (*unlock)(struct omap_rtc *rtc); | |
2153f949 | 131 | }; |
cd914bba | 132 | |
55ba953a JH |
133 | struct omap_rtc { |
134 | struct rtc_device *rtc; | |
135 | void __iomem *base; | |
532409aa | 136 | struct clk *clk; |
55ba953a JH |
137 | int irq_alarm; |
138 | int irq_timer; | |
139 | u8 interrupts_reg; | |
222a12fc | 140 | bool is_pmic_controller; |
2153f949 | 141 | const struct omap_rtc_device_type *type; |
55ba953a | 142 | }; |
db68b189 | 143 | |
55ba953a JH |
144 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
145 | { | |
146 | return readb(rtc->base + reg); | |
147 | } | |
cab1458c | 148 | |
c253a896 JH |
149 | static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) |
150 | { | |
151 | return readl(rtc->base + reg); | |
152 | } | |
153 | ||
55ba953a JH |
154 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
155 | { | |
156 | writeb(val, rtc->base + reg); | |
157 | } | |
db68b189 | 158 | |
55ba953a JH |
159 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
160 | { | |
161 | writel(val, rtc->base + reg); | |
162 | } | |
db68b189 | 163 | |
9c28bd07 LV |
164 | static void am3352_rtc_unlock(struct omap_rtc *rtc) |
165 | { | |
166 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); | |
167 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
168 | } | |
169 | ||
170 | static void am3352_rtc_lock(struct omap_rtc *rtc) | |
171 | { | |
172 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
173 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0); | |
174 | } | |
175 | ||
176 | static void default_rtc_unlock(struct omap_rtc *rtc) | |
177 | { | |
178 | } | |
179 | ||
180 | static void default_rtc_lock(struct omap_rtc *rtc) | |
181 | { | |
182 | } | |
183 | ||
10211ae3 JH |
184 | /* |
185 | * We rely on the rtc framework to handle locking (rtc->ops_lock), | |
db68b189 DB |
186 | * so the only other requirement is that register accesses which |
187 | * require BUSY to be clear are made with IRQs locally disabled | |
188 | */ | |
55ba953a | 189 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 | 190 | { |
10211ae3 JH |
191 | int count; |
192 | u8 status; | |
db68b189 DB |
193 | |
194 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
195 | for (count = 0; count < 50; count++) { | |
55ba953a | 196 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
10211ae3 | 197 | if (!(status & OMAP_RTC_STATUS_BUSY)) |
db68b189 DB |
198 | break; |
199 | udelay(1); | |
200 | } | |
201 | /* now we have ~15 usec to read/write various registers */ | |
202 | } | |
203 | ||
55ba953a | 204 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 205 | { |
10211ae3 JH |
206 | struct omap_rtc *rtc = dev_id; |
207 | unsigned long events = 0; | |
208 | u8 irq_data; | |
db68b189 | 209 | |
55ba953a | 210 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
211 | |
212 | /* alarm irq? */ | |
213 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
9c28bd07 | 214 | rtc->type->unlock(rtc); |
55ba953a | 215 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
9c28bd07 | 216 | rtc->type->lock(rtc); |
db68b189 DB |
217 | events |= RTC_IRQF | RTC_AF; |
218 | } | |
219 | ||
220 | /* 1/sec periodic/update irq? */ | |
221 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
222 | events |= RTC_IRQF | RTC_UF; | |
223 | ||
55ba953a | 224 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
225 | |
226 | return IRQ_HANDLED; | |
227 | } | |
228 | ||
16380c15 JS |
229 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
230 | { | |
55ba953a | 231 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 232 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
233 | |
234 | local_irq_disable(); | |
55ba953a JH |
235 | rtc_wait_not_busy(rtc); |
236 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
2153f949 | 237 | if (rtc->type->has_irqwakeen) |
55ba953a | 238 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
239 | |
240 | if (enabled) { | |
16380c15 | 241 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
242 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
243 | } else { | |
16380c15 | 244 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
245 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
246 | } | |
55ba953a | 247 | rtc_wait_not_busy(rtc); |
9c28bd07 | 248 | rtc->type->unlock(rtc); |
55ba953a | 249 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 250 | if (rtc->type->has_irqwakeen) |
55ba953a | 251 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 252 | rtc->type->lock(rtc); |
16380c15 JS |
253 | local_irq_enable(); |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
db68b189 DB |
258 | /* this hardware doesn't support "don't care" alarm fields */ |
259 | static int tm2bcd(struct rtc_time *tm) | |
260 | { | |
261 | if (rtc_valid_tm(tm) != 0) | |
262 | return -EINVAL; | |
263 | ||
fe20ba70 AB |
264 | tm->tm_sec = bin2bcd(tm->tm_sec); |
265 | tm->tm_min = bin2bcd(tm->tm_min); | |
266 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
267 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 268 | |
fe20ba70 | 269 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
270 | |
271 | /* epoch == 1900 */ | |
272 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
273 | return -EINVAL; | |
fe20ba70 | 274 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
275 | |
276 | return 0; | |
277 | } | |
278 | ||
279 | static void bcd2tm(struct rtc_time *tm) | |
280 | { | |
fe20ba70 AB |
281 | tm->tm_sec = bcd2bin(tm->tm_sec); |
282 | tm->tm_min = bcd2bin(tm->tm_min); | |
283 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
284 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
285 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 286 | /* epoch == 1900 */ |
fe20ba70 | 287 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
288 | } |
289 | ||
cbbe326f | 290 | static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) |
db68b189 | 291 | { |
55ba953a JH |
292 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
293 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
294 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
295 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
296 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
297 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
cbbe326f JH |
298 | } |
299 | ||
300 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
301 | { | |
302 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
db68b189 | 303 | |
cbbe326f JH |
304 | /* we don't report wday/yday/isdst ... */ |
305 | local_irq_disable(); | |
306 | rtc_wait_not_busy(rtc); | |
307 | omap_rtc_read_time_raw(rtc, tm); | |
db68b189 DB |
308 | local_irq_enable(); |
309 | ||
310 | bcd2tm(tm); | |
10211ae3 | 311 | |
db68b189 DB |
312 | return 0; |
313 | } | |
314 | ||
315 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
316 | { | |
55ba953a JH |
317 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
318 | ||
db68b189 DB |
319 | if (tm2bcd(tm) < 0) |
320 | return -EINVAL; | |
10211ae3 | 321 | |
db68b189 | 322 | local_irq_disable(); |
55ba953a | 323 | rtc_wait_not_busy(rtc); |
db68b189 | 324 | |
9c28bd07 | 325 | rtc->type->unlock(rtc); |
55ba953a JH |
326 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
327 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
328 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
329 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
330 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
331 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
9c28bd07 | 332 | rtc->type->lock(rtc); |
db68b189 DB |
333 | |
334 | local_irq_enable(); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
340 | { | |
55ba953a | 341 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
10211ae3 | 342 | u8 interrupts; |
55ba953a | 343 | |
db68b189 | 344 | local_irq_disable(); |
55ba953a | 345 | rtc_wait_not_busy(rtc); |
db68b189 | 346 | |
55ba953a JH |
347 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
348 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
349 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
350 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
351 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
352 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
353 | |
354 | local_irq_enable(); | |
355 | ||
356 | bcd2tm(&alm->time); | |
10211ae3 JH |
357 | |
358 | interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
359 | alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); | |
db68b189 DB |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
365 | { | |
55ba953a | 366 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 367 | u8 reg, irqwake_reg = 0; |
db68b189 | 368 | |
db68b189 DB |
369 | if (tm2bcd(&alm->time) < 0) |
370 | return -EINVAL; | |
371 | ||
372 | local_irq_disable(); | |
55ba953a | 373 | rtc_wait_not_busy(rtc); |
db68b189 | 374 | |
9c28bd07 | 375 | rtc->type->unlock(rtc); |
55ba953a JH |
376 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
377 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
378 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
379 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
380 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
381 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 382 | |
55ba953a | 383 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
2153f949 | 384 | if (rtc->type->has_irqwakeen) |
55ba953a | 385 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
386 | |
387 | if (alm->enabled) { | |
db68b189 | 388 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
389 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
390 | } else { | |
db68b189 | 391 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
392 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
393 | } | |
55ba953a | 394 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 395 | if (rtc->type->has_irqwakeen) |
55ba953a | 396 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 397 | rtc->type->lock(rtc); |
db68b189 DB |
398 | |
399 | local_irq_enable(); | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
222a12fc JH |
404 | static struct omap_rtc *omap_rtc_power_off_rtc; |
405 | ||
406 | /* | |
407 | * omap_rtc_poweroff: RTC-controlled power off | |
408 | * | |
409 | * The RTC can be used to control an external PMIC via the pmic_power_en pin, | |
410 | * which can be configured to transition to OFF on ALARM2 events. | |
411 | * | |
412 | * Notes: | |
413 | * The two-second alarm offset is the shortest offset possible as the alarm | |
414 | * registers must be set before the next timer update and the offset | |
415 | * calculation is too heavy for everything to be done within a single access | |
416 | * period (~15 us). | |
417 | * | |
418 | * Called with local interrupts disabled. | |
419 | */ | |
420 | static void omap_rtc_power_off(void) | |
421 | { | |
422 | struct omap_rtc *rtc = omap_rtc_power_off_rtc; | |
423 | struct rtc_time tm; | |
424 | unsigned long now; | |
425 | u32 val; | |
426 | ||
9c28bd07 | 427 | rtc->type->unlock(rtc); |
222a12fc JH |
428 | /* enable pmic_power_en control */ |
429 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
430 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); | |
431 | ||
432 | /* set alarm two seconds from now */ | |
433 | omap_rtc_read_time_raw(rtc, &tm); | |
434 | bcd2tm(&tm); | |
435 | rtc_tm_to_time(&tm, &now); | |
436 | rtc_time_to_tm(now + 2, &tm); | |
437 | ||
438 | if (tm2bcd(&tm) < 0) { | |
439 | dev_err(&rtc->rtc->dev, "power off failed\n"); | |
440 | return; | |
441 | } | |
442 | ||
443 | rtc_wait_not_busy(rtc); | |
444 | ||
445 | rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); | |
446 | rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); | |
447 | rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); | |
448 | rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); | |
449 | rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); | |
450 | rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); | |
451 | ||
452 | /* | |
453 | * enable ALARM2 interrupt | |
454 | * | |
455 | * NOTE: this fails on AM3352 if rtc_write (writeb) is used | |
456 | */ | |
457 | val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
458 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, | |
459 | val | OMAP_RTC_INTERRUPTS_IT_ALARM2); | |
9c28bd07 | 460 | rtc->type->lock(rtc); |
222a12fc JH |
461 | |
462 | /* | |
463 | * Wait for alarm to trigger (within two seconds) and external PMIC to | |
464 | * power off the system. Add a 500 ms margin for external latencies | |
465 | * (e.g. debounce circuits). | |
466 | */ | |
467 | mdelay(2500); | |
468 | } | |
469 | ||
db68b189 | 470 | static struct rtc_class_ops omap_rtc_ops = { |
db68b189 DB |
471 | .read_time = omap_rtc_read_time, |
472 | .set_time = omap_rtc_set_time, | |
473 | .read_alarm = omap_rtc_read_alarm, | |
474 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 475 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
476 | }; |
477 | ||
2153f949 | 478 | static const struct omap_rtc_device_type omap_rtc_default_type = { |
9291e340 | 479 | .has_power_up_reset = true, |
9c28bd07 LV |
480 | .lock = default_rtc_lock, |
481 | .unlock = default_rtc_unlock, | |
2153f949 JH |
482 | }; |
483 | ||
484 | static const struct omap_rtc_device_type omap_rtc_am3352_type = { | |
485 | .has_32kclk_en = true, | |
2153f949 | 486 | .has_irqwakeen = true, |
222a12fc | 487 | .has_pmic_mode = true, |
9c28bd07 LV |
488 | .lock = am3352_rtc_lock, |
489 | .unlock = am3352_rtc_unlock, | |
2153f949 JH |
490 | }; |
491 | ||
492 | static const struct omap_rtc_device_type omap_rtc_da830_type = { | |
9c28bd07 LV |
493 | .lock = am3352_rtc_lock, |
494 | .unlock = am3352_rtc_unlock, | |
2153f949 | 495 | }; |
9e0344dc | 496 | |
2153f949 | 497 | static const struct platform_device_id omap_rtc_id_table[] = { |
cab1458c | 498 | { |
a430ca22 | 499 | .name = "omap_rtc", |
2153f949 JH |
500 | .driver_data = (kernel_ulong_t)&omap_rtc_default_type, |
501 | }, { | |
8af750e3 | 502 | .name = "am3352-rtc", |
2153f949 JH |
503 | .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, |
504 | }, { | |
cab1458c | 505 | .name = "da830-rtc", |
2153f949 JH |
506 | .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, |
507 | }, { | |
508 | /* sentinel */ | |
509 | } | |
cab1458c | 510 | }; |
2153f949 | 511 | MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); |
cab1458c | 512 | |
9e0344dc | 513 | static const struct of_device_id omap_rtc_of_match[] = { |
2153f949 JH |
514 | { |
515 | .compatible = "ti,am3352-rtc", | |
516 | .data = &omap_rtc_am3352_type, | |
517 | }, { | |
518 | .compatible = "ti,da830-rtc", | |
519 | .data = &omap_rtc_da830_type, | |
520 | }, { | |
521 | /* sentinel */ | |
522 | } | |
9e0344dc AM |
523 | }; |
524 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
525 | ||
5d9094b6 | 526 | static int omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 527 | { |
10211ae3 JH |
528 | struct omap_rtc *rtc; |
529 | struct resource *res; | |
530 | u8 reg, mask, new_ctrl; | |
cab1458c | 531 | const struct platform_device_id *id_entry; |
9e0344dc | 532 | const struct of_device_id *of_id; |
437b37a6 | 533 | int ret; |
9e0344dc | 534 | |
55ba953a JH |
535 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
536 | if (!rtc) | |
537 | return -ENOMEM; | |
538 | ||
9e0344dc | 539 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
2153f949 JH |
540 | if (of_id) { |
541 | rtc->type = of_id->data; | |
222a12fc JH |
542 | rtc->is_pmic_controller = rtc->type->has_pmic_mode && |
543 | of_property_read_bool(pdev->dev.of_node, | |
094d3ee3 | 544 | "system-power-controller"); |
2153f949 JH |
545 | } else { |
546 | id_entry = platform_get_device_id(pdev); | |
547 | rtc->type = (void *)id_entry->driver_data; | |
337b600f SN |
548 | } |
549 | ||
55ba953a JH |
550 | rtc->irq_timer = platform_get_irq(pdev, 0); |
551 | if (rtc->irq_timer <= 0) | |
db68b189 | 552 | return -ENOENT; |
db68b189 | 553 | |
55ba953a JH |
554 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
555 | if (rtc->irq_alarm <= 0) | |
db68b189 | 556 | return -ENOENT; |
db68b189 | 557 | |
532409aa K |
558 | rtc->clk = devm_clk_get(&pdev->dev, "int-clk"); |
559 | ||
560 | if (!IS_ERR(rtc->clk)) | |
561 | clk_prepare_enable(rtc->clk); | |
562 | ||
db68b189 | 563 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
564 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
565 | if (IS_ERR(rtc->base)) | |
566 | return PTR_ERR(rtc->base); | |
567 | ||
568 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 569 | |
fc9bd902 VH |
570 | /* Enable the clock/module so that we can access the registers */ |
571 | pm_runtime_enable(&pdev->dev); | |
572 | pm_runtime_get_sync(&pdev->dev); | |
573 | ||
9c28bd07 | 574 | rtc->type->unlock(rtc); |
cab1458c | 575 | |
1ed8b5d2 JH |
576 | /* |
577 | * disable interrupts | |
578 | * | |
579 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 580 | */ |
55ba953a | 581 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 582 | |
cd914bba | 583 | /* enable RTC functional clock */ |
2153f949 | 584 | if (rtc->type->has_32kclk_en) { |
55ba953a JH |
585 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); |
586 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
587 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 588 | } |
cd914bba | 589 | |
db68b189 | 590 | /* clear old status */ |
55ba953a | 591 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
9291e340 JH |
592 | |
593 | mask = OMAP_RTC_STATUS_ALARM; | |
594 | ||
222a12fc JH |
595 | if (rtc->type->has_pmic_mode) |
596 | mask |= OMAP_RTC_STATUS_ALARM2; | |
597 | ||
9291e340 JH |
598 | if (rtc->type->has_power_up_reset) { |
599 | mask |= OMAP_RTC_STATUS_POWER_UP; | |
600 | if (reg & OMAP_RTC_STATUS_POWER_UP) | |
601 | dev_info(&pdev->dev, "RTC power up reset detected\n"); | |
db68b189 | 602 | } |
9291e340 JH |
603 | |
604 | if (reg & mask) | |
605 | rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); | |
db68b189 | 606 | |
db68b189 | 607 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 608 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
10211ae3 | 609 | if (reg & OMAP_RTC_CTRL_STOP) |
397b630a | 610 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
611 | |
612 | /* force to 24 hour mode */ | |
10211ae3 | 613 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
614 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
615 | ||
10211ae3 JH |
616 | /* |
617 | * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
db68b189 | 618 | * |
fa5b0782 SN |
619 | * - Device wake-up capability setting should come through chip |
620 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
621 | * flag in the platform device if the board is wired right for | |
622 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
623 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
624 | * |
625 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
626 | * rather than nPWRON_RESET, should forcibly enable split | |
627 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
628 | * is write-only, and always reads as zero...) | |
629 | */ | |
db68b189 | 630 | |
10211ae3 | 631 | if (new_ctrl & OMAP_RTC_CTRL_SPLIT) |
397b630a | 632 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
633 | |
634 | if (reg != new_ctrl) | |
55ba953a | 635 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 636 | |
9c28bd07 LV |
637 | rtc->type->lock(rtc); |
638 | ||
4390ce00 JH |
639 | device_init_wakeup(&pdev->dev, true); |
640 | ||
55ba953a | 641 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
4390ce00 | 642 | &omap_rtc_ops, THIS_MODULE); |
55ba953a JH |
643 | if (IS_ERR(rtc->rtc)) { |
644 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
645 | goto err; |
646 | } | |
4390ce00 JH |
647 | |
648 | /* handle periodic and alarm irqs */ | |
55ba953a JH |
649 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
650 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
651 | if (ret) |
652 | goto err; | |
653 | ||
55ba953a JH |
654 | if (rtc->irq_timer != rtc->irq_alarm) { |
655 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
656 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
657 | if (ret) |
658 | goto err; | |
659 | } | |
660 | ||
222a12fc JH |
661 | if (rtc->is_pmic_controller) { |
662 | if (!pm_power_off) { | |
663 | omap_rtc_power_off_rtc = rtc; | |
664 | pm_power_off = omap_rtc_power_off; | |
665 | } | |
666 | } | |
667 | ||
db68b189 DB |
668 | return 0; |
669 | ||
437b37a6 | 670 | err: |
7ecd9a3f | 671 | device_init_wakeup(&pdev->dev, false); |
9c28bd07 | 672 | rtc->type->lock(rtc); |
fc9bd902 VH |
673 | pm_runtime_put_sync(&pdev->dev); |
674 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
675 | |
676 | return ret; | |
db68b189 DB |
677 | } |
678 | ||
71fc8224 | 679 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 680 | { |
55ba953a | 681 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
db68b189 | 682 | |
222a12fc JH |
683 | if (pm_power_off == omap_rtc_power_off && |
684 | omap_rtc_power_off_rtc == rtc) { | |
685 | pm_power_off = NULL; | |
686 | omap_rtc_power_off_rtc = NULL; | |
687 | } | |
688 | ||
db68b189 DB |
689 | device_init_wakeup(&pdev->dev, 0); |
690 | ||
532409aa K |
691 | if (!IS_ERR(rtc->clk)) |
692 | clk_disable_unprepare(rtc->clk); | |
693 | ||
9c28bd07 | 694 | rtc->type->unlock(rtc); |
db68b189 | 695 | /* leave rtc running, but disable irqs */ |
55ba953a | 696 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 697 | |
9c28bd07 | 698 | rtc->type->lock(rtc); |
fc9bd902 VH |
699 | |
700 | /* Disable the clock/module */ | |
701 | pm_runtime_put_sync(&pdev->dev); | |
702 | pm_runtime_disable(&pdev->dev); | |
703 | ||
db68b189 DB |
704 | return 0; |
705 | } | |
706 | ||
04ebc359 | 707 | #ifdef CONFIG_PM_SLEEP |
04ebc359 | 708 | static int omap_rtc_suspend(struct device *dev) |
db68b189 | 709 | { |
55ba953a JH |
710 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
711 | ||
712 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 | 713 | |
9c28bd07 | 714 | rtc->type->unlock(rtc); |
10211ae3 JH |
715 | /* |
716 | * FIXME: the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
717 | * source on some platforms, and in fact this enable() call is just |
718 | * saving a flag that's never used... | |
db68b189 | 719 | */ |
ab7f580b | 720 | if (device_may_wakeup(dev)) |
55ba953a | 721 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 722 | else |
55ba953a | 723 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
9c28bd07 | 724 | rtc->type->lock(rtc); |
db68b189 | 725 | |
fc9bd902 | 726 | /* Disable the clock/module */ |
04ebc359 | 727 | pm_runtime_put_sync(dev); |
fc9bd902 | 728 | |
db68b189 DB |
729 | return 0; |
730 | } | |
731 | ||
04ebc359 | 732 | static int omap_rtc_resume(struct device *dev) |
db68b189 | 733 | { |
55ba953a JH |
734 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
735 | ||
fc9bd902 | 736 | /* Enable the clock/module so that we can access the registers */ |
04ebc359 | 737 | pm_runtime_get_sync(dev); |
fc9bd902 | 738 | |
9c28bd07 | 739 | rtc->type->unlock(rtc); |
ab7f580b | 740 | if (device_may_wakeup(dev)) |
55ba953a | 741 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 742 | else |
55ba953a | 743 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
9c28bd07 | 744 | rtc->type->lock(rtc); |
ab7f580b | 745 | |
db68b189 DB |
746 | return 0; |
747 | } | |
db68b189 DB |
748 | #endif |
749 | ||
04ebc359 JH |
750 | static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); |
751 | ||
db68b189 DB |
752 | static void omap_rtc_shutdown(struct platform_device *pdev) |
753 | { | |
55ba953a | 754 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
8ad5c722 | 755 | u8 mask; |
55ba953a | 756 | |
8ad5c722 JH |
757 | /* |
758 | * Keep the ALARM interrupt enabled to allow the system to power up on | |
759 | * alarm events. | |
760 | */ | |
9c28bd07 | 761 | rtc->type->unlock(rtc); |
8ad5c722 JH |
762 | mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
763 | mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; | |
764 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); | |
9c28bd07 | 765 | rtc->type->lock(rtc); |
db68b189 DB |
766 | } |
767 | ||
db68b189 | 768 | static struct platform_driver omap_rtc_driver = { |
5d9094b6 | 769 | .probe = omap_rtc_probe, |
71fc8224 | 770 | .remove = __exit_p(omap_rtc_remove), |
db68b189 DB |
771 | .shutdown = omap_rtc_shutdown, |
772 | .driver = { | |
a430ca22 | 773 | .name = "omap_rtc", |
04ebc359 | 774 | .pm = &omap_rtc_pm_ops, |
616b7341 | 775 | .of_match_table = omap_rtc_of_match, |
db68b189 | 776 | }, |
2153f949 | 777 | .id_table = omap_rtc_id_table, |
db68b189 DB |
778 | }; |
779 | ||
5d9094b6 | 780 | module_platform_driver(omap_rtc_driver); |
db68b189 | 781 | |
a430ca22 | 782 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 DB |
783 | MODULE_AUTHOR("George G. Davis (and others)"); |
784 | MODULE_LICENSE("GPL"); |