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db68b189 DB |
1 | /* |
2 | * TI OMAP1 Real Time Clock interface for Linux | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/bcd.h> | |
22 | #include <linux/platform_device.h> | |
9e0344dc AM |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
fc9bd902 | 25 | #include <linux/pm_runtime.h> |
4b30c9fc | 26 | #include <linux/io.h> |
db68b189 DB |
27 | |
28 | /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock | |
29 | * with century-range alarm matching, driven by the 32kHz clock. | |
30 | * | |
31 | * The main user-visible ways it differs from PC RTCs are by omitting | |
32 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
33 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
34 | * | |
35 | * Board-specific wiring options include using split power mode with | |
36 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
37 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
38 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
39 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
40 | */ |
41 | ||
cab1458c AM |
42 | #define DRIVER_NAME "omap_rtc" |
43 | ||
db68b189 DB |
44 | /* RTC registers */ |
45 | #define OMAP_RTC_SECONDS_REG 0x00 | |
46 | #define OMAP_RTC_MINUTES_REG 0x04 | |
47 | #define OMAP_RTC_HOURS_REG 0x08 | |
48 | #define OMAP_RTC_DAYS_REG 0x0C | |
49 | #define OMAP_RTC_MONTHS_REG 0x10 | |
50 | #define OMAP_RTC_YEARS_REG 0x14 | |
51 | #define OMAP_RTC_WEEKS_REG 0x18 | |
52 | ||
53 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
54 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
55 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
56 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
57 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
58 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
59 | ||
60 | #define OMAP_RTC_CTRL_REG 0x40 | |
61 | #define OMAP_RTC_STATUS_REG 0x44 | |
62 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
63 | ||
64 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
65 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
66 | #define OMAP_RTC_OSC_REG 0x54 | |
67 | ||
cab1458c AM |
68 | #define OMAP_RTC_KICK0_REG 0x6c |
69 | #define OMAP_RTC_KICK1_REG 0x70 | |
70 | ||
8af750e3 HG |
71 | #define OMAP_RTC_IRQWAKEEN 0x7c |
72 | ||
db68b189 | 73 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
74 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
75 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
76 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
77 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
78 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
79 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
80 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
81 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
82 | |
83 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a SN |
84 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
85 | #define OMAP_RTC_STATUS_ALARM BIT(6) | |
86 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
87 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
88 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
89 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
90 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
91 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
92 | |
93 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
92adb96a SN |
94 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
95 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 96 | |
cd914bba SN |
97 | /* OMAP_RTC_OSC_REG bit fields: */ |
98 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
99 | ||
8af750e3 | 100 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 101 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 102 | |
cab1458c AM |
103 | /* OMAP_RTC_KICKER values */ |
104 | #define KICK0_VALUE 0x83e70b13 | |
105 | #define KICK1_VALUE 0x95a4f1e0 | |
106 | ||
92adb96a | 107 | #define OMAP_RTC_HAS_KICKER BIT(0) |
cab1458c | 108 | |
8af750e3 HG |
109 | /* |
110 | * Few RTC IP revisions has special WAKE-EN Register to enable Wakeup | |
111 | * generation for event Alarm. | |
112 | */ | |
92adb96a | 113 | #define OMAP_RTC_HAS_IRQWAKEEN BIT(1) |
8af750e3 | 114 | |
cd914bba SN |
115 | /* |
116 | * Some RTC IP revisions (like those in AM335x and DRA7x) need | |
117 | * the 32KHz clock to be explicitly enabled. | |
118 | */ | |
119 | #define OMAP_RTC_HAS_32KCLK_EN BIT(2) | |
120 | ||
55ba953a JH |
121 | struct omap_rtc { |
122 | struct rtc_device *rtc; | |
123 | void __iomem *base; | |
124 | int irq_alarm; | |
125 | int irq_timer; | |
126 | u8 interrupts_reg; | |
127 | unsigned long flags; | |
128 | }; | |
db68b189 | 129 | |
55ba953a JH |
130 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
131 | { | |
132 | return readb(rtc->base + reg); | |
133 | } | |
cab1458c | 134 | |
55ba953a JH |
135 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
136 | { | |
137 | writeb(val, rtc->base + reg); | |
138 | } | |
db68b189 | 139 | |
55ba953a JH |
140 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
141 | { | |
142 | writel(val, rtc->base + reg); | |
143 | } | |
db68b189 | 144 | |
db68b189 DB |
145 | /* we rely on the rtc framework to handle locking (rtc->ops_lock), |
146 | * so the only other requirement is that register accesses which | |
147 | * require BUSY to be clear are made with IRQs locally disabled | |
148 | */ | |
55ba953a | 149 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 DB |
150 | { |
151 | int count = 0; | |
152 | u8 status; | |
153 | ||
154 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
155 | for (count = 0; count < 50; count++) { | |
55ba953a | 156 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
157 | if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0) |
158 | break; | |
159 | udelay(1); | |
160 | } | |
161 | /* now we have ~15 usec to read/write various registers */ | |
162 | } | |
163 | ||
55ba953a | 164 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 165 | { |
55ba953a | 166 | struct omap_rtc *rtc = dev_id; |
db68b189 DB |
167 | unsigned long events = 0; |
168 | u8 irq_data; | |
169 | ||
55ba953a | 170 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
171 | |
172 | /* alarm irq? */ | |
173 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
55ba953a | 174 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
db68b189 DB |
175 | events |= RTC_IRQF | RTC_AF; |
176 | } | |
177 | ||
178 | /* 1/sec periodic/update irq? */ | |
179 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
180 | events |= RTC_IRQF | RTC_UF; | |
181 | ||
55ba953a | 182 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
183 | |
184 | return IRQ_HANDLED; | |
185 | } | |
186 | ||
16380c15 JS |
187 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
188 | { | |
55ba953a | 189 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 190 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
191 | |
192 | local_irq_disable(); | |
55ba953a JH |
193 | rtc_wait_not_busy(rtc); |
194 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
195 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
196 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); | |
ab7f580b LV |
197 | |
198 | if (enabled) { | |
16380c15 | 199 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
200 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
201 | } else { | |
16380c15 | 202 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
203 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
204 | } | |
55ba953a JH |
205 | rtc_wait_not_busy(rtc); |
206 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); | |
207 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
208 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); | |
16380c15 JS |
209 | local_irq_enable(); |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
db68b189 DB |
214 | /* this hardware doesn't support "don't care" alarm fields */ |
215 | static int tm2bcd(struct rtc_time *tm) | |
216 | { | |
217 | if (rtc_valid_tm(tm) != 0) | |
218 | return -EINVAL; | |
219 | ||
fe20ba70 AB |
220 | tm->tm_sec = bin2bcd(tm->tm_sec); |
221 | tm->tm_min = bin2bcd(tm->tm_min); | |
222 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
223 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 224 | |
fe20ba70 | 225 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
226 | |
227 | /* epoch == 1900 */ | |
228 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
229 | return -EINVAL; | |
fe20ba70 | 230 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
231 | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static void bcd2tm(struct rtc_time *tm) | |
236 | { | |
fe20ba70 AB |
237 | tm->tm_sec = bcd2bin(tm->tm_sec); |
238 | tm->tm_min = bcd2bin(tm->tm_min); | |
239 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
240 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
241 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 242 | /* epoch == 1900 */ |
fe20ba70 | 243 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
244 | } |
245 | ||
246 | ||
247 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
248 | { | |
55ba953a JH |
249 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
250 | ||
db68b189 DB |
251 | /* we don't report wday/yday/isdst ... */ |
252 | local_irq_disable(); | |
55ba953a | 253 | rtc_wait_not_busy(rtc); |
db68b189 | 254 | |
55ba953a JH |
255 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
256 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
257 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
258 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
259 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
260 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
db68b189 DB |
261 | |
262 | local_irq_enable(); | |
263 | ||
264 | bcd2tm(tm); | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
269 | { | |
55ba953a JH |
270 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
271 | ||
db68b189 DB |
272 | if (tm2bcd(tm) < 0) |
273 | return -EINVAL; | |
274 | local_irq_disable(); | |
55ba953a | 275 | rtc_wait_not_busy(rtc); |
db68b189 | 276 | |
55ba953a JH |
277 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
278 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
279 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
280 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
281 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
282 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
db68b189 DB |
283 | |
284 | local_irq_enable(); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
289 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
290 | { | |
55ba953a JH |
291 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
292 | ||
db68b189 | 293 | local_irq_disable(); |
55ba953a | 294 | rtc_wait_not_busy(rtc); |
db68b189 | 295 | |
55ba953a JH |
296 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
297 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
298 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
299 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
300 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
301 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
302 | |
303 | local_irq_enable(); | |
304 | ||
305 | bcd2tm(&alm->time); | |
55ba953a | 306 | alm->enabled = !!(rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG) |
db68b189 | 307 | & OMAP_RTC_INTERRUPTS_IT_ALARM); |
db68b189 DB |
308 | |
309 | return 0; | |
310 | } | |
311 | ||
312 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
313 | { | |
55ba953a | 314 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 315 | u8 reg, irqwake_reg = 0; |
db68b189 | 316 | |
db68b189 DB |
317 | if (tm2bcd(&alm->time) < 0) |
318 | return -EINVAL; | |
319 | ||
320 | local_irq_disable(); | |
55ba953a | 321 | rtc_wait_not_busy(rtc); |
db68b189 | 322 | |
55ba953a JH |
323 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
324 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
325 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
326 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
327 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
328 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 329 | |
55ba953a JH |
330 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
331 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
332 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); | |
ab7f580b LV |
333 | |
334 | if (alm->enabled) { | |
db68b189 | 335 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
336 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
337 | } else { | |
db68b189 | 338 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
339 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
340 | } | |
55ba953a JH |
341 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
342 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
343 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); | |
db68b189 DB |
344 | |
345 | local_irq_enable(); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static struct rtc_class_ops omap_rtc_ops = { | |
db68b189 DB |
351 | .read_time = omap_rtc_read_time, |
352 | .set_time = omap_rtc_set_time, | |
353 | .read_alarm = omap_rtc_read_alarm, | |
354 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 355 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
356 | }; |
357 | ||
8af750e3 HG |
358 | #define OMAP_RTC_DATA_AM3352_IDX 1 |
359 | #define OMAP_RTC_DATA_DA830_IDX 2 | |
9e0344dc | 360 | |
d17a82e2 | 361 | static const struct platform_device_id omap_rtc_devtype[] = { |
cab1458c AM |
362 | { |
363 | .name = DRIVER_NAME, | |
8af750e3 HG |
364 | }, |
365 | [OMAP_RTC_DATA_AM3352_IDX] = { | |
366 | .name = "am3352-rtc", | |
cd914bba SN |
367 | .driver_data = OMAP_RTC_HAS_KICKER | OMAP_RTC_HAS_IRQWAKEEN | |
368 | OMAP_RTC_HAS_32KCLK_EN, | |
8af750e3 HG |
369 | }, |
370 | [OMAP_RTC_DATA_DA830_IDX] = { | |
cab1458c AM |
371 | .name = "da830-rtc", |
372 | .driver_data = OMAP_RTC_HAS_KICKER, | |
373 | }, | |
374 | {}, | |
375 | }; | |
376 | MODULE_DEVICE_TABLE(platform, omap_rtc_devtype); | |
377 | ||
9e0344dc AM |
378 | static const struct of_device_id omap_rtc_of_match[] = { |
379 | { .compatible = "ti,da830-rtc", | |
380 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX], | |
381 | }, | |
8af750e3 HG |
382 | { .compatible = "ti,am3352-rtc", |
383 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_AM3352_IDX], | |
384 | }, | |
9e0344dc AM |
385 | {}, |
386 | }; | |
387 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
388 | ||
71fc8224 | 389 | static int __init omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 390 | { |
55ba953a | 391 | struct omap_rtc *rtc; |
3765e8f1 | 392 | struct resource *res; |
db68b189 | 393 | u8 reg, new_ctrl; |
cab1458c | 394 | const struct platform_device_id *id_entry; |
9e0344dc | 395 | const struct of_device_id *of_id; |
437b37a6 | 396 | int ret; |
9e0344dc | 397 | |
55ba953a JH |
398 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
399 | if (!rtc) | |
400 | return -ENOMEM; | |
401 | ||
9e0344dc AM |
402 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
403 | if (of_id) | |
404 | pdev->id_entry = of_id->data; | |
db68b189 | 405 | |
337b600f SN |
406 | id_entry = platform_get_device_id(pdev); |
407 | if (!id_entry) { | |
408 | dev_err(&pdev->dev, "no matching device entry\n"); | |
409 | return -ENODEV; | |
410 | } | |
411 | ||
55ba953a JH |
412 | rtc->flags = id_entry->driver_data; |
413 | ||
414 | rtc->irq_timer = platform_get_irq(pdev, 0); | |
415 | if (rtc->irq_timer <= 0) | |
db68b189 | 416 | return -ENOENT; |
db68b189 | 417 | |
55ba953a JH |
418 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
419 | if (rtc->irq_alarm <= 0) | |
db68b189 | 420 | return -ENOENT; |
db68b189 | 421 | |
db68b189 | 422 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
423 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
424 | if (IS_ERR(rtc->base)) | |
425 | return PTR_ERR(rtc->base); | |
426 | ||
427 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 428 | |
fc9bd902 VH |
429 | /* Enable the clock/module so that we can access the registers */ |
430 | pm_runtime_enable(&pdev->dev); | |
431 | pm_runtime_get_sync(&pdev->dev); | |
432 | ||
55ba953a JH |
433 | if (rtc->flags & OMAP_RTC_HAS_KICKER) { |
434 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); | |
435 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
cab1458c AM |
436 | } |
437 | ||
1ed8b5d2 JH |
438 | /* |
439 | * disable interrupts | |
440 | * | |
441 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 442 | */ |
55ba953a | 443 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 444 | |
cd914bba | 445 | /* enable RTC functional clock */ |
55ba953a JH |
446 | if (rtc->flags & OMAP_RTC_HAS_32KCLK_EN) { |
447 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); | |
448 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
449 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 450 | } |
cd914bba | 451 | |
db68b189 | 452 | /* clear old status */ |
55ba953a | 453 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 | 454 | if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) { |
397b630a | 455 | dev_info(&pdev->dev, "RTC power up reset detected\n"); |
55ba953a | 456 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_POWER_UP); |
db68b189 DB |
457 | } |
458 | if (reg & (u8) OMAP_RTC_STATUS_ALARM) | |
55ba953a | 459 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
db68b189 | 460 | |
db68b189 | 461 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 462 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
db68b189 | 463 | if (reg & (u8) OMAP_RTC_CTRL_STOP) |
397b630a | 464 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
465 | |
466 | /* force to 24 hour mode */ | |
12b3e038 | 467 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT|OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
468 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
469 | ||
470 | /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
471 | * | |
fa5b0782 SN |
472 | * - Device wake-up capability setting should come through chip |
473 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
474 | * flag in the platform device if the board is wired right for | |
475 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
476 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
477 | * |
478 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
479 | * rather than nPWRON_RESET, should forcibly enable split | |
480 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
481 | * is write-only, and always reads as zero...) | |
482 | */ | |
db68b189 DB |
483 | |
484 | if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT) | |
397b630a | 485 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
486 | |
487 | if (reg != new_ctrl) | |
55ba953a | 488 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 489 | |
4390ce00 JH |
490 | device_init_wakeup(&pdev->dev, true); |
491 | ||
55ba953a | 492 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
4390ce00 | 493 | &omap_rtc_ops, THIS_MODULE); |
55ba953a JH |
494 | if (IS_ERR(rtc->rtc)) { |
495 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
496 | goto err; |
497 | } | |
4390ce00 JH |
498 | |
499 | /* handle periodic and alarm irqs */ | |
55ba953a JH |
500 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
501 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
502 | if (ret) |
503 | goto err; | |
504 | ||
55ba953a JH |
505 | if (rtc->irq_timer != rtc->irq_alarm) { |
506 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
507 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
508 | if (ret) |
509 | goto err; | |
510 | } | |
511 | ||
db68b189 DB |
512 | return 0; |
513 | ||
437b37a6 | 514 | err: |
7ecd9a3f | 515 | device_init_wakeup(&pdev->dev, false); |
55ba953a JH |
516 | if (rtc->flags & OMAP_RTC_HAS_KICKER) |
517 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
fc9bd902 VH |
518 | pm_runtime_put_sync(&pdev->dev); |
519 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
520 | |
521 | return ret; | |
db68b189 DB |
522 | } |
523 | ||
71fc8224 | 524 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 525 | { |
55ba953a | 526 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
db68b189 DB |
527 | |
528 | device_init_wakeup(&pdev->dev, 0); | |
529 | ||
530 | /* leave rtc running, but disable irqs */ | |
55ba953a | 531 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 532 | |
55ba953a JH |
533 | if (rtc->flags & OMAP_RTC_HAS_KICKER) |
534 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
fc9bd902 VH |
535 | |
536 | /* Disable the clock/module */ | |
537 | pm_runtime_put_sync(&pdev->dev); | |
538 | pm_runtime_disable(&pdev->dev); | |
539 | ||
db68b189 DB |
540 | return 0; |
541 | } | |
542 | ||
04ebc359 | 543 | #ifdef CONFIG_PM_SLEEP |
04ebc359 | 544 | static int omap_rtc_suspend(struct device *dev) |
db68b189 | 545 | { |
55ba953a JH |
546 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
547 | ||
548 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 DB |
549 | |
550 | /* FIXME the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
551 | * source on some platforms, and in fact this enable() call is just |
552 | * saving a flag that's never used... | |
db68b189 | 553 | */ |
ab7f580b | 554 | if (device_may_wakeup(dev)) |
55ba953a | 555 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 556 | else |
55ba953a | 557 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 558 | |
fc9bd902 | 559 | /* Disable the clock/module */ |
04ebc359 | 560 | pm_runtime_put_sync(dev); |
fc9bd902 | 561 | |
db68b189 DB |
562 | return 0; |
563 | } | |
564 | ||
04ebc359 | 565 | static int omap_rtc_resume(struct device *dev) |
db68b189 | 566 | { |
55ba953a JH |
567 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
568 | ||
fc9bd902 | 569 | /* Enable the clock/module so that we can access the registers */ |
04ebc359 | 570 | pm_runtime_get_sync(dev); |
fc9bd902 | 571 | |
ab7f580b | 572 | if (device_may_wakeup(dev)) |
55ba953a | 573 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 574 | else |
55ba953a | 575 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
ab7f580b | 576 | |
db68b189 DB |
577 | return 0; |
578 | } | |
db68b189 DB |
579 | #endif |
580 | ||
04ebc359 JH |
581 | static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); |
582 | ||
db68b189 DB |
583 | static void omap_rtc_shutdown(struct platform_device *pdev) |
584 | { | |
55ba953a JH |
585 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
586 | ||
587 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); | |
db68b189 DB |
588 | } |
589 | ||
ad28a07b | 590 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 | 591 | static struct platform_driver omap_rtc_driver = { |
71fc8224 | 592 | .remove = __exit_p(omap_rtc_remove), |
db68b189 DB |
593 | .shutdown = omap_rtc_shutdown, |
594 | .driver = { | |
cab1458c | 595 | .name = DRIVER_NAME, |
db68b189 | 596 | .owner = THIS_MODULE, |
04ebc359 | 597 | .pm = &omap_rtc_pm_ops, |
616b7341 | 598 | .of_match_table = omap_rtc_of_match, |
db68b189 | 599 | }, |
cab1458c | 600 | .id_table = omap_rtc_devtype, |
db68b189 DB |
601 | }; |
602 | ||
09c5a36b | 603 | module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe); |
db68b189 DB |
604 | |
605 | MODULE_AUTHOR("George G. Davis (and others)"); | |
606 | MODULE_LICENSE("GPL"); |