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db68b189 DB |
1 | /* |
2 | * TI OMAP1 Real Time Clock interface for Linux | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/bcd.h> | |
22 | #include <linux/platform_device.h> | |
9e0344dc AM |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
fc9bd902 | 25 | #include <linux/pm_runtime.h> |
4b30c9fc | 26 | #include <linux/io.h> |
db68b189 DB |
27 | |
28 | /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock | |
29 | * with century-range alarm matching, driven by the 32kHz clock. | |
30 | * | |
31 | * The main user-visible ways it differs from PC RTCs are by omitting | |
32 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
33 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
34 | * | |
35 | * Board-specific wiring options include using split power mode with | |
36 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
37 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
38 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
39 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
40 | */ |
41 | ||
db68b189 DB |
42 | /* RTC registers */ |
43 | #define OMAP_RTC_SECONDS_REG 0x00 | |
44 | #define OMAP_RTC_MINUTES_REG 0x04 | |
45 | #define OMAP_RTC_HOURS_REG 0x08 | |
46 | #define OMAP_RTC_DAYS_REG 0x0C | |
47 | #define OMAP_RTC_MONTHS_REG 0x10 | |
48 | #define OMAP_RTC_YEARS_REG 0x14 | |
49 | #define OMAP_RTC_WEEKS_REG 0x18 | |
50 | ||
51 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
52 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
53 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
54 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
55 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
56 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
57 | ||
58 | #define OMAP_RTC_CTRL_REG 0x40 | |
59 | #define OMAP_RTC_STATUS_REG 0x44 | |
60 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
61 | ||
62 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
63 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
64 | #define OMAP_RTC_OSC_REG 0x54 | |
65 | ||
cab1458c AM |
66 | #define OMAP_RTC_KICK0_REG 0x6c |
67 | #define OMAP_RTC_KICK1_REG 0x70 | |
68 | ||
8af750e3 HG |
69 | #define OMAP_RTC_IRQWAKEEN 0x7c |
70 | ||
db68b189 | 71 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
72 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
73 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
74 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
75 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
76 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
77 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
78 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
79 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
80 | |
81 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a SN |
82 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
83 | #define OMAP_RTC_STATUS_ALARM BIT(6) | |
84 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
85 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
86 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
87 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
88 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
89 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
90 | |
91 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
92adb96a SN |
92 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
93 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 94 | |
cd914bba SN |
95 | /* OMAP_RTC_OSC_REG bit fields: */ |
96 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
97 | ||
8af750e3 | 98 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 99 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 100 | |
cab1458c AM |
101 | /* OMAP_RTC_KICKER values */ |
102 | #define KICK0_VALUE 0x83e70b13 | |
103 | #define KICK1_VALUE 0x95a4f1e0 | |
104 | ||
92adb96a | 105 | #define OMAP_RTC_HAS_KICKER BIT(0) |
cab1458c | 106 | |
8af750e3 HG |
107 | /* |
108 | * Few RTC IP revisions has special WAKE-EN Register to enable Wakeup | |
109 | * generation for event Alarm. | |
110 | */ | |
92adb96a | 111 | #define OMAP_RTC_HAS_IRQWAKEEN BIT(1) |
8af750e3 | 112 | |
cd914bba SN |
113 | /* |
114 | * Some RTC IP revisions (like those in AM335x and DRA7x) need | |
115 | * the 32KHz clock to be explicitly enabled. | |
116 | */ | |
117 | #define OMAP_RTC_HAS_32KCLK_EN BIT(2) | |
118 | ||
55ba953a JH |
119 | struct omap_rtc { |
120 | struct rtc_device *rtc; | |
121 | void __iomem *base; | |
122 | int irq_alarm; | |
123 | int irq_timer; | |
124 | u8 interrupts_reg; | |
125 | unsigned long flags; | |
126 | }; | |
db68b189 | 127 | |
55ba953a JH |
128 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
129 | { | |
130 | return readb(rtc->base + reg); | |
131 | } | |
cab1458c | 132 | |
55ba953a JH |
133 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
134 | { | |
135 | writeb(val, rtc->base + reg); | |
136 | } | |
db68b189 | 137 | |
55ba953a JH |
138 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
139 | { | |
140 | writel(val, rtc->base + reg); | |
141 | } | |
db68b189 | 142 | |
db68b189 DB |
143 | /* we rely on the rtc framework to handle locking (rtc->ops_lock), |
144 | * so the only other requirement is that register accesses which | |
145 | * require BUSY to be clear are made with IRQs locally disabled | |
146 | */ | |
55ba953a | 147 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 DB |
148 | { |
149 | int count = 0; | |
150 | u8 status; | |
151 | ||
152 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
153 | for (count = 0; count < 50; count++) { | |
55ba953a | 154 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
155 | if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0) |
156 | break; | |
157 | udelay(1); | |
158 | } | |
159 | /* now we have ~15 usec to read/write various registers */ | |
160 | } | |
161 | ||
55ba953a | 162 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 163 | { |
55ba953a | 164 | struct omap_rtc *rtc = dev_id; |
db68b189 DB |
165 | unsigned long events = 0; |
166 | u8 irq_data; | |
167 | ||
55ba953a | 168 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
169 | |
170 | /* alarm irq? */ | |
171 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
55ba953a | 172 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
db68b189 DB |
173 | events |= RTC_IRQF | RTC_AF; |
174 | } | |
175 | ||
176 | /* 1/sec periodic/update irq? */ | |
177 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
178 | events |= RTC_IRQF | RTC_UF; | |
179 | ||
55ba953a | 180 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
181 | |
182 | return IRQ_HANDLED; | |
183 | } | |
184 | ||
16380c15 JS |
185 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
186 | { | |
55ba953a | 187 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 188 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
189 | |
190 | local_irq_disable(); | |
55ba953a JH |
191 | rtc_wait_not_busy(rtc); |
192 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
193 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
194 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); | |
ab7f580b LV |
195 | |
196 | if (enabled) { | |
16380c15 | 197 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
198 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
199 | } else { | |
16380c15 | 200 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
201 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
202 | } | |
55ba953a JH |
203 | rtc_wait_not_busy(rtc); |
204 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); | |
205 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
206 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); | |
16380c15 JS |
207 | local_irq_enable(); |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
db68b189 DB |
212 | /* this hardware doesn't support "don't care" alarm fields */ |
213 | static int tm2bcd(struct rtc_time *tm) | |
214 | { | |
215 | if (rtc_valid_tm(tm) != 0) | |
216 | return -EINVAL; | |
217 | ||
fe20ba70 AB |
218 | tm->tm_sec = bin2bcd(tm->tm_sec); |
219 | tm->tm_min = bin2bcd(tm->tm_min); | |
220 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
221 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 222 | |
fe20ba70 | 223 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
224 | |
225 | /* epoch == 1900 */ | |
226 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
227 | return -EINVAL; | |
fe20ba70 | 228 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static void bcd2tm(struct rtc_time *tm) | |
234 | { | |
fe20ba70 AB |
235 | tm->tm_sec = bcd2bin(tm->tm_sec); |
236 | tm->tm_min = bcd2bin(tm->tm_min); | |
237 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
238 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
239 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 240 | /* epoch == 1900 */ |
fe20ba70 | 241 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
242 | } |
243 | ||
244 | ||
245 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
246 | { | |
55ba953a JH |
247 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
248 | ||
db68b189 DB |
249 | /* we don't report wday/yday/isdst ... */ |
250 | local_irq_disable(); | |
55ba953a | 251 | rtc_wait_not_busy(rtc); |
db68b189 | 252 | |
55ba953a JH |
253 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
254 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
255 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
256 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
257 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
258 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
db68b189 DB |
259 | |
260 | local_irq_enable(); | |
261 | ||
262 | bcd2tm(tm); | |
263 | return 0; | |
264 | } | |
265 | ||
266 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
267 | { | |
55ba953a JH |
268 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
269 | ||
db68b189 DB |
270 | if (tm2bcd(tm) < 0) |
271 | return -EINVAL; | |
272 | local_irq_disable(); | |
55ba953a | 273 | rtc_wait_not_busy(rtc); |
db68b189 | 274 | |
55ba953a JH |
275 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
276 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
277 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
278 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
279 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
280 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
db68b189 DB |
281 | |
282 | local_irq_enable(); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
288 | { | |
55ba953a JH |
289 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
290 | ||
db68b189 | 291 | local_irq_disable(); |
55ba953a | 292 | rtc_wait_not_busy(rtc); |
db68b189 | 293 | |
55ba953a JH |
294 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
295 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
296 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
297 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
298 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
299 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
300 | |
301 | local_irq_enable(); | |
302 | ||
303 | bcd2tm(&alm->time); | |
55ba953a | 304 | alm->enabled = !!(rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG) |
db68b189 | 305 | & OMAP_RTC_INTERRUPTS_IT_ALARM); |
db68b189 DB |
306 | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
311 | { | |
55ba953a | 312 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 313 | u8 reg, irqwake_reg = 0; |
db68b189 | 314 | |
db68b189 DB |
315 | if (tm2bcd(&alm->time) < 0) |
316 | return -EINVAL; | |
317 | ||
318 | local_irq_disable(); | |
55ba953a | 319 | rtc_wait_not_busy(rtc); |
db68b189 | 320 | |
55ba953a JH |
321 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
322 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
323 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
324 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
325 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
326 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 327 | |
55ba953a JH |
328 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
329 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
330 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); | |
ab7f580b LV |
331 | |
332 | if (alm->enabled) { | |
db68b189 | 333 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
334 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
335 | } else { | |
db68b189 | 336 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
337 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
338 | } | |
55ba953a JH |
339 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
340 | if (rtc->flags & OMAP_RTC_HAS_IRQWAKEEN) | |
341 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); | |
db68b189 DB |
342 | |
343 | local_irq_enable(); | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
348 | static struct rtc_class_ops omap_rtc_ops = { | |
db68b189 DB |
349 | .read_time = omap_rtc_read_time, |
350 | .set_time = omap_rtc_set_time, | |
351 | .read_alarm = omap_rtc_read_alarm, | |
352 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 353 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
354 | }; |
355 | ||
8af750e3 HG |
356 | #define OMAP_RTC_DATA_AM3352_IDX 1 |
357 | #define OMAP_RTC_DATA_DA830_IDX 2 | |
9e0344dc | 358 | |
d17a82e2 | 359 | static const struct platform_device_id omap_rtc_devtype[] = { |
cab1458c | 360 | { |
a430ca22 | 361 | .name = "omap_rtc", |
8af750e3 HG |
362 | }, |
363 | [OMAP_RTC_DATA_AM3352_IDX] = { | |
364 | .name = "am3352-rtc", | |
cd914bba SN |
365 | .driver_data = OMAP_RTC_HAS_KICKER | OMAP_RTC_HAS_IRQWAKEEN | |
366 | OMAP_RTC_HAS_32KCLK_EN, | |
8af750e3 HG |
367 | }, |
368 | [OMAP_RTC_DATA_DA830_IDX] = { | |
cab1458c AM |
369 | .name = "da830-rtc", |
370 | .driver_data = OMAP_RTC_HAS_KICKER, | |
371 | }, | |
372 | {}, | |
373 | }; | |
374 | MODULE_DEVICE_TABLE(platform, omap_rtc_devtype); | |
375 | ||
9e0344dc AM |
376 | static const struct of_device_id omap_rtc_of_match[] = { |
377 | { .compatible = "ti,da830-rtc", | |
378 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX], | |
379 | }, | |
8af750e3 HG |
380 | { .compatible = "ti,am3352-rtc", |
381 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_AM3352_IDX], | |
382 | }, | |
9e0344dc AM |
383 | {}, |
384 | }; | |
385 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
386 | ||
71fc8224 | 387 | static int __init omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 388 | { |
55ba953a | 389 | struct omap_rtc *rtc; |
3765e8f1 | 390 | struct resource *res; |
db68b189 | 391 | u8 reg, new_ctrl; |
cab1458c | 392 | const struct platform_device_id *id_entry; |
9e0344dc | 393 | const struct of_device_id *of_id; |
437b37a6 | 394 | int ret; |
9e0344dc | 395 | |
55ba953a JH |
396 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
397 | if (!rtc) | |
398 | return -ENOMEM; | |
399 | ||
9e0344dc AM |
400 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
401 | if (of_id) | |
402 | pdev->id_entry = of_id->data; | |
db68b189 | 403 | |
337b600f SN |
404 | id_entry = platform_get_device_id(pdev); |
405 | if (!id_entry) { | |
406 | dev_err(&pdev->dev, "no matching device entry\n"); | |
407 | return -ENODEV; | |
408 | } | |
409 | ||
55ba953a JH |
410 | rtc->flags = id_entry->driver_data; |
411 | ||
412 | rtc->irq_timer = platform_get_irq(pdev, 0); | |
413 | if (rtc->irq_timer <= 0) | |
db68b189 | 414 | return -ENOENT; |
db68b189 | 415 | |
55ba953a JH |
416 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
417 | if (rtc->irq_alarm <= 0) | |
db68b189 | 418 | return -ENOENT; |
db68b189 | 419 | |
db68b189 | 420 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
421 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
422 | if (IS_ERR(rtc->base)) | |
423 | return PTR_ERR(rtc->base); | |
424 | ||
425 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 426 | |
fc9bd902 VH |
427 | /* Enable the clock/module so that we can access the registers */ |
428 | pm_runtime_enable(&pdev->dev); | |
429 | pm_runtime_get_sync(&pdev->dev); | |
430 | ||
55ba953a JH |
431 | if (rtc->flags & OMAP_RTC_HAS_KICKER) { |
432 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); | |
433 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
cab1458c AM |
434 | } |
435 | ||
1ed8b5d2 JH |
436 | /* |
437 | * disable interrupts | |
438 | * | |
439 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 440 | */ |
55ba953a | 441 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 442 | |
cd914bba | 443 | /* enable RTC functional clock */ |
55ba953a JH |
444 | if (rtc->flags & OMAP_RTC_HAS_32KCLK_EN) { |
445 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); | |
446 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
447 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 448 | } |
cd914bba | 449 | |
db68b189 | 450 | /* clear old status */ |
55ba953a | 451 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 | 452 | if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) { |
397b630a | 453 | dev_info(&pdev->dev, "RTC power up reset detected\n"); |
55ba953a | 454 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_POWER_UP); |
db68b189 DB |
455 | } |
456 | if (reg & (u8) OMAP_RTC_STATUS_ALARM) | |
55ba953a | 457 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
db68b189 | 458 | |
db68b189 | 459 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 460 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
db68b189 | 461 | if (reg & (u8) OMAP_RTC_CTRL_STOP) |
397b630a | 462 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
463 | |
464 | /* force to 24 hour mode */ | |
12b3e038 | 465 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT|OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
466 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
467 | ||
468 | /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
469 | * | |
fa5b0782 SN |
470 | * - Device wake-up capability setting should come through chip |
471 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
472 | * flag in the platform device if the board is wired right for | |
473 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
474 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
475 | * |
476 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
477 | * rather than nPWRON_RESET, should forcibly enable split | |
478 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
479 | * is write-only, and always reads as zero...) | |
480 | */ | |
db68b189 DB |
481 | |
482 | if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT) | |
397b630a | 483 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
484 | |
485 | if (reg != new_ctrl) | |
55ba953a | 486 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 487 | |
4390ce00 JH |
488 | device_init_wakeup(&pdev->dev, true); |
489 | ||
55ba953a | 490 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
4390ce00 | 491 | &omap_rtc_ops, THIS_MODULE); |
55ba953a JH |
492 | if (IS_ERR(rtc->rtc)) { |
493 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
494 | goto err; |
495 | } | |
4390ce00 JH |
496 | |
497 | /* handle periodic and alarm irqs */ | |
55ba953a JH |
498 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
499 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
500 | if (ret) |
501 | goto err; | |
502 | ||
55ba953a JH |
503 | if (rtc->irq_timer != rtc->irq_alarm) { |
504 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
505 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
506 | if (ret) |
507 | goto err; | |
508 | } | |
509 | ||
db68b189 DB |
510 | return 0; |
511 | ||
437b37a6 | 512 | err: |
7ecd9a3f | 513 | device_init_wakeup(&pdev->dev, false); |
55ba953a JH |
514 | if (rtc->flags & OMAP_RTC_HAS_KICKER) |
515 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
fc9bd902 VH |
516 | pm_runtime_put_sync(&pdev->dev); |
517 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
518 | |
519 | return ret; | |
db68b189 DB |
520 | } |
521 | ||
71fc8224 | 522 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 523 | { |
55ba953a | 524 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
db68b189 DB |
525 | |
526 | device_init_wakeup(&pdev->dev, 0); | |
527 | ||
528 | /* leave rtc running, but disable irqs */ | |
55ba953a | 529 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 530 | |
55ba953a JH |
531 | if (rtc->flags & OMAP_RTC_HAS_KICKER) |
532 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
fc9bd902 VH |
533 | |
534 | /* Disable the clock/module */ | |
535 | pm_runtime_put_sync(&pdev->dev); | |
536 | pm_runtime_disable(&pdev->dev); | |
537 | ||
db68b189 DB |
538 | return 0; |
539 | } | |
540 | ||
04ebc359 | 541 | #ifdef CONFIG_PM_SLEEP |
04ebc359 | 542 | static int omap_rtc_suspend(struct device *dev) |
db68b189 | 543 | { |
55ba953a JH |
544 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
545 | ||
546 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 DB |
547 | |
548 | /* FIXME the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
549 | * source on some platforms, and in fact this enable() call is just |
550 | * saving a flag that's never used... | |
db68b189 | 551 | */ |
ab7f580b | 552 | if (device_may_wakeup(dev)) |
55ba953a | 553 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 554 | else |
55ba953a | 555 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 556 | |
fc9bd902 | 557 | /* Disable the clock/module */ |
04ebc359 | 558 | pm_runtime_put_sync(dev); |
fc9bd902 | 559 | |
db68b189 DB |
560 | return 0; |
561 | } | |
562 | ||
04ebc359 | 563 | static int omap_rtc_resume(struct device *dev) |
db68b189 | 564 | { |
55ba953a JH |
565 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
566 | ||
fc9bd902 | 567 | /* Enable the clock/module so that we can access the registers */ |
04ebc359 | 568 | pm_runtime_get_sync(dev); |
fc9bd902 | 569 | |
ab7f580b | 570 | if (device_may_wakeup(dev)) |
55ba953a | 571 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 572 | else |
55ba953a | 573 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
ab7f580b | 574 | |
db68b189 DB |
575 | return 0; |
576 | } | |
db68b189 DB |
577 | #endif |
578 | ||
04ebc359 JH |
579 | static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); |
580 | ||
db68b189 DB |
581 | static void omap_rtc_shutdown(struct platform_device *pdev) |
582 | { | |
55ba953a JH |
583 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
584 | ||
585 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); | |
db68b189 DB |
586 | } |
587 | ||
db68b189 | 588 | static struct platform_driver omap_rtc_driver = { |
71fc8224 | 589 | .remove = __exit_p(omap_rtc_remove), |
db68b189 DB |
590 | .shutdown = omap_rtc_shutdown, |
591 | .driver = { | |
a430ca22 | 592 | .name = "omap_rtc", |
db68b189 | 593 | .owner = THIS_MODULE, |
04ebc359 | 594 | .pm = &omap_rtc_pm_ops, |
616b7341 | 595 | .of_match_table = omap_rtc_of_match, |
db68b189 | 596 | }, |
cab1458c | 597 | .id_table = omap_rtc_devtype, |
db68b189 DB |
598 | }; |
599 | ||
09c5a36b | 600 | module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe); |
db68b189 | 601 | |
a430ca22 | 602 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 DB |
603 | MODULE_AUTHOR("George G. Davis (and others)"); |
604 | MODULE_LICENSE("GPL"); |