[mirror_ubuntu-hirsute-kernel.git] / drivers / rtc / rtc-pcf85363.c

/*
 * drivers/rtc/rtc-pcf85363.c
 *
 * Driver for NXP PCF85363 real-time clock.
 *
 * Copyright (C) 2017 Eric Nelson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Based loosely on rtc-8583 by Russell King, Wolfram Sang and Juergen Beisert
 */
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>

/*
 * Date/Time registers
 */
#define DT_100THS	0x00
#define DT_SECS		0x01
#define DT_MINUTES	0x02
#define DT_HOURS	0x03
#define DT_DAYS		0x04
#define DT_WEEKDAYS	0x05
#define DT_MONTHS	0x06
#define DT_YEARS	0x07

/*
 * Alarm registers
 */
#define DT_SECOND_ALM1	0x08
#define DT_MINUTE_ALM1	0x09
#define DT_HOUR_ALM1	0x0a
#define DT_DAY_ALM1	0x0b
#define DT_MONTH_ALM1	0x0c
#define DT_MINUTE_ALM2	0x0d
#define DT_HOUR_ALM2	0x0e
#define DT_WEEKDAY_ALM2	0x0f
#define DT_ALARM_EN	0x10

/*
 * Time stamp registers
 */
#define DT_TIMESTAMP1	0x11
#define DT_TIMESTAMP2	0x17
#define DT_TIMESTAMP3	0x1d
#define DT_TS_MODE	0x23

/*
 * control registers
 */
#define CTRL_OFFSET	0x24
#define CTRL_OSCILLATOR	0x25
#define CTRL_BATTERY	0x26
#define CTRL_PIN_IO	0x27
#define CTRL_FUNCTION	0x28
#define CTRL_INTA_EN	0x29
#define CTRL_INTB_EN	0x2a
#define CTRL_FLAGS	0x2b
#define CTRL_RAMBYTE	0x2c
#define CTRL_WDOG	0x2d
#define CTRL_STOP_EN	0x2e
#define CTRL_RESETS	0x2f
#define CTRL_RAM	0x40

#define ALRM_SEC_A1E	BIT(0)
#define ALRM_MIN_A1E	BIT(1)
#define ALRM_HR_A1E	BIT(2)
#define ALRM_DAY_A1E	BIT(3)
#define ALRM_MON_A1E	BIT(4)
#define ALRM_MIN_A2E	BIT(5)
#define ALRM_HR_A2E	BIT(6)
#define ALRM_DAY_A2E	BIT(7)

#define INT_WDIE	BIT(0)
#define INT_BSIE	BIT(1)
#define INT_TSRIE	BIT(2)
#define INT_A2IE	BIT(3)
#define INT_A1IE	BIT(4)
#define INT_OIE		BIT(5)
#define INT_PIE		BIT(6)
#define INT_ILP		BIT(7)

#define FLAGS_TSR1F	BIT(0)
#define FLAGS_TSR2F	BIT(1)
#define FLAGS_TSR3F	BIT(2)
#define FLAGS_BSF	BIT(3)
#define FLAGS_WDF	BIT(4)
#define FLAGS_A1F	BIT(5)
#define FLAGS_A2F	BIT(6)
#define FLAGS_PIF	BIT(7)

#define PIN_IO_INTAPM	GENMASK(1, 0)
#define PIN_IO_INTA_CLK	0
#define PIN_IO_INTA_BAT	1
#define PIN_IO_INTA_OUT	2
#define PIN_IO_INTA_HIZ	3

#define STOP_EN_STOP	BIT(0)

#define RESET_CPR	0xa4

#define NVRAM_SIZE	0x40

struct pcf85363 {
	struct rtc_device	*rtc;
	struct regmap		*regmap;
};

struct pcf85x63_config {
	struct regmap_config regmap;
	unsigned int num_nvram;
};

static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char buf[DT_YEARS + 1];
	int ret, len = sizeof(buf);

	/* read the RTC date and time registers all at once */
	ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len);
	if (ret) {
		dev_err(dev, "%s: error %d\n", __func__, ret);
		return ret;
	}

	tm->tm_year = bcd2bin(buf[DT_YEARS]);
	/* adjust for 1900 base of rtc_time */
	tm->tm_year += 100;

	tm->tm_wday = buf[DT_WEEKDAYS] & 7;
	buf[DT_SECS] &= 0x7F;
	tm->tm_sec = bcd2bin(buf[DT_SECS]);
	buf[DT_MINUTES] &= 0x7F;
	tm->tm_min = bcd2bin(buf[DT_MINUTES]);
	tm->tm_hour = bcd2bin(buf[DT_HOURS]);
	tm->tm_mday = bcd2bin(buf[DT_DAYS]);
	tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1;

	return 0;
}

static int pcf85363_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char tmp[11];
	unsigned char *buf = &tmp[2];
	int ret;

	tmp[0] = STOP_EN_STOP;
	tmp[1] = RESET_CPR;

	buf[DT_100THS] = 0;
	buf[DT_SECS] = bin2bcd(tm->tm_sec);
	buf[DT_MINUTES] = bin2bcd(tm->tm_min);
	buf[DT_HOURS] = bin2bcd(tm->tm_hour);
	buf[DT_DAYS] = bin2bcd(tm->tm_mday);
	buf[DT_WEEKDAYS] = tm->tm_wday;
	buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1);
	buf[DT_YEARS] = bin2bcd(tm->tm_year % 100);

	ret = regmap_bulk_write(pcf85363->regmap, CTRL_STOP_EN,
				tmp, sizeof(tmp));
	if (ret)
		return ret;

	return regmap_write(pcf85363->regmap, CTRL_STOP_EN, 0);
}

static int pcf85363_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	unsigned int val;
	int ret;

	ret = regmap_bulk_read(pcf85363->regmap, DT_SECOND_ALM1, buf,
			       sizeof(buf));
	if (ret)
		return ret;

	alrm->time.tm_sec = bcd2bin(buf[0]);
	alrm->time.tm_min = bcd2bin(buf[1]);
	alrm->time.tm_hour = bcd2bin(buf[2]);
	alrm->time.tm_mday = bcd2bin(buf[3]);
	alrm->time.tm_mon = bcd2bin(buf[4]) - 1;

	ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val);
	if (ret)
		return ret;

	alrm->enabled =  !!(val & INT_A1IE);

	return 0;
}

static int _pcf85363_rtc_alarm_irq_enable(struct pcf85363 *pcf85363, unsigned
					  int enabled)
{
	unsigned int alarm_flags = ALRM_SEC_A1E | ALRM_MIN_A1E | ALRM_HR_A1E |
				   ALRM_DAY_A1E | ALRM_MON_A1E;
	int ret;

	ret = regmap_update_bits(pcf85363->regmap, DT_ALARM_EN, alarm_flags,
				 enabled ? alarm_flags : 0);
	if (ret)
		return ret;

	ret = regmap_update_bits(pcf85363->regmap, CTRL_INTA_EN,
				 INT_A1IE, enabled ? INT_A1IE : 0);

	if (ret || enabled)
		return ret;

	/* clear current flags */
	return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
}

static int pcf85363_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);

	return _pcf85363_rtc_alarm_irq_enable(pcf85363, enabled);
}

static int pcf85363_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	int ret;

	buf[0] = bin2bcd(alrm->time.tm_sec);
	buf[1] = bin2bcd(alrm->time.tm_min);
	buf[2] = bin2bcd(alrm->time.tm_hour);
	buf[3] = bin2bcd(alrm->time.tm_mday);
	buf[4] = bin2bcd(alrm->time.tm_mon + 1);

	/*
	 * Disable the alarm interrupt before changing the value to avoid
	 * spurious interrupts
	 */
	ret = _pcf85363_rtc_alarm_irq_enable(pcf85363, 0);
	if (ret)
		return ret;

	ret = regmap_bulk_write(pcf85363->regmap, DT_SECOND_ALM1, buf,
				sizeof(buf));
	if (ret)
		return ret;

	return _pcf85363_rtc_alarm_irq_enable(pcf85363, alrm->enabled);
}

static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
{
	struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
	unsigned int flags;
	int err;

	err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
	if (err)
		return IRQ_NONE;

	if (flags & FLAGS_A1F) {
		rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF | RTC_AF);
		regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static const struct rtc_class_ops rtc_ops = {
	.read_time	= pcf85363_rtc_read_time,
	.set_time	= pcf85363_rtc_set_time,
};

static const struct rtc_class_ops rtc_ops_alarm = {
	.read_time	= pcf85363_rtc_read_time,
	.set_time	= pcf85363_rtc_set_time,
	.read_alarm	= pcf85363_rtc_read_alarm,
	.set_alarm	= pcf85363_rtc_set_alarm,
	.alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
};

static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val,
			       size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;

	return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset,
				val, bytes);
}

static int pcf85363_nvram_write(void *priv, unsigned int offset, void *val,
				size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;

	return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset,
				 val, bytes);
}

static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
			       size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;
	unsigned int tmp_val;
	int ret;

	ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, &tmp_val);
	(*(unsigned char *) val) = (unsigned char) tmp_val;

	return ret;
}

static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
				size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;
	unsigned char tmp_val;

	tmp_val = *((unsigned char *)val);
	return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
				(unsigned int)tmp_val);
}

static const struct pcf85x63_config pcf_85263_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x2f,
	},
	.num_nvram = 1
};

static const struct pcf85x63_config pcf_85363_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x7f,
	},
	.num_nvram = 2
};

static int pcf85363_probe(struct i2c_client *client,
			  const struct i2c_device_id *id)
{
	struct pcf85363 *pcf85363;
	const struct pcf85x63_config *config = &pcf_85363_config;
	const void *data = of_device_get_match_data(&client->dev);
	static struct nvmem_config nvmem_cfg[] = {
		{
			.name = "pcf85x63-",
			.word_size = 1,
			.stride = 1,
			.size = 1,
			.reg_read = pcf85x63_nvram_read,
			.reg_write = pcf85x63_nvram_write,
		}, {
			.name = "pcf85363-",
			.word_size = 1,
			.stride = 1,
			.size = NVRAM_SIZE,
			.reg_read = pcf85363_nvram_read,
			.reg_write = pcf85363_nvram_write,
		},
	};
	int ret, i;

	if (data)
		config = data;

	pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
				GFP_KERNEL);
	if (!pcf85363)
		return -ENOMEM;

	pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
	if (IS_ERR(pcf85363->regmap)) {
		dev_err(&client->dev, "regmap allocation failed\n");
		return PTR_ERR(pcf85363->regmap);
	}

	i2c_set_clientdata(client, pcf85363);

	pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
	if (IS_ERR(pcf85363->rtc))
		return PTR_ERR(pcf85363->rtc);

	pcf85363->rtc->ops = &rtc_ops;
	pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;

	if (client->irq > 0) {
		regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
		regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
				   PIN_IO_INTA_OUT, PIN_IO_INTAPM);
		ret = devm_request_threaded_irq(&client->dev, client->irq,
						NULL, pcf85363_rtc_handle_irq,
						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
						"pcf85363", client);
		if (ret)
			dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
		else
			pcf85363->rtc->ops = &rtc_ops_alarm;
	}

	ret = rtc_register_device(pcf85363->rtc);

	for (i = 0; i < config->num_nvram; i++) {
		nvmem_cfg[i].priv = pcf85363;
		rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
	}

	return ret;
}

static const struct of_device_id dev_ids[] = {
	{ .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
	{ .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dev_ids);

static struct i2c_driver pcf85363_driver = {
	.driver	= {
		.name	= "pcf85363",
		.of_match_table = of_match_ptr(dev_ids),
	},
	.probe	= pcf85363_probe,
};

module_i2c_driver(pcf85363_driver);

MODULE_AUTHOR("Eric Nelson");
MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
a9687aa2 EN	1	/*
	2	* drivers/rtc/rtc-pcf85363.c
	3	*
	4	* Driver for NXP PCF85363 real-time clock.
	5	*
	6	* Copyright (C) 2017 Eric Nelson
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* Based loosely on rtc-8583 by Russell King, Wolfram Sang and Juergen Beisert
	13	*/
	14	#include <linux/module.h>
	15	#include <linux/i2c.h>
	16	#include <linux/slab.h>
	17	#include <linux/rtc.h>
	18	#include <linux/init.h>
	19	#include <linux/err.h>
	20	#include <linux/errno.h>
	21	#include <linux/bcd.h>
	22	#include <linux/of.h>
	23	#include <linux/of_device.h>
	24	#include <linux/regmap.h>
	25
	26	/*
	27	* Date/Time registers
	28	*/
	29	#define DT_100THS 0x00
	30	#define DT_SECS 0x01
	31	#define DT_MINUTES 0x02
	32	#define DT_HOURS 0x03
	33	#define DT_DAYS 0x04
	34	#define DT_WEEKDAYS 0x05
	35	#define DT_MONTHS 0x06
	36	#define DT_YEARS 0x07
	37
	38	/*
	39	* Alarm registers
	40	*/
	41	#define DT_SECOND_ALM1 0x08
	42	#define DT_MINUTE_ALM1 0x09
	43	#define DT_HOUR_ALM1 0x0a
	44	#define DT_DAY_ALM1 0x0b
	45	#define DT_MONTH_ALM1 0x0c
	46	#define DT_MINUTE_ALM2 0x0d
	47	#define DT_HOUR_ALM2 0x0e
	48	#define DT_WEEKDAY_ALM2 0x0f
	49	#define DT_ALARM_EN 0x10
	50
	51	/*
	52	* Time stamp registers
	53	*/
	54	#define DT_TIMESTAMP1 0x11
	55	#define DT_TIMESTAMP2 0x17
	56	#define DT_TIMESTAMP3 0x1d
	57	#define DT_TS_MODE 0x23
	58
	59	/*
	60	* control registers
	61	*/
	62	#define CTRL_OFFSET 0x24
	63	#define CTRL_OSCILLATOR 0x25
	64	#define CTRL_BATTERY 0x26
65	#define CTRL_PIN_IO 0x27
66	#define CTRL_FUNCTION 0x28
67	#define CTRL_INTA_EN 0x29
68	#define CTRL_INTB_EN 0x2a
69	#define CTRL_FLAGS 0x2b
70	#define CTRL_RAMBYTE 0x2c
71	#define CTRL_WDOG 0x2d
72	#define CTRL_STOP_EN 0x2e
73	#define CTRL_RESETS 0x2f
74	#define CTRL_RAM 0x40
75
e5aac267 AB	76	#define ALRM_SEC_A1E BIT(0)
	77	#define ALRM_MIN_A1E BIT(1)
	78	#define ALRM_HR_A1E BIT(2)
	79	#define ALRM_DAY_A1E BIT(3)
	80	#define ALRM_MON_A1E BIT(4)
	81	#define ALRM_MIN_A2E BIT(5)
	82	#define ALRM_HR_A2E BIT(6)
	83	#define ALRM_DAY_A2E BIT(7)
	84
	85	#define INT_WDIE BIT(0)
	86	#define INT_BSIE BIT(1)
	87	#define INT_TSRIE BIT(2)
	88	#define INT_A2IE BIT(3)
	89	#define INT_A1IE BIT(4)
	90	#define INT_OIE BIT(5)
	91	#define INT_PIE BIT(6)
	92	#define INT_ILP BIT(7)
	93
	94	#define FLAGS_TSR1F BIT(0)
	95	#define FLAGS_TSR2F BIT(1)
	96	#define FLAGS_TSR3F BIT(2)
	97	#define FLAGS_BSF BIT(3)
	98	#define FLAGS_WDF BIT(4)
	99	#define FLAGS_A1F BIT(5)
	100	#define FLAGS_A2F BIT(6)
	101	#define FLAGS_PIF BIT(7)
	102
	103	#define PIN_IO_INTAPM GENMASK(1, 0)
	104	#define PIN_IO_INTA_CLK 0
	105	#define PIN_IO_INTA_BAT 1
	106	#define PIN_IO_INTA_OUT 2
	107	#define PIN_IO_INTA_HIZ 3
	108
188306ac AB	109	#define STOP_EN_STOP BIT(0)
	110
	111	#define RESET_CPR 0xa4
	112
a9687aa2 EN	113	#define NVRAM_SIZE 0x40
a9687aa2 EN	114
a9687aa2	115	struct pcf85363 {
a9687aa2	116	struct rtc_device *rtc;
a9687aa2 EN	117	struct regmap *regmap;
	118	};
	119
fc979933 BD	120	struct pcf85x63_config {
	121	struct regmap_config regmap;
	122	unsigned int num_nvram;
	123	};
	124
a9687aa2 EN	125	static int pcf85363_rtc_read_time(struct device dev, struct rtc_time tm)
	126	{
	127	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	128	unsigned char buf[DT_YEARS + 1];
	129	int ret, len = sizeof(buf);
	130
	131	/* read the RTC date and time registers all at once */
	132	ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len);
	133	if (ret) {
	134	dev_err(dev, "%s: error %d\n", __func__, ret);
	135	return ret;
	136	}
	137
	138	tm->tm_year = bcd2bin(buf[DT_YEARS]);
	139	/* adjust for 1900 base of rtc_time */
	140	tm->tm_year += 100;
	141
	142	tm->tm_wday = buf[DT_WEEKDAYS] & 7;
	143	buf[DT_SECS] &= 0x7F;
	144	tm->tm_sec = bcd2bin(buf[DT_SECS]);
	145	buf[DT_MINUTES] &= 0x7F;
	146	tm->tm_min = bcd2bin(buf[DT_MINUTES]);
	147	tm->tm_hour = bcd2bin(buf[DT_HOURS]);
	148	tm->tm_mday = bcd2bin(buf[DT_DAYS]);
	149	tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1;
	150
	151	return 0;
	152	}
	153
	154	static int pcf85363_rtc_set_time(struct device dev, struct rtc_time tm)
	155	{
	156	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
188306ac AB	157	unsigned char tmp[11];
	158	unsigned char *buf = &tmp[2];
	159	int ret;
	160
	161	tmp[0] = STOP_EN_STOP;
	162	tmp[1] = RESET_CPR;
a9687aa2 EN	163
	164	buf[DT_100THS] = 0;
	165	buf[DT_SECS] = bin2bcd(tm->tm_sec);
	166	buf[DT_MINUTES] = bin2bcd(tm->tm_min);
	167	buf[DT_HOURS] = bin2bcd(tm->tm_hour);
	168	buf[DT_DAYS] = bin2bcd(tm->tm_mday);
	169	buf[DT_WEEKDAYS] = tm->tm_wday;
	170	buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1);
	171	buf[DT_YEARS] = bin2bcd(tm->tm_year % 100);
	172
188306ac AB	173	ret = regmap_bulk_write(pcf85363->regmap, CTRL_STOP_EN,
	174	tmp, sizeof(tmp));
	175	if (ret)
	176	return ret;
	177
	178	return regmap_write(pcf85363->regmap, CTRL_STOP_EN, 0);
a9687aa2 EN	179	}
a9687aa2 EN	180
e5aac267 AB	181	static int pcf85363_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	182	{
	183	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	184	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	185	unsigned int val;
	186	int ret;
	187
	188	ret = regmap_bulk_read(pcf85363->regmap, DT_SECOND_ALM1, buf,
	189	sizeof(buf));
	190	if (ret)
	191	return ret;
	192
	193	alrm->time.tm_sec = bcd2bin(buf[0]);
	194	alrm->time.tm_min = bcd2bin(buf[1]);
	195	alrm->time.tm_hour = bcd2bin(buf[2]);
	196	alrm->time.tm_mday = bcd2bin(buf[3]);
	197	alrm->time.tm_mon = bcd2bin(buf[4]) - 1;
	198
	199	ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val);
	200	if (ret)
	201	return ret;
	202
	203	alrm->enabled = !!(val & INT_A1IE);
	204
	205	return 0;
	206	}
	207
	208	static int _pcf85363_rtc_alarm_irq_enable(struct pcf85363 *pcf85363, unsigned
	209	int enabled)
	210	{
	211	unsigned int alarm_flags = ALRM_SEC_A1E \| ALRM_MIN_A1E \| ALRM_HR_A1E \|
	212	ALRM_DAY_A1E \| ALRM_MON_A1E;
	213	int ret;
	214
	215	ret = regmap_update_bits(pcf85363->regmap, DT_ALARM_EN, alarm_flags,
	216	enabled ? alarm_flags : 0);
	217	if (ret)
	218	return ret;
	219
	220	ret = regmap_update_bits(pcf85363->regmap, CTRL_INTA_EN,
	221	INT_A1IE, enabled ? INT_A1IE : 0);
	222
	223	if (ret \|\| enabled)
	224	return ret;
	225
	226	/* clear current flags */
	227	return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
	228	}
	229
	230	static int pcf85363_rtc_alarm_irq_enable(struct device *dev,
	231	unsigned int enabled)
	232	{
	233	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	234
	235	return _pcf85363_rtc_alarm_irq_enable(pcf85363, enabled);
	236	}
	237
	238	static int pcf85363_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	239	{
	240	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	241	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	242	int ret;
	243
	244	buf[0] = bin2bcd(alrm->time.tm_sec);
245	buf[1] = bin2bcd(alrm->time.tm_min);
246	buf[2] = bin2bcd(alrm->time.tm_hour);
247	buf[3] = bin2bcd(alrm->time.tm_mday);
248	buf[4] = bin2bcd(alrm->time.tm_mon + 1);
249
250	/*
251	* Disable the alarm interrupt before changing the value to avoid
252	* spurious interrupts
253	*/
254	ret = _pcf85363_rtc_alarm_irq_enable(pcf85363, 0);
255	if (ret)
256	return ret;
257
258	ret = regmap_bulk_write(pcf85363->regmap, DT_SECOND_ALM1, buf,
259	sizeof(buf));
260	if (ret)
261	return ret;
262
263	return _pcf85363_rtc_alarm_irq_enable(pcf85363, alrm->enabled);
264	}
265
266	static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
267	{
268	struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
269	unsigned int flags;
270	int err;
271
272	err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
273	if (err)
274	return IRQ_NONE;
275
276	if (flags & FLAGS_A1F) {
277	rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF \| RTC_AF);
278	regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
279	return IRQ_HANDLED;
280	}
281
282	return IRQ_NONE;
283	}
284
a9687aa2 EN	285	static const struct rtc_class_ops rtc_ops = {
	286	.read_time = pcf85363_rtc_read_time,
	287	.set_time = pcf85363_rtc_set_time,
	288	};
	289
e5aac267 AB	290	static const struct rtc_class_ops rtc_ops_alarm = {
	291	.read_time = pcf85363_rtc_read_time,
	292	.set_time = pcf85363_rtc_set_time,
	293	.read_alarm = pcf85363_rtc_read_alarm,
	294	.set_alarm = pcf85363_rtc_set_alarm,
	295	.alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
	296	};
	297
a9687aa2 EN	298	static int pcf85363_nvram_read(void priv, unsigned int offset, void val,
	299	size_t bytes)
	300	{
	301	struct pcf85363 *pcf85363 = priv;
	302
	303	return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset,
	304	val, bytes);
	305	}
	306
	307	static int pcf85363_nvram_write(void priv, unsigned int offset, void val,
	308	size_t bytes)
	309	{
	310	struct pcf85363 *pcf85363 = priv;
	311
	312	return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset,
	313	val, bytes);
	314	}
	315
fc979933 BD	316	static int pcf85x63_nvram_read(void priv, unsigned int offset, void val,
	317	size_t bytes)
	318	{
	319	struct pcf85363 *pcf85363 = priv;
	320	unsigned int tmp_val;
	321	int ret;
	322
	323	ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, &tmp_val);
	324	((unsigned char ) val) = (unsigned char) tmp_val;
	325
	326	return ret;
	327	}
	328
	329	static int pcf85x63_nvram_write(void priv, unsigned int offset, void val,
	330	size_t bytes)
	331	{
	332	struct pcf85363 *pcf85363 = priv;
	333	unsigned char tmp_val;
	334
	335	tmp_val = ((unsigned char )val);
	336	return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
	337	(unsigned int)tmp_val);
	338	}
	339
	340	static const struct pcf85x63_config pcf_85263_config = {
	341	.regmap = {
	342	.reg_bits = 8,
	343	.val_bits = 8,
	344	.max_register = 0x2f,
	345	},
	346	.num_nvram = 1
	347	};
	348
	349	static const struct pcf85x63_config pcf_85363_config = {
	350	.regmap = {
	351	.reg_bits = 8,
	352	.val_bits = 8,
	353	.max_register = 0x7f,
	354	},
	355	.num_nvram = 2
a9687aa2 EN	356	};
	357
	358	static int pcf85363_probe(struct i2c_client *client,
	359	const struct i2c_device_id *id)
	360	{
	361	struct pcf85363 *pcf85363;
fc979933 BD	362	const struct pcf85x63_config *config = &pcf_85363_config;
	363	const void *data = of_device_get_match_data(&client->dev);
	364	static struct nvmem_config nvmem_cfg[] = {
	365	{
	366	.name = "pcf85x63-",
	367	.word_size = 1,
	368	.stride = 1,
	369	.size = 1,
	370	.reg_read = pcf85x63_nvram_read,
	371	.reg_write = pcf85x63_nvram_write,
	372	}, {
	373	.name = "pcf85363-",
	374	.word_size = 1,
	375	.stride = 1,
	376	.size = NVRAM_SIZE,
	377	.reg_read = pcf85363_nvram_read,
	378	.reg_write = pcf85363_nvram_write,
	379	},
0e7a412f	380	};
fc979933 BD	381	int ret, i;
	382
	383	if (data)
	384	config = data;
a9687aa2	385
a9687aa2 EN	386	pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
	387	GFP_KERNEL);
	388	if (!pcf85363)
	389	return -ENOMEM;
	390
fc979933	391	pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
a9687aa2 EN	392	if (IS_ERR(pcf85363->regmap)) {
	393	dev_err(&client->dev, "regmap allocation failed\n");
	394	return PTR_ERR(pcf85363->regmap);
	395	}
	396
a9687aa2 EN	397	i2c_set_clientdata(client, pcf85363);
a9687aa2 EN	398
8f7b1d71	399	pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
a9687aa2 EN	400	if (IS_ERR(pcf85363->rtc))
	401	return PTR_ERR(pcf85363->rtc);
	402
a9687aa2	403	pcf85363->rtc->ops = &rtc_ops;
c0ec8319 AB	404	pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
c0ec8319 AB	405	pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;
a9687aa2	406
e5aac267 AB	407	if (client->irq > 0) {
	408	regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
	409	regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
	410	PIN_IO_INTA_OUT, PIN_IO_INTAPM);
8f7b1d71	411	ret = devm_request_threaded_irq(&client->dev, client->irq,
e5aac267 AB	412	NULL, pcf85363_rtc_handle_irq,
	413	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	414	"pcf85363", client);
	415	if (ret)
	416	dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
	417	else
	418	pcf85363->rtc->ops = &rtc_ops_alarm;
	419	}
	420
24849d17 AB	421	ret = rtc_register_device(pcf85363->rtc);
24849d17 AB	422
fc979933 BD	423	for (i = 0; i < config->num_nvram; i++) {
	424	nvmem_cfg[i].priv = pcf85363;
	425	rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
	426	}
24849d17 AB	427
24849d17 AB	428	return ret;
a9687aa2 EN	429	}
	430
	431	static const struct of_device_id dev_ids[] = {
fc979933 BD	432	{ .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
	433	{ .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
	434	{ /* sentinel */ }
a9687aa2 EN	435	};
	436	MODULE_DEVICE_TABLE(of, dev_ids);
	437
	438	static struct i2c_driver pcf85363_driver = {
	439	.driver = {
	440	.name = "pcf85363",
	441	.of_match_table = of_match_ptr(dev_ids),
	442	},
	443	.probe = pcf85363_probe,
	444	};
	445
	446	module_i2c_driver(pcf85363_driver);
	447
	448	MODULE_AUTHOR("Eric Nelson");
fc979933	449	MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
a9687aa2	450	MODULE_LICENSE("GPL");