[mirror_ubuntu-hirsute-kernel.git] / drivers / rtc / rtc-pcf85363.c

// SPDX-License-Identifier: GPL-2.0
/*
 * drivers/rtc/rtc-pcf85363.c
 *
 * Driver for NXP PCF85363 real-time clock.
 *
 * Copyright (C) 2017 Eric Nelson
 */
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>

/*
 * Date/Time registers
 */
#define DT_100THS	0x00
#define DT_SECS		0x01
#define DT_MINUTES	0x02
#define DT_HOURS	0x03
#define DT_DAYS		0x04
#define DT_WEEKDAYS	0x05
#define DT_MONTHS	0x06
#define DT_YEARS	0x07

/*
 * Alarm registers
 */
#define DT_SECOND_ALM1	0x08
#define DT_MINUTE_ALM1	0x09
#define DT_HOUR_ALM1	0x0a
#define DT_DAY_ALM1	0x0b
#define DT_MONTH_ALM1	0x0c
#define DT_MINUTE_ALM2	0x0d
#define DT_HOUR_ALM2	0x0e
#define DT_WEEKDAY_ALM2	0x0f
#define DT_ALARM_EN	0x10

/*
 * Time stamp registers
 */
#define DT_TIMESTAMP1	0x11
#define DT_TIMESTAMP2	0x17
#define DT_TIMESTAMP3	0x1d
#define DT_TS_MODE	0x23

/*
 * control registers
 */
#define CTRL_OFFSET	0x24
#define CTRL_OSCILLATOR	0x25
#define CTRL_BATTERY	0x26
#define CTRL_PIN_IO	0x27
#define CTRL_FUNCTION	0x28
#define CTRL_INTA_EN	0x29
#define CTRL_INTB_EN	0x2a
#define CTRL_FLAGS	0x2b
#define CTRL_RAMBYTE	0x2c
#define CTRL_WDOG	0x2d
#define CTRL_STOP_EN	0x2e
#define CTRL_RESETS	0x2f
#define CTRL_RAM	0x40

#define ALRM_SEC_A1E	BIT(0)
#define ALRM_MIN_A1E	BIT(1)
#define ALRM_HR_A1E	BIT(2)
#define ALRM_DAY_A1E	BIT(3)
#define ALRM_MON_A1E	BIT(4)
#define ALRM_MIN_A2E	BIT(5)
#define ALRM_HR_A2E	BIT(6)
#define ALRM_DAY_A2E	BIT(7)

#define INT_WDIE	BIT(0)
#define INT_BSIE	BIT(1)
#define INT_TSRIE	BIT(2)
#define INT_A2IE	BIT(3)
#define INT_A1IE	BIT(4)
#define INT_OIE		BIT(5)
#define INT_PIE		BIT(6)
#define INT_ILP		BIT(7)

#define FLAGS_TSR1F	BIT(0)
#define FLAGS_TSR2F	BIT(1)
#define FLAGS_TSR3F	BIT(2)
#define FLAGS_BSF	BIT(3)
#define FLAGS_WDF	BIT(4)
#define FLAGS_A1F	BIT(5)
#define FLAGS_A2F	BIT(6)
#define FLAGS_PIF	BIT(7)

#define PIN_IO_INTAPM	GENMASK(1, 0)
#define PIN_IO_INTA_CLK	0
#define PIN_IO_INTA_BAT	1
#define PIN_IO_INTA_OUT	2
#define PIN_IO_INTA_HIZ	3

#define STOP_EN_STOP	BIT(0)

#define RESET_CPR	0xa4

#define NVRAM_SIZE	0x40

struct pcf85363 {
	struct rtc_device	*rtc;
	struct regmap		*regmap;
};

struct pcf85x63_config {
	struct regmap_config regmap;
	unsigned int num_nvram;
};

static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char buf[DT_YEARS + 1];
	int ret, len = sizeof(buf);

	/* read the RTC date and time registers all at once */
	ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len);
	if (ret) {
		dev_err(dev, "%s: error %d\n", __func__, ret);
		return ret;
	}

	tm->tm_year = bcd2bin(buf[DT_YEARS]);
	/* adjust for 1900 base of rtc_time */
	tm->tm_year += 100;

	tm->tm_wday = buf[DT_WEEKDAYS] & 7;
	buf[DT_SECS] &= 0x7F;
	tm->tm_sec = bcd2bin(buf[DT_SECS]);
	buf[DT_MINUTES] &= 0x7F;
	tm->tm_min = bcd2bin(buf[DT_MINUTES]);
	tm->tm_hour = bcd2bin(buf[DT_HOURS]);
	tm->tm_mday = bcd2bin(buf[DT_DAYS]);
	tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1;

	return 0;
}

static int pcf85363_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char tmp[11];
	unsigned char *buf = &tmp[2];
	int ret;

	tmp[0] = STOP_EN_STOP;
	tmp[1] = RESET_CPR;

	buf[DT_100THS] = 0;
	buf[DT_SECS] = bin2bcd(tm->tm_sec);
	buf[DT_MINUTES] = bin2bcd(tm->tm_min);
	buf[DT_HOURS] = bin2bcd(tm->tm_hour);
	buf[DT_DAYS] = bin2bcd(tm->tm_mday);
	buf[DT_WEEKDAYS] = tm->tm_wday;
	buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1);
	buf[DT_YEARS] = bin2bcd(tm->tm_year % 100);

	ret = regmap_bulk_write(pcf85363->regmap, CTRL_STOP_EN,
				tmp, sizeof(tmp));
	if (ret)
		return ret;

	return regmap_write(pcf85363->regmap, CTRL_STOP_EN, 0);
}

static int pcf85363_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	unsigned int val;
	int ret;

	ret = regmap_bulk_read(pcf85363->regmap, DT_SECOND_ALM1, buf,
			       sizeof(buf));
	if (ret)
		return ret;

	alrm->time.tm_sec = bcd2bin(buf[0]);
	alrm->time.tm_min = bcd2bin(buf[1]);
	alrm->time.tm_hour = bcd2bin(buf[2]);
	alrm->time.tm_mday = bcd2bin(buf[3]);
	alrm->time.tm_mon = bcd2bin(buf[4]) - 1;

	ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val);
	if (ret)
		return ret;

	alrm->enabled =  !!(val & INT_A1IE);

	return 0;
}

static int _pcf85363_rtc_alarm_irq_enable(struct pcf85363 *pcf85363, unsigned
					  int enabled)
{
	unsigned int alarm_flags = ALRM_SEC_A1E | ALRM_MIN_A1E | ALRM_HR_A1E |
				   ALRM_DAY_A1E | ALRM_MON_A1E;
	int ret;

	ret = regmap_update_bits(pcf85363->regmap, DT_ALARM_EN, alarm_flags,
				 enabled ? alarm_flags : 0);
	if (ret)
		return ret;

	ret = regmap_update_bits(pcf85363->regmap, CTRL_INTA_EN,
				 INT_A1IE, enabled ? INT_A1IE : 0);

	if (ret || enabled)
		return ret;

	/* clear current flags */
	return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
}

static int pcf85363_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);

	return _pcf85363_rtc_alarm_irq_enable(pcf85363, enabled);
}

static int pcf85363_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	int ret;

	buf[0] = bin2bcd(alrm->time.tm_sec);
	buf[1] = bin2bcd(alrm->time.tm_min);
	buf[2] = bin2bcd(alrm->time.tm_hour);
	buf[3] = bin2bcd(alrm->time.tm_mday);
	buf[4] = bin2bcd(alrm->time.tm_mon + 1);

	/*
	 * Disable the alarm interrupt before changing the value to avoid
	 * spurious interrupts
	 */
	ret = _pcf85363_rtc_alarm_irq_enable(pcf85363, 0);
	if (ret)
		return ret;

	ret = regmap_bulk_write(pcf85363->regmap, DT_SECOND_ALM1, buf,
				sizeof(buf));
	if (ret)
		return ret;

	return _pcf85363_rtc_alarm_irq_enable(pcf85363, alrm->enabled);
}

static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
{
	struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
	unsigned int flags;
	int err;

	err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
	if (err)
		return IRQ_NONE;

	if (flags & FLAGS_A1F) {
		rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF | RTC_AF);
		regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static const struct rtc_class_ops rtc_ops = {
	.read_time	= pcf85363_rtc_read_time,
	.set_time	= pcf85363_rtc_set_time,
};

static const struct rtc_class_ops rtc_ops_alarm = {
	.read_time	= pcf85363_rtc_read_time,
	.set_time	= pcf85363_rtc_set_time,
	.read_alarm	= pcf85363_rtc_read_alarm,
	.set_alarm	= pcf85363_rtc_set_alarm,
	.alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
};

static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val,
			       size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;

	return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset,
				val, bytes);
}

static int pcf85363_nvram_write(void *priv, unsigned int offset, void *val,
				size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;

	return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset,
				 val, bytes);
}

static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
			       size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;
	unsigned int tmp_val;
	int ret;

	ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, &tmp_val);
	(*(unsigned char *) val) = (unsigned char) tmp_val;

	return ret;
}

static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
				size_t bytes)
{
	struct pcf85363 *pcf85363 = priv;
	unsigned char tmp_val;

	tmp_val = *((unsigned char *)val);
	return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
				(unsigned int)tmp_val);
}

static const struct pcf85x63_config pcf_85263_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x2f,
	},
	.num_nvram = 1
};

static const struct pcf85x63_config pcf_85363_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x7f,
	},
	.num_nvram = 2
};

static int pcf85363_probe(struct i2c_client *client,
			  const struct i2c_device_id *id)
{
	struct pcf85363 *pcf85363;
	const struct pcf85x63_config *config = &pcf_85363_config;
	const void *data = of_device_get_match_data(&client->dev);
	static struct nvmem_config nvmem_cfg[] = {
		{
			.name = "pcf85x63-",
			.word_size = 1,
			.stride = 1,
			.size = 1,
			.reg_read = pcf85x63_nvram_read,
			.reg_write = pcf85x63_nvram_write,
		}, {
			.name = "pcf85363-",
			.word_size = 1,
			.stride = 1,
			.size = NVRAM_SIZE,
			.reg_read = pcf85363_nvram_read,
			.reg_write = pcf85363_nvram_write,
		},
	};
	int ret, i;

	if (data)
		config = data;

	pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
				GFP_KERNEL);
	if (!pcf85363)
		return -ENOMEM;

	pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
	if (IS_ERR(pcf85363->regmap)) {
		dev_err(&client->dev, "regmap allocation failed\n");
		return PTR_ERR(pcf85363->regmap);
	}

	i2c_set_clientdata(client, pcf85363);

	pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
	if (IS_ERR(pcf85363->rtc))
		return PTR_ERR(pcf85363->rtc);

	pcf85363->rtc->ops = &rtc_ops;
	pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;

	if (client->irq > 0) {
		regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
		regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
				   PIN_IO_INTA_OUT, PIN_IO_INTAPM);
		ret = devm_request_threaded_irq(&client->dev, client->irq,
						NULL, pcf85363_rtc_handle_irq,
						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
						"pcf85363", client);
		if (ret)
			dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
		else
			pcf85363->rtc->ops = &rtc_ops_alarm;
	}

	ret = rtc_register_device(pcf85363->rtc);

	for (i = 0; i < config->num_nvram; i++) {
		nvmem_cfg[i].priv = pcf85363;
		rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
	}

	return ret;
}

static const struct of_device_id dev_ids[] = {
	{ .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
	{ .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dev_ids);

static struct i2c_driver pcf85363_driver = {
	.driver	= {
		.name	= "pcf85363",
		.of_match_table = of_match_ptr(dev_ids),
	},
	.probe	= pcf85363_probe,
};

module_i2c_driver(pcf85363_driver);

MODULE_AUTHOR("Eric Nelson");
MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
56573ca7	1	// SPDX-License-Identifier: GPL-2.0
a9687aa2 EN	2	/*
	3	* drivers/rtc/rtc-pcf85363.c
	4	*
	5	* Driver for NXP PCF85363 real-time clock.
	6	*
	7	* Copyright (C) 2017 Eric Nelson
a9687aa2 EN	8	*/
	9	#include <linux/module.h>
	10	#include <linux/i2c.h>
	11	#include <linux/slab.h>
	12	#include <linux/rtc.h>
	13	#include <linux/init.h>
	14	#include <linux/err.h>
	15	#include <linux/errno.h>
	16	#include <linux/bcd.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
	19	#include <linux/regmap.h>
	20
	21	/*
	22	* Date/Time registers
	23	*/
	24	#define DT_100THS 0x00
	25	#define DT_SECS 0x01
	26	#define DT_MINUTES 0x02
	27	#define DT_HOURS 0x03
	28	#define DT_DAYS 0x04
	29	#define DT_WEEKDAYS 0x05
	30	#define DT_MONTHS 0x06
	31	#define DT_YEARS 0x07
	32
	33	/*
	34	* Alarm registers
	35	*/
	36	#define DT_SECOND_ALM1 0x08
	37	#define DT_MINUTE_ALM1 0x09
	38	#define DT_HOUR_ALM1 0x0a
	39	#define DT_DAY_ALM1 0x0b
	40	#define DT_MONTH_ALM1 0x0c
	41	#define DT_MINUTE_ALM2 0x0d
	42	#define DT_HOUR_ALM2 0x0e
	43	#define DT_WEEKDAY_ALM2 0x0f
	44	#define DT_ALARM_EN 0x10
	45
	46	/*
	47	* Time stamp registers
	48	*/
	49	#define DT_TIMESTAMP1 0x11
	50	#define DT_TIMESTAMP2 0x17
	51	#define DT_TIMESTAMP3 0x1d
	52	#define DT_TS_MODE 0x23
	53
	54	/*
	55	* control registers
	56	*/
	57	#define CTRL_OFFSET 0x24
	58	#define CTRL_OSCILLATOR 0x25
	59	#define CTRL_BATTERY 0x26
	60	#define CTRL_PIN_IO 0x27
	61	#define CTRL_FUNCTION 0x28
	62	#define CTRL_INTA_EN 0x29
	63	#define CTRL_INTB_EN 0x2a
	64	#define CTRL_FLAGS 0x2b
	65	#define CTRL_RAMBYTE 0x2c
	66	#define CTRL_WDOG 0x2d
	67	#define CTRL_STOP_EN 0x2e
	68	#define CTRL_RESETS 0x2f
	69	#define CTRL_RAM 0x40
	70
e5aac267 AB	71	#define ALRM_SEC_A1E BIT(0)
	72	#define ALRM_MIN_A1E BIT(1)
	73	#define ALRM_HR_A1E BIT(2)
	74	#define ALRM_DAY_A1E BIT(3)
	75	#define ALRM_MON_A1E BIT(4)
	76	#define ALRM_MIN_A2E BIT(5)
	77	#define ALRM_HR_A2E BIT(6)
	78	#define ALRM_DAY_A2E BIT(7)
	79
	80	#define INT_WDIE BIT(0)
	81	#define INT_BSIE BIT(1)
	82	#define INT_TSRIE BIT(2)
	83	#define INT_A2IE BIT(3)
	84	#define INT_A1IE BIT(4)
	85	#define INT_OIE BIT(5)
	86	#define INT_PIE BIT(6)
	87	#define INT_ILP BIT(7)
	88
	89	#define FLAGS_TSR1F BIT(0)
	90	#define FLAGS_TSR2F BIT(1)
	91	#define FLAGS_TSR3F BIT(2)
	92	#define FLAGS_BSF BIT(3)
	93	#define FLAGS_WDF BIT(4)
	94	#define FLAGS_A1F BIT(5)
	95	#define FLAGS_A2F BIT(6)
	96	#define FLAGS_PIF BIT(7)
	97
	98	#define PIN_IO_INTAPM GENMASK(1, 0)
	99	#define PIN_IO_INTA_CLK 0
	100	#define PIN_IO_INTA_BAT 1
	101	#define PIN_IO_INTA_OUT 2
	102	#define PIN_IO_INTA_HIZ 3
	103
188306ac AB	104	#define STOP_EN_STOP BIT(0)
	105
	106	#define RESET_CPR 0xa4
	107
a9687aa2 EN	108	#define NVRAM_SIZE 0x40
a9687aa2 EN	109
a9687aa2	110	struct pcf85363 {
a9687aa2	111	struct rtc_device *rtc;
a9687aa2 EN	112	struct regmap *regmap;
	113	};
	114
fc979933 BD	115	struct pcf85x63_config {
	116	struct regmap_config regmap;
	117	unsigned int num_nvram;
	118	};
	119
a9687aa2 EN	120	static int pcf85363_rtc_read_time(struct device dev, struct rtc_time tm)
	121	{
	122	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	123	unsigned char buf[DT_YEARS + 1];
	124	int ret, len = sizeof(buf);
	125
	126	/* read the RTC date and time registers all at once */
	127	ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len);
	128	if (ret) {
	129	dev_err(dev, "%s: error %d\n", __func__, ret);
	130	return ret;
	131	}
	132
	133	tm->tm_year = bcd2bin(buf[DT_YEARS]);
	134	/* adjust for 1900 base of rtc_time */
	135	tm->tm_year += 100;
	136
	137	tm->tm_wday = buf[DT_WEEKDAYS] & 7;
	138	buf[DT_SECS] &= 0x7F;
	139	tm->tm_sec = bcd2bin(buf[DT_SECS]);
	140	buf[DT_MINUTES] &= 0x7F;
	141	tm->tm_min = bcd2bin(buf[DT_MINUTES]);
	142	tm->tm_hour = bcd2bin(buf[DT_HOURS]);
	143	tm->tm_mday = bcd2bin(buf[DT_DAYS]);
	144	tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1;
	145
	146	return 0;
	147	}
	148
	149	static int pcf85363_rtc_set_time(struct device dev, struct rtc_time tm)
	150	{
	151	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
188306ac AB	152	unsigned char tmp[11];
	153	unsigned char *buf = &tmp[2];
	154	int ret;
	155
	156	tmp[0] = STOP_EN_STOP;
	157	tmp[1] = RESET_CPR;
a9687aa2 EN	158
	159	buf[DT_100THS] = 0;
	160	buf[DT_SECS] = bin2bcd(tm->tm_sec);
	161	buf[DT_MINUTES] = bin2bcd(tm->tm_min);
	162	buf[DT_HOURS] = bin2bcd(tm->tm_hour);
	163	buf[DT_DAYS] = bin2bcd(tm->tm_mday);
	164	buf[DT_WEEKDAYS] = tm->tm_wday;
	165	buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1);
	166	buf[DT_YEARS] = bin2bcd(tm->tm_year % 100);
	167
188306ac AB	168	ret = regmap_bulk_write(pcf85363->regmap, CTRL_STOP_EN,
	169	tmp, sizeof(tmp));
	170	if (ret)
	171	return ret;
	172
	173	return regmap_write(pcf85363->regmap, CTRL_STOP_EN, 0);
a9687aa2 EN	174	}
a9687aa2 EN	175
e5aac267 AB	176	static int pcf85363_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	177	{
	178	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	179	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	180	unsigned int val;
	181	int ret;
	182
	183	ret = regmap_bulk_read(pcf85363->regmap, DT_SECOND_ALM1, buf,
	184	sizeof(buf));
	185	if (ret)
	186	return ret;
	187
	188	alrm->time.tm_sec = bcd2bin(buf[0]);
	189	alrm->time.tm_min = bcd2bin(buf[1]);
	190	alrm->time.tm_hour = bcd2bin(buf[2]);
	191	alrm->time.tm_mday = bcd2bin(buf[3]);
	192	alrm->time.tm_mon = bcd2bin(buf[4]) - 1;
	193
	194	ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val);
	195	if (ret)
	196	return ret;
	197
	198	alrm->enabled = !!(val & INT_A1IE);
	199
	200	return 0;
	201	}
	202
	203	static int _pcf85363_rtc_alarm_irq_enable(struct pcf85363 *pcf85363, unsigned
	204	int enabled)
	205	{
	206	unsigned int alarm_flags = ALRM_SEC_A1E \| ALRM_MIN_A1E \| ALRM_HR_A1E \|
	207	ALRM_DAY_A1E \| ALRM_MON_A1E;
	208	int ret;
	209
	210	ret = regmap_update_bits(pcf85363->regmap, DT_ALARM_EN, alarm_flags,
	211	enabled ? alarm_flags : 0);
	212	if (ret)
	213	return ret;
	214
	215	ret = regmap_update_bits(pcf85363->regmap, CTRL_INTA_EN,
	216	INT_A1IE, enabled ? INT_A1IE : 0);
	217
	218	if (ret \|\| enabled)
	219	return ret;
	220
	221	/* clear current flags */
	222	return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
	223	}
	224
	225	static int pcf85363_rtc_alarm_irq_enable(struct device *dev,
	226	unsigned int enabled)
	227	{
	228	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	229
	230	return _pcf85363_rtc_alarm_irq_enable(pcf85363, enabled);
	231	}
	232
	233	static int pcf85363_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	234	{
	235	struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
	236	unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
	237	int ret;
	238
	239	buf[0] = bin2bcd(alrm->time.tm_sec);
240	buf[1] = bin2bcd(alrm->time.tm_min);
241	buf[2] = bin2bcd(alrm->time.tm_hour);
242	buf[3] = bin2bcd(alrm->time.tm_mday);
243	buf[4] = bin2bcd(alrm->time.tm_mon + 1);
244
245	/*
246	* Disable the alarm interrupt before changing the value to avoid
247	* spurious interrupts
248	*/
249	ret = _pcf85363_rtc_alarm_irq_enable(pcf85363, 0);
250	if (ret)
251	return ret;
252
253	ret = regmap_bulk_write(pcf85363->regmap, DT_SECOND_ALM1, buf,
254	sizeof(buf));
255	if (ret)
256	return ret;
257
258	return _pcf85363_rtc_alarm_irq_enable(pcf85363, alrm->enabled);
259	}
260
261	static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
262	{
263	struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
264	unsigned int flags;
265	int err;
266
267	err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
268	if (err)
269	return IRQ_NONE;
270
271	if (flags & FLAGS_A1F) {
272	rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF \| RTC_AF);
273	regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
274	return IRQ_HANDLED;
275	}
276
277	return IRQ_NONE;
278	}
279
a9687aa2 EN	280	static const struct rtc_class_ops rtc_ops = {
	281	.read_time = pcf85363_rtc_read_time,
	282	.set_time = pcf85363_rtc_set_time,
	283	};
	284
e5aac267 AB	285	static const struct rtc_class_ops rtc_ops_alarm = {
	286	.read_time = pcf85363_rtc_read_time,
	287	.set_time = pcf85363_rtc_set_time,
	288	.read_alarm = pcf85363_rtc_read_alarm,
	289	.set_alarm = pcf85363_rtc_set_alarm,
	290	.alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
	291	};
	292
a9687aa2 EN	293	static int pcf85363_nvram_read(void priv, unsigned int offset, void val,
	294	size_t bytes)
	295	{
	296	struct pcf85363 *pcf85363 = priv;
	297
	298	return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset,
	299	val, bytes);
	300	}
	301
	302	static int pcf85363_nvram_write(void priv, unsigned int offset, void val,
	303	size_t bytes)
	304	{
	305	struct pcf85363 *pcf85363 = priv;
	306
	307	return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset,
	308	val, bytes);
	309	}
	310
fc979933 BD	311	static int pcf85x63_nvram_read(void priv, unsigned int offset, void val,
	312	size_t bytes)
	313	{
	314	struct pcf85363 *pcf85363 = priv;
	315	unsigned int tmp_val;
	316	int ret;
	317
	318	ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, &tmp_val);
	319	((unsigned char ) val) = (unsigned char) tmp_val;
	320
	321	return ret;
	322	}
	323
	324	static int pcf85x63_nvram_write(void priv, unsigned int offset, void val,
	325	size_t bytes)
	326	{
	327	struct pcf85363 *pcf85363 = priv;
	328	unsigned char tmp_val;
	329
	330	tmp_val = ((unsigned char )val);
	331	return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
	332	(unsigned int)tmp_val);
	333	}
	334
	335	static const struct pcf85x63_config pcf_85263_config = {
	336	.regmap = {
	337	.reg_bits = 8,
	338	.val_bits = 8,
	339	.max_register = 0x2f,
	340	},
	341	.num_nvram = 1
	342	};
	343
	344	static const struct pcf85x63_config pcf_85363_config = {
	345	.regmap = {
	346	.reg_bits = 8,
	347	.val_bits = 8,
	348	.max_register = 0x7f,
	349	},
	350	.num_nvram = 2
a9687aa2 EN	351	};
	352
	353	static int pcf85363_probe(struct i2c_client *client,
	354	const struct i2c_device_id *id)
	355	{
	356	struct pcf85363 *pcf85363;
fc979933 BD	357	const struct pcf85x63_config *config = &pcf_85363_config;
	358	const void *data = of_device_get_match_data(&client->dev);
	359	static struct nvmem_config nvmem_cfg[] = {
	360	{
	361	.name = "pcf85x63-",
	362	.word_size = 1,
	363	.stride = 1,
	364	.size = 1,
	365	.reg_read = pcf85x63_nvram_read,
	366	.reg_write = pcf85x63_nvram_write,
	367	}, {
	368	.name = "pcf85363-",
	369	.word_size = 1,
	370	.stride = 1,
	371	.size = NVRAM_SIZE,
	372	.reg_read = pcf85363_nvram_read,
	373	.reg_write = pcf85363_nvram_write,
	374	},
0e7a412f	375	};
fc979933 BD	376	int ret, i;
	377
	378	if (data)
	379	config = data;
a9687aa2	380
a9687aa2 EN	381	pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
	382	GFP_KERNEL);
	383	if (!pcf85363)
	384	return -ENOMEM;
	385
fc979933	386	pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
a9687aa2 EN	387	if (IS_ERR(pcf85363->regmap)) {
	388	dev_err(&client->dev, "regmap allocation failed\n");
	389	return PTR_ERR(pcf85363->regmap);
	390	}
	391
a9687aa2 EN	392	i2c_set_clientdata(client, pcf85363);
a9687aa2 EN	393
8f7b1d71	394	pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
a9687aa2 EN	395	if (IS_ERR(pcf85363->rtc))
	396	return PTR_ERR(pcf85363->rtc);
	397
a9687aa2	398	pcf85363->rtc->ops = &rtc_ops;
c0ec8319 AB	399	pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
c0ec8319 AB	400	pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;
a9687aa2	401
e5aac267 AB	402	if (client->irq > 0) {
	403	regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
	404	regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
	405	PIN_IO_INTA_OUT, PIN_IO_INTAPM);
8f7b1d71	406	ret = devm_request_threaded_irq(&client->dev, client->irq,
e5aac267 AB	407	NULL, pcf85363_rtc_handle_irq,
	408	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	409	"pcf85363", client);
	410	if (ret)
	411	dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
	412	else
	413	pcf85363->rtc->ops = &rtc_ops_alarm;
	414	}
	415
24849d17 AB	416	ret = rtc_register_device(pcf85363->rtc);
24849d17 AB	417
fc979933 BD	418	for (i = 0; i < config->num_nvram; i++) {
	419	nvmem_cfg[i].priv = pcf85363;
	420	rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
	421	}
24849d17 AB	422
24849d17 AB	423	return ret;
a9687aa2 EN	424	}
	425
	426	static const struct of_device_id dev_ids[] = {
fc979933 BD	427	{ .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
	428	{ .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
	429	{ /* sentinel */ }
a9687aa2 EN	430	};
	431	MODULE_DEVICE_TABLE(of, dev_ids);
	432
	433	static struct i2c_driver pcf85363_driver = {
	434	.driver = {
	435	.name = "pcf85363",
	436	.of_match_table = of_match_ptr(dev_ids),
	437	},
	438	.probe = pcf85363_probe,
	439	};
	440
	441	module_i2c_driver(pcf85363_driver);
	442
	443	MODULE_AUTHOR("Eric Nelson");
fc979933	444	MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
a9687aa2	445	MODULE_LICENSE("GPL");