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Commit | Line | Data |
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1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
39ce4084 | 28 | #include <linux/of.h> |
dbd9acbe SK |
29 | #include <linux/uaccess.h> |
30 | #include <linux/io.h> | |
1add6781 | 31 | |
1add6781 | 32 | #include <asm/irq.h> |
b9d7c5d3 | 33 | #include "rtc-s3c.h" |
1add6781 | 34 | |
19be09f5 CC |
35 | struct s3c_rtc { |
36 | struct device *dev; | |
37 | struct rtc_device *rtc; | |
38 | ||
39 | void __iomem *base; | |
40 | struct clk *rtc_clk; | |
df9e26d0 | 41 | struct clk *rtc_src_clk; |
1fb1c35f | 42 | bool clk_disabled; |
19be09f5 | 43 | |
6b72086d | 44 | const struct s3c_rtc_data *data; |
1add6781 | 45 | |
19be09f5 CC |
46 | int irq_alarm; |
47 | int irq_tick; | |
1add6781 | 48 | |
19be09f5 CC |
49 | spinlock_t pie_lock; |
50 | spinlock_t alarm_clk_lock; | |
1add6781 | 51 | |
fc1afe60 KK |
52 | int ticnt_save; |
53 | int ticnt_en_save; | |
19be09f5 CC |
54 | bool wake_en; |
55 | }; | |
56 | ||
ae05c950 CC |
57 | struct s3c_rtc_data { |
58 | int max_user_freq; | |
df9e26d0 | 59 | bool needs_src_clk; |
ae05c950 CC |
60 | |
61 | void (*irq_handler) (struct s3c_rtc *info, int mask); | |
62 | void (*set_freq) (struct s3c_rtc *info, int freq); | |
63 | void (*enable_tick) (struct s3c_rtc *info, struct seq_file *seq); | |
64 | void (*select_tick_clk) (struct s3c_rtc *info); | |
65 | void (*save_tick_cnt) (struct s3c_rtc *info); | |
66 | void (*restore_tick_cnt) (struct s3c_rtc *info); | |
67 | void (*enable) (struct s3c_rtc *info); | |
68 | void (*disable) (struct s3c_rtc *info); | |
69 | }; | |
70 | ||
498bcf31 | 71 | static int s3c_rtc_enable_clk(struct s3c_rtc *info) |
88cee8fd | 72 | { |
88cee8fd | 73 | unsigned long irq_flags; |
498bcf31 | 74 | int ret = 0; |
88cee8fd | 75 | |
19be09f5 | 76 | spin_lock_irqsave(&info->alarm_clk_lock, irq_flags); |
498bcf31 | 77 | |
1fb1c35f | 78 | if (info->clk_disabled) { |
498bcf31 KK |
79 | ret = clk_enable(info->rtc_clk); |
80 | if (ret) | |
81 | goto out; | |
82 | ||
83 | if (info->data->needs_src_clk) { | |
84 | ret = clk_enable(info->rtc_src_clk); | |
85 | if (ret) { | |
86 | clk_disable(info->rtc_clk); | |
87 | goto out; | |
88 | } | |
89 | } | |
1fb1c35f JS |
90 | info->clk_disabled = false; |
91 | } | |
498bcf31 KK |
92 | |
93 | out: | |
24e14554 | 94 | spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags); |
498bcf31 KK |
95 | |
96 | return ret; | |
24e14554 CC |
97 | } |
98 | ||
99 | static void s3c_rtc_disable_clk(struct s3c_rtc *info) | |
100 | { | |
101 | unsigned long irq_flags; | |
102 | ||
103 | spin_lock_irqsave(&info->alarm_clk_lock, irq_flags); | |
1fb1c35f JS |
104 | if (!info->clk_disabled) { |
105 | if (info->data->needs_src_clk) | |
106 | clk_disable(info->rtc_src_clk); | |
107 | clk_disable(info->rtc_clk); | |
108 | info->clk_disabled = true; | |
109 | } | |
19be09f5 | 110 | spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags); |
88cee8fd DK |
111 | } |
112 | ||
1add6781 | 113 | /* IRQ Handlers */ |
ae05c950 | 114 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 | 115 | { |
19be09f5 | 116 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 117 | |
ae05c950 CC |
118 | if (info->data->irq_handler) |
119 | info->data->irq_handler(info, S3C2410_INTP_TIC); | |
88cee8fd | 120 | |
1add6781 BD |
121 | return IRQ_HANDLED; |
122 | } | |
123 | ||
ae05c950 | 124 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 | 125 | { |
19be09f5 | 126 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 127 | |
ae05c950 CC |
128 | if (info->data->irq_handler) |
129 | info->data->irq_handler(info, S3C2410_INTP_ALM); | |
2f3478f6 | 130 | |
1add6781 BD |
131 | return IRQ_HANDLED; |
132 | } | |
133 | ||
134 | /* Update control registers */ | |
2ec38a03 | 135 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 | 136 | { |
19be09f5 | 137 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 | 138 | unsigned int tmp; |
498bcf31 | 139 | int ret; |
1add6781 | 140 | |
19be09f5 | 141 | dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled); |
1add6781 | 142 | |
498bcf31 KK |
143 | ret = s3c_rtc_enable_clk(info); |
144 | if (ret) | |
145 | return ret; | |
24e14554 | 146 | |
19be09f5 | 147 | tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 148 | |
2ec38a03 | 149 | if (enabled) |
1add6781 BD |
150 | tmp |= S3C2410_RTCALM_ALMEN; |
151 | ||
19be09f5 | 152 | writeb(tmp, info->base + S3C2410_RTCALM); |
2ec38a03 | 153 | |
24e14554 | 154 | s3c_rtc_disable_clk(info); |
88cee8fd | 155 | |
498bcf31 KK |
156 | if (enabled) { |
157 | ret = s3c_rtc_enable_clk(info); | |
158 | if (ret) | |
159 | return ret; | |
160 | } else { | |
1fb1c35f | 161 | s3c_rtc_disable_clk(info); |
498bcf31 | 162 | } |
1fb1c35f | 163 | |
2ec38a03 | 164 | return 0; |
1add6781 BD |
165 | } |
166 | ||
ae05c950 | 167 | /* Set RTC frequency */ |
19be09f5 | 168 | static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq) |
1add6781 | 169 | { |
498bcf31 KK |
170 | int ret; |
171 | ||
5d2a5037 JC |
172 | if (!is_power_of_2(freq)) |
173 | return -EINVAL; | |
174 | ||
498bcf31 KK |
175 | ret = s3c_rtc_enable_clk(info); |
176 | if (ret) | |
177 | return ret; | |
19be09f5 | 178 | spin_lock_irq(&info->pie_lock); |
1add6781 | 179 | |
ae05c950 CC |
180 | if (info->data->set_freq) |
181 | info->data->set_freq(info, freq); | |
25c1a246 | 182 | |
19be09f5 | 183 | spin_unlock_irq(&info->pie_lock); |
70c96dfa | 184 | s3c_rtc_disable_clk(info); |
773be7ee BD |
185 | |
186 | return 0; | |
1add6781 BD |
187 | } |
188 | ||
189 | /* Time read/write */ | |
1add6781 BD |
190 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) |
191 | { | |
19be09f5 | 192 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 | 193 | unsigned int have_retried = 0; |
498bcf31 | 194 | int ret; |
1add6781 | 195 | |
498bcf31 KK |
196 | ret = s3c_rtc_enable_clk(info); |
197 | if (ret) | |
198 | return ret; | |
df9e26d0 | 199 | |
fc1afe60 | 200 | retry_get_time: |
19be09f5 CC |
201 | rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN); |
202 | rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR); | |
203 | rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE); | |
204 | rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON); | |
205 | rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR); | |
206 | rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC); | |
1add6781 | 207 | |
48fc7f7e | 208 | /* the only way to work out whether the system was mid-update |
1add6781 BD |
209 | * when we read it is to check the second counter, and if it |
210 | * is zero, then we re-try the entire read | |
211 | */ | |
212 | ||
213 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
214 | have_retried = 1; | |
215 | goto retry_get_time; | |
216 | } | |
217 | ||
fe20ba70 AB |
218 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
219 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
220 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
221 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
222 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
223 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 | 224 | |
24e14554 CC |
225 | s3c_rtc_disable_clk(info); |
226 | ||
1add6781 | 227 | rtc_tm->tm_year += 100; |
4e8896cd | 228 | |
d4a48c2a | 229 | dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n", |
fc1afe60 KK |
230 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, |
231 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); | |
4e8896cd | 232 | |
1add6781 BD |
233 | rtc_tm->tm_mon -= 1; |
234 | ||
5b3ffddd | 235 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
236 | } |
237 | ||
238 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
239 | { | |
19be09f5 | 240 | struct s3c_rtc *info = dev_get_drvdata(dev); |
641741e0 | 241 | int year = tm->tm_year - 100; |
498bcf31 | 242 | int ret; |
9a654518 | 243 | |
d4a48c2a | 244 | dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n", |
fc1afe60 KK |
245 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
246 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
641741e0 BD |
247 | |
248 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 249 | |
641741e0 | 250 | if (year < 0 || year >= 100) { |
9a654518 | 251 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 252 | return -EINVAL; |
9a654518 BD |
253 | } |
254 | ||
498bcf31 KK |
255 | ret = s3c_rtc_enable_clk(info); |
256 | if (ret) | |
257 | return ret; | |
19be09f5 CC |
258 | |
259 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC); | |
260 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN); | |
261 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR); | |
262 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE); | |
263 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON); | |
264 | writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR); | |
265 | ||
24e14554 | 266 | s3c_rtc_disable_clk(info); |
1add6781 BD |
267 | |
268 | return 0; | |
269 | } | |
270 | ||
271 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
272 | { | |
19be09f5 | 273 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
274 | struct rtc_time *alm_tm = &alrm->time; |
275 | unsigned int alm_en; | |
498bcf31 | 276 | int ret; |
1add6781 | 277 | |
498bcf31 KK |
278 | ret = s3c_rtc_enable_clk(info); |
279 | if (ret) | |
280 | return ret; | |
df9e26d0 | 281 | |
19be09f5 CC |
282 | alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC); |
283 | alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN); | |
284 | alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR); | |
285 | alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON); | |
286 | alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE); | |
287 | alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR); | |
1add6781 | 288 | |
19be09f5 | 289 | alm_en = readb(info->base + S3C2410_RTCALM); |
1add6781 | 290 | |
24e14554 CC |
291 | s3c_rtc_disable_clk(info); |
292 | ||
a2db8dfc DB |
293 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
294 | ||
d4a48c2a | 295 | dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
fc1afe60 KK |
296 | alm_en, |
297 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, | |
298 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); | |
1add6781 | 299 | |
1add6781 | 300 | /* decode the alarm enable field */ |
1add6781 | 301 | if (alm_en & S3C2410_RTCALM_SECEN) |
fe20ba70 | 302 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 BD |
303 | |
304 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 305 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 BD |
306 | |
307 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 308 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 BD |
309 | |
310 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 311 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 BD |
312 | |
313 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 314 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 | 315 | alm_tm->tm_mon -= 1; |
1add6781 BD |
316 | } |
317 | ||
318 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 319 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 BD |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
324 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
325 | { | |
19be09f5 | 326 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
327 | struct rtc_time *tm = &alrm->time; |
328 | unsigned int alrm_en; | |
498bcf31 | 329 | int ret; |
1add6781 | 330 | |
d4a48c2a | 331 | dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
fc1afe60 KK |
332 | alrm->enabled, |
333 | 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, | |
334 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
1add6781 | 335 | |
498bcf31 KK |
336 | ret = s3c_rtc_enable_clk(info); |
337 | if (ret) | |
338 | return ret; | |
24e14554 | 339 | |
19be09f5 CC |
340 | alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
341 | writeb(0x00, info->base + S3C2410_RTCALM); | |
1add6781 BD |
342 | |
343 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
344 | alrm_en |= S3C2410_RTCALM_SECEN; | |
19be09f5 | 345 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC); |
1add6781 BD |
346 | } |
347 | ||
348 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
349 | alrm_en |= S3C2410_RTCALM_MINEN; | |
19be09f5 | 350 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN); |
1add6781 BD |
351 | } |
352 | ||
353 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
354 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
19be09f5 | 355 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR); |
1add6781 BD |
356 | } |
357 | ||
fb4ac3c1 KK |
358 | if (tm->tm_mon < 12 && tm->tm_mon >= 0) { |
359 | alrm_en |= S3C2410_RTCALM_MONEN; | |
360 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_ALMMON); | |
361 | } | |
362 | ||
363 | if (tm->tm_mday <= 31 && tm->tm_mday >= 1) { | |
364 | alrm_en |= S3C2410_RTCALM_DAYEN; | |
365 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_ALMDATE); | |
366 | } | |
367 | ||
d4a48c2a | 368 | dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); |
1add6781 | 369 | |
19be09f5 | 370 | writeb(alrm_en, info->base + S3C2410_RTCALM); |
1add6781 | 371 | |
24e14554 | 372 | s3c_rtc_disable_clk(info); |
1add6781 | 373 | |
24e14554 | 374 | s3c_rtc_setaie(dev, alrm->enabled); |
19be09f5 | 375 | |
1add6781 BD |
376 | return 0; |
377 | } | |
378 | ||
1add6781 BD |
379 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
380 | { | |
19be09f5 | 381 | struct s3c_rtc *info = dev_get_drvdata(dev); |
498bcf31 | 382 | int ret; |
1add6781 | 383 | |
498bcf31 KK |
384 | ret = s3c_rtc_enable_clk(info); |
385 | if (ret) | |
386 | return ret; | |
9f4123b7 | 387 | |
ae05c950 CC |
388 | if (info->data->enable_tick) |
389 | info->data->enable_tick(info, seq); | |
390 | ||
24e14554 | 391 | s3c_rtc_disable_clk(info); |
ae05c950 | 392 | |
1add6781 BD |
393 | return 0; |
394 | } | |
395 | ||
ff8371ac | 396 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
397 | .read_time = s3c_rtc_gettime, |
398 | .set_time = s3c_rtc_settime, | |
399 | .read_alarm = s3c_rtc_getalarm, | |
400 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
401 | .proc = s3c_rtc_proc, |
402 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
403 | }; |
404 | ||
ae05c950 | 405 | static void s3c24xx_rtc_enable(struct s3c_rtc *info) |
1add6781 | 406 | { |
d67288da | 407 | unsigned int con, tmp; |
1add6781 | 408 | |
d67288da | 409 | con = readw(info->base + S3C2410_RTCCON); |
ae05c950 CC |
410 | /* re-enable the device, and check it is ok */ |
411 | if ((con & S3C2410_RTCCON_RTCEN) == 0) { | |
412 | dev_info(info->dev, "rtc disabled, re-enabling\n"); | |
1add6781 | 413 | |
ae05c950 | 414 | tmp = readw(info->base + S3C2410_RTCCON); |
fc1afe60 | 415 | writew(tmp | S3C2410_RTCCON_RTCEN, info->base + S3C2410_RTCCON); |
ae05c950 | 416 | } |
1add6781 | 417 | |
ae05c950 CC |
418 | if (con & S3C2410_RTCCON_CNTSEL) { |
419 | dev_info(info->dev, "removing RTCCON_CNTSEL\n"); | |
1add6781 | 420 | |
ae05c950 CC |
421 | tmp = readw(info->base + S3C2410_RTCCON); |
422 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
fc1afe60 | 423 | info->base + S3C2410_RTCCON); |
ae05c950 | 424 | } |
1add6781 | 425 | |
ae05c950 CC |
426 | if (con & S3C2410_RTCCON_CLKRST) { |
427 | dev_info(info->dev, "removing RTCCON_CLKRST\n"); | |
1add6781 | 428 | |
ae05c950 CC |
429 | tmp = readw(info->base + S3C2410_RTCCON); |
430 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
fc1afe60 | 431 | info->base + S3C2410_RTCCON); |
1add6781 | 432 | } |
ae05c950 CC |
433 | } |
434 | ||
435 | static void s3c24xx_rtc_disable(struct s3c_rtc *info) | |
436 | { | |
437 | unsigned int con; | |
438 | ||
ae05c950 CC |
439 | con = readw(info->base + S3C2410_RTCCON); |
440 | con &= ~S3C2410_RTCCON_RTCEN; | |
441 | writew(con, info->base + S3C2410_RTCCON); | |
442 | ||
443 | con = readb(info->base + S3C2410_TICNT); | |
444 | con &= ~S3C2410_TICNT_ENABLE; | |
445 | writeb(con, info->base + S3C2410_TICNT); | |
ae05c950 CC |
446 | } |
447 | ||
448 | static void s3c6410_rtc_disable(struct s3c_rtc *info) | |
449 | { | |
450 | unsigned int con; | |
451 | ||
ae05c950 CC |
452 | con = readw(info->base + S3C2410_RTCCON); |
453 | con &= ~S3C64XX_RTCCON_TICEN; | |
454 | con &= ~S3C2410_RTCCON_RTCEN; | |
455 | writew(con, info->base + S3C2410_RTCCON); | |
1add6781 BD |
456 | } |
457 | ||
19be09f5 | 458 | static int s3c_rtc_remove(struct platform_device *pdev) |
1add6781 | 459 | { |
19be09f5 CC |
460 | struct s3c_rtc *info = platform_get_drvdata(pdev); |
461 | ||
462 | s3c_rtc_setaie(info->dev, 0); | |
1add6781 | 463 | |
7f23a936 JS |
464 | if (info->data->needs_src_clk) |
465 | clk_unprepare(info->rtc_src_clk); | |
19be09f5 | 466 | clk_unprepare(info->rtc_clk); |
e48add8c | 467 | |
1add6781 BD |
468 | return 0; |
469 | } | |
470 | ||
d2524caa HS |
471 | static const struct of_device_id s3c_rtc_dt_match[]; |
472 | ||
6b72086d | 473 | static const struct s3c_rtc_data *s3c_rtc_get_data(struct platform_device *pdev) |
d2524caa | 474 | { |
ae05c950 | 475 | const struct of_device_id *match; |
d67288da | 476 | |
ae05c950 | 477 | match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node); |
6b72086d | 478 | return match->data; |
d2524caa HS |
479 | } |
480 | ||
5a167f45 | 481 | static int s3c_rtc_probe(struct platform_device *pdev) |
1add6781 | 482 | { |
19be09f5 | 483 | struct s3c_rtc *info = NULL; |
e1df962e | 484 | struct rtc_time rtc_tm; |
1add6781 BD |
485 | struct resource *res; |
486 | int ret; | |
487 | ||
19be09f5 CC |
488 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
489 | if (!info) | |
490 | return -ENOMEM; | |
1add6781 BD |
491 | |
492 | /* find the IRQs */ | |
19be09f5 CC |
493 | info->irq_tick = platform_get_irq(pdev, 1); |
494 | if (info->irq_tick < 0) { | |
1add6781 | 495 | dev_err(&pdev->dev, "no irq for rtc tick\n"); |
19be09f5 | 496 | return info->irq_tick; |
1add6781 BD |
497 | } |
498 | ||
19be09f5 | 499 | info->dev = &pdev->dev; |
ae05c950 CC |
500 | info->data = s3c_rtc_get_data(pdev); |
501 | if (!info->data) { | |
502 | dev_err(&pdev->dev, "failed getting s3c_rtc_data\n"); | |
503 | return -EINVAL; | |
504 | } | |
19be09f5 CC |
505 | spin_lock_init(&info->pie_lock); |
506 | spin_lock_init(&info->alarm_clk_lock); | |
507 | ||
508 | platform_set_drvdata(pdev, info); | |
509 | ||
510 | info->irq_alarm = platform_get_irq(pdev, 0); | |
511 | if (info->irq_alarm < 0) { | |
1add6781 | 512 | dev_err(&pdev->dev, "no irq for alarm\n"); |
19be09f5 | 513 | return info->irq_alarm; |
1add6781 BD |
514 | } |
515 | ||
d4a48c2a | 516 | dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", |
fc1afe60 | 517 | info->irq_tick, info->irq_alarm); |
1add6781 BD |
518 | |
519 | /* get the memory region */ | |
1add6781 | 520 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
19be09f5 CC |
521 | info->base = devm_ioremap_resource(&pdev->dev, res); |
522 | if (IS_ERR(info->base)) | |
523 | return PTR_ERR(info->base); | |
1add6781 | 524 | |
19be09f5 CC |
525 | info->rtc_clk = devm_clk_get(&pdev->dev, "rtc"); |
526 | if (IS_ERR(info->rtc_clk)) { | |
ae6e00b4 JMC |
527 | ret = PTR_ERR(info->rtc_clk); |
528 | if (ret != -EPROBE_DEFER) | |
529 | dev_err(&pdev->dev, "failed to find rtc clock\n"); | |
530 | else | |
531 | dev_dbg(&pdev->dev, "probe deferred due to missing rtc clk\n"); | |
532 | return ret; | |
e48add8c | 533 | } |
9903f68a KK |
534 | ret = clk_prepare_enable(info->rtc_clk); |
535 | if (ret) | |
536 | return ret; | |
e48add8c | 537 | |
eaf3a659 MS |
538 | if (info->data->needs_src_clk) { |
539 | info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src"); | |
540 | if (IS_ERR(info->rtc_src_clk)) { | |
ae6e00b4 JMC |
541 | ret = PTR_ERR(info->rtc_src_clk); |
542 | if (ret != -EPROBE_DEFER) | |
543 | dev_err(&pdev->dev, | |
544 | "failed to find rtc source clock\n"); | |
545 | else | |
546 | dev_dbg(&pdev->dev, | |
547 | "probe deferred due to missing rtc src clk\n"); | |
8768e7b3 | 548 | goto err_src_clk; |
eaf3a659 | 549 | } |
9903f68a KK |
550 | ret = clk_prepare_enable(info->rtc_src_clk); |
551 | if (ret) | |
552 | goto err_src_clk; | |
df9e26d0 | 553 | } |
df9e26d0 | 554 | |
1add6781 | 555 | /* check to see if everything is setup correctly */ |
ae05c950 CC |
556 | if (info->data->enable) |
557 | info->data->enable(info); | |
1add6781 | 558 | |
d4a48c2a | 559 | dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", |
fc1afe60 | 560 | readw(info->base + S3C2410_RTCCON)); |
1add6781 | 561 | |
51b7616e YK |
562 | device_init_wakeup(&pdev->dev, 1); |
563 | ||
202fe4c2 | 564 | /* Check RTC Time */ |
492da68c | 565 | if (s3c_rtc_gettime(&pdev->dev, &rtc_tm)) { |
202fe4c2 KK |
566 | rtc_tm.tm_year = 100; |
567 | rtc_tm.tm_mon = 0; | |
568 | rtc_tm.tm_mday = 1; | |
569 | rtc_tm.tm_hour = 0; | |
570 | rtc_tm.tm_min = 0; | |
571 | rtc_tm.tm_sec = 0; | |
572 | ||
573 | s3c_rtc_settime(&pdev->dev, &rtc_tm); | |
574 | ||
575 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
576 | } | |
577 | ||
1add6781 | 578 | /* register RTC and exit */ |
19be09f5 | 579 | info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, |
fc1afe60 | 580 | THIS_MODULE); |
19be09f5 | 581 | if (IS_ERR(info->rtc)) { |
1add6781 | 582 | dev_err(&pdev->dev, "cannot attach rtc\n"); |
19be09f5 | 583 | ret = PTR_ERR(info->rtc); |
1add6781 BD |
584 | goto err_nortc; |
585 | } | |
586 | ||
19be09f5 | 587 | ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq, |
fc1afe60 | 588 | 0, "s3c2410-rtc alarm", info); |
19be09f5 CC |
589 | if (ret) { |
590 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret); | |
591 | goto err_nortc; | |
592 | } | |
eaa6e4dd | 593 | |
19be09f5 | 594 | ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq, |
fc1afe60 | 595 | 0, "s3c2410-rtc tick", info); |
19be09f5 CC |
596 | if (ret) { |
597 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret); | |
598 | goto err_nortc; | |
599 | } | |
051fe54e | 600 | |
ae05c950 CC |
601 | if (info->data->select_tick_clk) |
602 | info->data->select_tick_clk(info); | |
62d17601 | 603 | |
19be09f5 | 604 | s3c_rtc_setfreq(info, 1); |
62d17601 | 605 | |
1add6781 BD |
606 | return 0; |
607 | ||
fc1afe60 | 608 | err_nortc: |
ae05c950 CC |
609 | if (info->data->disable) |
610 | info->data->disable(info); | |
24e14554 CC |
611 | |
612 | if (info->data->needs_src_clk) | |
613 | clk_disable_unprepare(info->rtc_src_clk); | |
8768e7b3 | 614 | err_src_clk: |
19be09f5 | 615 | clk_disable_unprepare(info->rtc_clk); |
1add6781 | 616 | |
1add6781 BD |
617 | return ret; |
618 | } | |
619 | ||
32e445aa | 620 | #ifdef CONFIG_PM_SLEEP |
1add6781 | 621 | |
32e445aa | 622 | static int s3c_rtc_suspend(struct device *dev) |
1add6781 | 623 | { |
19be09f5 | 624 | struct s3c_rtc *info = dev_get_drvdata(dev); |
498bcf31 | 625 | int ret; |
32e445aa | 626 | |
498bcf31 KK |
627 | ret = s3c_rtc_enable_clk(info); |
628 | if (ret) | |
629 | return ret; | |
ae05c950 | 630 | |
1add6781 | 631 | /* save TICNT for anyone using periodic interrupts */ |
ae05c950 CC |
632 | if (info->data->save_tick_cnt) |
633 | info->data->save_tick_cnt(info); | |
634 | ||
635 | if (info->data->disable) | |
636 | info->data->disable(info); | |
f501ed52 | 637 | |
19be09f5 CC |
638 | if (device_may_wakeup(dev) && !info->wake_en) { |
639 | if (enable_irq_wake(info->irq_alarm) == 0) | |
640 | info->wake_en = true; | |
52cd4e5c | 641 | else |
32e445aa | 642 | dev_err(dev, "enable_irq_wake failed\n"); |
52cd4e5c | 643 | } |
ae05c950 | 644 | |
1add6781 BD |
645 | return 0; |
646 | } | |
647 | ||
32e445aa | 648 | static int s3c_rtc_resume(struct device *dev) |
1add6781 | 649 | { |
19be09f5 | 650 | struct s3c_rtc *info = dev_get_drvdata(dev); |
9f4123b7 | 651 | |
ae05c950 CC |
652 | if (info->data->enable) |
653 | info->data->enable(info); | |
654 | ||
655 | if (info->data->restore_tick_cnt) | |
656 | info->data->restore_tick_cnt(info); | |
f501ed52 | 657 | |
24e14554 CC |
658 | s3c_rtc_disable_clk(info); |
659 | ||
19be09f5 CC |
660 | if (device_may_wakeup(dev) && info->wake_en) { |
661 | disable_irq_wake(info->irq_alarm); | |
662 | info->wake_en = false; | |
52cd4e5c | 663 | } |
ae05c950 | 664 | |
1add6781 BD |
665 | return 0; |
666 | } | |
1add6781 | 667 | #endif |
32e445aa JH |
668 | static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); |
669 | ||
ae05c950 CC |
670 | static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask) |
671 | { | |
ae05c950 | 672 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
ae05c950 CC |
673 | } |
674 | ||
675 | static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask) | |
676 | { | |
ae05c950 CC |
677 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
678 | writeb(mask, info->base + S3C2410_INTP); | |
ae05c950 CC |
679 | } |
680 | ||
681 | static void s3c2410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
682 | { | |
683 | unsigned int tmp = 0; | |
684 | int val; | |
685 | ||
686 | tmp = readb(info->base + S3C2410_TICNT); | |
687 | tmp &= S3C2410_TICNT_ENABLE; | |
688 | ||
689 | val = (info->rtc->max_user_freq / freq) - 1; | |
690 | tmp |= val; | |
691 | ||
692 | writel(tmp, info->base + S3C2410_TICNT); | |
693 | } | |
694 | ||
695 | static void s3c2416_rtc_setfreq(struct s3c_rtc *info, int freq) | |
696 | { | |
697 | unsigned int tmp = 0; | |
698 | int val; | |
699 | ||
700 | tmp = readb(info->base + S3C2410_TICNT); | |
701 | tmp &= S3C2410_TICNT_ENABLE; | |
702 | ||
703 | val = (info->rtc->max_user_freq / freq) - 1; | |
704 | ||
705 | tmp |= S3C2443_TICNT_PART(val); | |
706 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
707 | ||
708 | writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2); | |
709 | ||
710 | writel(tmp, info->base + S3C2410_TICNT); | |
711 | } | |
712 | ||
713 | static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq) | |
714 | { | |
715 | unsigned int tmp = 0; | |
716 | int val; | |
717 | ||
718 | tmp = readb(info->base + S3C2410_TICNT); | |
719 | tmp &= S3C2410_TICNT_ENABLE; | |
720 | ||
721 | val = (info->rtc->max_user_freq / freq) - 1; | |
722 | ||
723 | tmp |= S3C2443_TICNT_PART(val); | |
724 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
725 | ||
726 | writel(tmp, info->base + S3C2410_TICNT); | |
727 | } | |
728 | ||
729 | static void s3c6410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
730 | { | |
731 | int val; | |
732 | ||
733 | val = (info->rtc->max_user_freq / freq) - 1; | |
734 | writel(val, info->base + S3C2410_TICNT); | |
735 | } | |
736 | ||
737 | static void s3c24xx_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
738 | { | |
739 | unsigned int ticnt; | |
740 | ||
741 | ticnt = readb(info->base + S3C2410_TICNT); | |
742 | ticnt &= S3C2410_TICNT_ENABLE; | |
743 | ||
744 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
745 | } | |
746 | ||
747 | static void s3c2416_rtc_select_tick_clk(struct s3c_rtc *info) | |
748 | { | |
749 | unsigned int con; | |
750 | ||
751 | con = readw(info->base + S3C2410_RTCCON); | |
752 | con |= S3C2443_RTCCON_TICSEL; | |
753 | writew(con, info->base + S3C2410_RTCCON); | |
754 | } | |
755 | ||
756 | static void s3c6410_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
757 | { | |
758 | unsigned int ticnt; | |
759 | ||
760 | ticnt = readw(info->base + S3C2410_RTCCON); | |
761 | ticnt &= S3C64XX_RTCCON_TICEN; | |
762 | ||
763 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
764 | } | |
765 | ||
766 | static void s3c24xx_rtc_save_tick_cnt(struct s3c_rtc *info) | |
767 | { | |
768 | info->ticnt_save = readb(info->base + S3C2410_TICNT); | |
769 | } | |
770 | ||
771 | static void s3c24xx_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
772 | { | |
773 | writeb(info->ticnt_save, info->base + S3C2410_TICNT); | |
774 | } | |
775 | ||
776 | static void s3c6410_rtc_save_tick_cnt(struct s3c_rtc *info) | |
777 | { | |
778 | info->ticnt_en_save = readw(info->base + S3C2410_RTCCON); | |
779 | info->ticnt_en_save &= S3C64XX_RTCCON_TICEN; | |
780 | info->ticnt_save = readl(info->base + S3C2410_TICNT); | |
781 | } | |
782 | ||
783 | static void s3c6410_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
784 | { | |
785 | unsigned int con; | |
786 | ||
787 | writel(info->ticnt_save, info->base + S3C2410_TICNT); | |
788 | if (info->ticnt_en_save) { | |
789 | con = readw(info->base + S3C2410_RTCCON); | |
fc1afe60 | 790 | writew(con | info->ticnt_en_save, info->base + S3C2410_RTCCON); |
ae05c950 CC |
791 | } |
792 | } | |
793 | ||
794 | static struct s3c_rtc_data const s3c2410_rtc_data = { | |
795 | .max_user_freq = 128, | |
796 | .irq_handler = s3c24xx_rtc_irq, | |
797 | .set_freq = s3c2410_rtc_setfreq, | |
798 | .enable_tick = s3c24xx_rtc_enable_tick, | |
799 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
800 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
801 | .enable = s3c24xx_rtc_enable, | |
802 | .disable = s3c24xx_rtc_disable, | |
803 | }; | |
804 | ||
805 | static struct s3c_rtc_data const s3c2416_rtc_data = { | |
806 | .max_user_freq = 32768, | |
807 | .irq_handler = s3c24xx_rtc_irq, | |
808 | .set_freq = s3c2416_rtc_setfreq, | |
809 | .enable_tick = s3c24xx_rtc_enable_tick, | |
810 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
811 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
812 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
813 | .enable = s3c24xx_rtc_enable, | |
814 | .disable = s3c24xx_rtc_disable, | |
815 | }; | |
816 | ||
817 | static struct s3c_rtc_data const s3c2443_rtc_data = { | |
818 | .max_user_freq = 32768, | |
819 | .irq_handler = s3c24xx_rtc_irq, | |
820 | .set_freq = s3c2443_rtc_setfreq, | |
821 | .enable_tick = s3c24xx_rtc_enable_tick, | |
822 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
823 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
824 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
825 | .enable = s3c24xx_rtc_enable, | |
826 | .disable = s3c24xx_rtc_disable, | |
827 | }; | |
828 | ||
829 | static struct s3c_rtc_data const s3c6410_rtc_data = { | |
830 | .max_user_freq = 32768, | |
8792f777 | 831 | .needs_src_clk = true, |
ae05c950 CC |
832 | .irq_handler = s3c6410_rtc_irq, |
833 | .set_freq = s3c6410_rtc_setfreq, | |
834 | .enable_tick = s3c6410_rtc_enable_tick, | |
835 | .save_tick_cnt = s3c6410_rtc_save_tick_cnt, | |
836 | .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt, | |
837 | .enable = s3c24xx_rtc_enable, | |
838 | .disable = s3c6410_rtc_disable, | |
c3cba928 TB |
839 | }; |
840 | ||
39ce4084 | 841 | static const struct of_device_id s3c_rtc_dt_match[] = { |
d2524caa | 842 | { |
cd1e6f9e | 843 | .compatible = "samsung,s3c2410-rtc", |
21df6fed | 844 | .data = &s3c2410_rtc_data, |
25c1a246 | 845 | }, { |
cd1e6f9e | 846 | .compatible = "samsung,s3c2416-rtc", |
21df6fed | 847 | .data = &s3c2416_rtc_data, |
25c1a246 | 848 | }, { |
cd1e6f9e | 849 | .compatible = "samsung,s3c2443-rtc", |
21df6fed | 850 | .data = &s3c2443_rtc_data, |
d2524caa | 851 | }, { |
cd1e6f9e | 852 | .compatible = "samsung,s3c6410-rtc", |
21df6fed | 853 | .data = &s3c6410_rtc_data, |
df9e26d0 CC |
854 | }, { |
855 | .compatible = "samsung,exynos3250-rtc", | |
21df6fed | 856 | .data = &s3c6410_rtc_data, |
d2524caa | 857 | }, |
ae05c950 | 858 | { /* sentinel */ }, |
39ce4084 TA |
859 | }; |
860 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
9f4123b7 MC |
861 | |
862 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 863 | .probe = s3c_rtc_probe, |
5a167f45 | 864 | .remove = s3c_rtc_remove, |
1add6781 | 865 | .driver = { |
9f4123b7 | 866 | .name = "s3c-rtc", |
32e445aa | 867 | .pm = &s3c_rtc_pm_ops, |
04a373fd | 868 | .of_match_table = of_match_ptr(s3c_rtc_dt_match), |
1add6781 BD |
869 | }, |
870 | }; | |
0c4eae66 | 871 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
872 | |
873 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
874 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
875 | MODULE_LICENSE("GPL"); | |
ad28a07b | 876 | MODULE_ALIAS("platform:s3c2410-rtc"); |