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Commit | Line | Data |
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1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
1add6781 | 28 | |
a09e64fb | 29 | #include <mach/hardware.h> |
1add6781 BD |
30 | #include <asm/uaccess.h> |
31 | #include <asm/io.h> | |
32 | #include <asm/irq.h> | |
e2cd00cf | 33 | #include <plat/regs-rtc.h> |
1add6781 | 34 | |
9f4123b7 MC |
35 | enum s3c_cpu_type { |
36 | TYPE_S3C2410, | |
37 | TYPE_S3C64XX, | |
38 | }; | |
39 | ||
1add6781 BD |
40 | /* I have yet to find an S3C implementation with more than one |
41 | * of these rtc blocks in */ | |
42 | ||
43 | static struct resource *s3c_rtc_mem; | |
44 | ||
e48add8c | 45 | static struct clk *rtc_clk; |
1add6781 BD |
46 | static void __iomem *s3c_rtc_base; |
47 | static int s3c_rtc_alarmno = NO_IRQ; | |
48 | static int s3c_rtc_tickno = NO_IRQ; | |
52cd4e5c | 49 | static bool wake_en; |
9f4123b7 | 50 | static enum s3c_cpu_type s3c_rtc_cpu_type; |
1add6781 BD |
51 | |
52 | static DEFINE_SPINLOCK(s3c_rtc_pie_lock); | |
1add6781 BD |
53 | |
54 | /* IRQ Handlers */ | |
55 | ||
7d12e780 | 56 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 BD |
57 | { |
58 | struct rtc_device *rdev = id; | |
59 | ||
ab6a2d70 | 60 | rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); |
2f3478f6 AD |
61 | |
62 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
63 | writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP); | |
64 | ||
1add6781 BD |
65 | return IRQ_HANDLED; |
66 | } | |
67 | ||
7d12e780 | 68 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 BD |
69 | { |
70 | struct rtc_device *rdev = id; | |
71 | ||
773be7ee | 72 | rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); |
2f3478f6 AD |
73 | |
74 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
75 | writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP); | |
76 | ||
1add6781 BD |
77 | return IRQ_HANDLED; |
78 | } | |
79 | ||
80 | /* Update control registers */ | |
2ec38a03 | 81 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 BD |
82 | { |
83 | unsigned int tmp; | |
84 | ||
2ec38a03 | 85 | pr_debug("%s: aie=%d\n", __func__, enabled); |
1add6781 | 86 | |
9a654518 | 87 | tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 88 | |
2ec38a03 | 89 | if (enabled) |
1add6781 BD |
90 | tmp |= S3C2410_RTCALM_ALMEN; |
91 | ||
9a654518 | 92 | writeb(tmp, s3c_rtc_base + S3C2410_RTCALM); |
2ec38a03 AL |
93 | |
94 | return 0; | |
1add6781 BD |
95 | } |
96 | ||
773be7ee | 97 | static int s3c_rtc_setfreq(struct device *dev, int freq) |
1add6781 | 98 | { |
9f4123b7 MC |
99 | struct platform_device *pdev = to_platform_device(dev); |
100 | struct rtc_device *rtc_dev = platform_get_drvdata(pdev); | |
101 | unsigned int tmp = 0; | |
1add6781 | 102 | |
5d2a5037 JC |
103 | if (!is_power_of_2(freq)) |
104 | return -EINVAL; | |
105 | ||
1add6781 | 106 | spin_lock_irq(&s3c_rtc_pie_lock); |
1add6781 | 107 | |
9f4123b7 MC |
108 | if (s3c_rtc_cpu_type == TYPE_S3C2410) { |
109 | tmp = readb(s3c_rtc_base + S3C2410_TICNT); | |
110 | tmp &= S3C2410_TICNT_ENABLE; | |
111 | } | |
112 | ||
113 | tmp |= (rtc_dev->max_user_freq / freq)-1; | |
1add6781 | 114 | |
2f3478f6 | 115 | writel(tmp, s3c_rtc_base + S3C2410_TICNT); |
1add6781 | 116 | spin_unlock_irq(&s3c_rtc_pie_lock); |
773be7ee BD |
117 | |
118 | return 0; | |
1add6781 BD |
119 | } |
120 | ||
121 | /* Time read/write */ | |
122 | ||
123 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
124 | { | |
125 | unsigned int have_retried = 0; | |
9a654518 | 126 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
127 | |
128 | retry_get_time: | |
9a654518 BD |
129 | rtc_tm->tm_min = readb(base + S3C2410_RTCMIN); |
130 | rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR); | |
131 | rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE); | |
132 | rtc_tm->tm_mon = readb(base + S3C2410_RTCMON); | |
133 | rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR); | |
134 | rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC); | |
1add6781 BD |
135 | |
136 | /* the only way to work out wether the system was mid-update | |
137 | * when we read it is to check the second counter, and if it | |
138 | * is zero, then we re-try the entire read | |
139 | */ | |
140 | ||
141 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
142 | have_retried = 1; | |
143 | goto retry_get_time; | |
144 | } | |
145 | ||
30ffc40c KK |
146 | pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n", |
147 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, | |
1add6781 BD |
148 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); |
149 | ||
fe20ba70 AB |
150 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
151 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
152 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
153 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
154 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
155 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 BD |
156 | |
157 | rtc_tm->tm_year += 100; | |
158 | rtc_tm->tm_mon -= 1; | |
159 | ||
5b3ffddd | 160 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
161 | } |
162 | ||
163 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
164 | { | |
9a654518 | 165 | void __iomem *base = s3c_rtc_base; |
641741e0 | 166 | int year = tm->tm_year - 100; |
9a654518 | 167 | |
30ffc40c KK |
168 | pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n", |
169 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, | |
641741e0 BD |
170 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
171 | ||
172 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 173 | |
641741e0 | 174 | if (year < 0 || year >= 100) { |
9a654518 | 175 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 176 | return -EINVAL; |
9a654518 BD |
177 | } |
178 | ||
fe20ba70 AB |
179 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC); |
180 | writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN); | |
181 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR); | |
182 | writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE); | |
183 | writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON); | |
184 | writeb(bin2bcd(year), base + S3C2410_RTCYEAR); | |
1add6781 BD |
185 | |
186 | return 0; | |
187 | } | |
188 | ||
189 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
190 | { | |
191 | struct rtc_time *alm_tm = &alrm->time; | |
9a654518 | 192 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
193 | unsigned int alm_en; |
194 | ||
9a654518 BD |
195 | alm_tm->tm_sec = readb(base + S3C2410_ALMSEC); |
196 | alm_tm->tm_min = readb(base + S3C2410_ALMMIN); | |
197 | alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR); | |
198 | alm_tm->tm_mon = readb(base + S3C2410_ALMMON); | |
199 | alm_tm->tm_mday = readb(base + S3C2410_ALMDATE); | |
200 | alm_tm->tm_year = readb(base + S3C2410_ALMYEAR); | |
1add6781 | 201 | |
9a654518 | 202 | alm_en = readb(base + S3C2410_RTCALM); |
1add6781 | 203 | |
a2db8dfc DB |
204 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
205 | ||
30ffc40c | 206 | pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 207 | alm_en, |
30ffc40c | 208 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, |
1add6781 BD |
209 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); |
210 | ||
211 | ||
212 | /* decode the alarm enable field */ | |
213 | ||
214 | if (alm_en & S3C2410_RTCALM_SECEN) | |
fe20ba70 | 215 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 | 216 | else |
dd061d1a | 217 | alm_tm->tm_sec = -1; |
1add6781 BD |
218 | |
219 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 220 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 | 221 | else |
dd061d1a | 222 | alm_tm->tm_min = -1; |
1add6781 BD |
223 | |
224 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 225 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 | 226 | else |
dd061d1a | 227 | alm_tm->tm_hour = -1; |
1add6781 BD |
228 | |
229 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 230 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 | 231 | else |
dd061d1a | 232 | alm_tm->tm_mday = -1; |
1add6781 BD |
233 | |
234 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 235 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 BD |
236 | alm_tm->tm_mon -= 1; |
237 | } else { | |
dd061d1a | 238 | alm_tm->tm_mon = -1; |
1add6781 BD |
239 | } |
240 | ||
241 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 242 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 | 243 | else |
dd061d1a | 244 | alm_tm->tm_year = -1; |
1add6781 BD |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
249 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
250 | { | |
251 | struct rtc_time *tm = &alrm->time; | |
9a654518 | 252 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
253 | unsigned int alrm_en; |
254 | ||
30ffc40c | 255 | pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 256 | alrm->enabled, |
30ffc40c KK |
257 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
258 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
1add6781 BD |
259 | |
260 | ||
9a654518 BD |
261 | alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
262 | writeb(0x00, base + S3C2410_RTCALM); | |
1add6781 BD |
263 | |
264 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
265 | alrm_en |= S3C2410_RTCALM_SECEN; | |
fe20ba70 | 266 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC); |
1add6781 BD |
267 | } |
268 | ||
269 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
270 | alrm_en |= S3C2410_RTCALM_MINEN; | |
fe20ba70 | 271 | writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN); |
1add6781 BD |
272 | } |
273 | ||
274 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
275 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
fe20ba70 | 276 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR); |
1add6781 BD |
277 | } |
278 | ||
279 | pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en); | |
280 | ||
9a654518 | 281 | writeb(alrm_en, base + S3C2410_RTCALM); |
1add6781 | 282 | |
2ec38a03 | 283 | s3c_rtc_setaie(dev, alrm->enabled); |
1add6781 | 284 | |
1add6781 BD |
285 | return 0; |
286 | } | |
287 | ||
1add6781 BD |
288 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
289 | { | |
9f4123b7 | 290 | unsigned int ticnt; |
1add6781 | 291 | |
9f4123b7 | 292 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 293 | ticnt = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
294 | ticnt &= S3C64XX_RTCCON_TICEN; |
295 | } else { | |
296 | ticnt = readb(s3c_rtc_base + S3C2410_TICNT); | |
297 | ticnt &= S3C2410_TICNT_ENABLE; | |
298 | } | |
299 | ||
300 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
1add6781 BD |
301 | return 0; |
302 | } | |
303 | ||
304 | static int s3c_rtc_open(struct device *dev) | |
305 | { | |
306 | struct platform_device *pdev = to_platform_device(dev); | |
307 | struct rtc_device *rtc_dev = platform_get_drvdata(pdev); | |
308 | int ret; | |
309 | ||
310 | ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq, | |
38515e90 | 311 | IRQF_DISABLED, "s3c2410-rtc alarm", rtc_dev); |
1add6781 BD |
312 | |
313 | if (ret) { | |
314 | dev_err(dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret); | |
315 | return ret; | |
316 | } | |
317 | ||
318 | ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq, | |
38515e90 | 319 | IRQF_DISABLED, "s3c2410-rtc tick", rtc_dev); |
1add6781 BD |
320 | |
321 | if (ret) { | |
322 | dev_err(dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret); | |
323 | goto tick_err; | |
324 | } | |
325 | ||
326 | return ret; | |
327 | ||
328 | tick_err: | |
329 | free_irq(s3c_rtc_alarmno, rtc_dev); | |
330 | return ret; | |
331 | } | |
332 | ||
333 | static void s3c_rtc_release(struct device *dev) | |
334 | { | |
335 | struct platform_device *pdev = to_platform_device(dev); | |
336 | struct rtc_device *rtc_dev = platform_get_drvdata(pdev); | |
337 | ||
338 | /* do not clear AIE here, it may be needed for wake */ | |
339 | ||
1add6781 BD |
340 | free_irq(s3c_rtc_alarmno, rtc_dev); |
341 | free_irq(s3c_rtc_tickno, rtc_dev); | |
342 | } | |
343 | ||
ff8371ac | 344 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
345 | .open = s3c_rtc_open, |
346 | .release = s3c_rtc_release, | |
1add6781 BD |
347 | .read_time = s3c_rtc_gettime, |
348 | .set_time = s3c_rtc_settime, | |
349 | .read_alarm = s3c_rtc_getalarm, | |
350 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
351 | .proc = s3c_rtc_proc, |
352 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
353 | }; |
354 | ||
355 | static void s3c_rtc_enable(struct platform_device *pdev, int en) | |
356 | { | |
9a654518 | 357 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
358 | unsigned int tmp; |
359 | ||
360 | if (s3c_rtc_base == NULL) | |
361 | return; | |
362 | ||
363 | if (!en) { | |
f61ae671 | 364 | tmp = readw(base + S3C2410_RTCCON); |
9f4123b7 MC |
365 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) |
366 | tmp &= ~S3C64XX_RTCCON_TICEN; | |
367 | tmp &= ~S3C2410_RTCCON_RTCEN; | |
f61ae671 | 368 | writew(tmp, base + S3C2410_RTCCON); |
9f4123b7 MC |
369 | |
370 | if (s3c_rtc_cpu_type == TYPE_S3C2410) { | |
371 | tmp = readb(base + S3C2410_TICNT); | |
372 | tmp &= ~S3C2410_TICNT_ENABLE; | |
373 | writeb(tmp, base + S3C2410_TICNT); | |
374 | } | |
1add6781 BD |
375 | } else { |
376 | /* re-enable the device, and check it is ok */ | |
377 | ||
f61ae671 | 378 | if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) { |
1add6781 BD |
379 | dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); |
380 | ||
f61ae671 CY |
381 | tmp = readw(base + S3C2410_RTCCON); |
382 | writew(tmp | S3C2410_RTCCON_RTCEN, | |
383 | base + S3C2410_RTCCON); | |
1add6781 BD |
384 | } |
385 | ||
f61ae671 | 386 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) { |
1add6781 BD |
387 | dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); |
388 | ||
f61ae671 CY |
389 | tmp = readw(base + S3C2410_RTCCON); |
390 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
391 | base + S3C2410_RTCCON); | |
1add6781 BD |
392 | } |
393 | ||
f61ae671 | 394 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) { |
1add6781 BD |
395 | dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); |
396 | ||
f61ae671 CY |
397 | tmp = readw(base + S3C2410_RTCCON); |
398 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
399 | base + S3C2410_RTCCON); | |
1add6781 BD |
400 | } |
401 | } | |
402 | } | |
403 | ||
4cd0c5c4 | 404 | static int __devexit s3c_rtc_remove(struct platform_device *dev) |
1add6781 BD |
405 | { |
406 | struct rtc_device *rtc = platform_get_drvdata(dev); | |
407 | ||
408 | platform_set_drvdata(dev, NULL); | |
409 | rtc_device_unregister(rtc); | |
410 | ||
2ec38a03 | 411 | s3c_rtc_setaie(&dev->dev, 0); |
1add6781 | 412 | |
e48add8c AD |
413 | clk_disable(rtc_clk); |
414 | clk_put(rtc_clk); | |
415 | rtc_clk = NULL; | |
416 | ||
1add6781 BD |
417 | iounmap(s3c_rtc_base); |
418 | release_resource(s3c_rtc_mem); | |
419 | kfree(s3c_rtc_mem); | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
4cd0c5c4 | 424 | static int __devinit s3c_rtc_probe(struct platform_device *pdev) |
1add6781 BD |
425 | { |
426 | struct rtc_device *rtc; | |
e1df962e | 427 | struct rtc_time rtc_tm; |
1add6781 BD |
428 | struct resource *res; |
429 | int ret; | |
430 | ||
2a4e2b87 | 431 | pr_debug("%s: probe=%p\n", __func__, pdev); |
1add6781 BD |
432 | |
433 | /* find the IRQs */ | |
434 | ||
435 | s3c_rtc_tickno = platform_get_irq(pdev, 1); | |
436 | if (s3c_rtc_tickno < 0) { | |
437 | dev_err(&pdev->dev, "no irq for rtc tick\n"); | |
438 | return -ENOENT; | |
439 | } | |
440 | ||
441 | s3c_rtc_alarmno = platform_get_irq(pdev, 0); | |
442 | if (s3c_rtc_alarmno < 0) { | |
443 | dev_err(&pdev->dev, "no irq for alarm\n"); | |
444 | return -ENOENT; | |
445 | } | |
446 | ||
447 | pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n", | |
448 | s3c_rtc_tickno, s3c_rtc_alarmno); | |
449 | ||
450 | /* get the memory region */ | |
451 | ||
452 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
453 | if (res == NULL) { | |
454 | dev_err(&pdev->dev, "failed to get memory region resource\n"); | |
455 | return -ENOENT; | |
456 | } | |
457 | ||
458 | s3c_rtc_mem = request_mem_region(res->start, | |
9a654518 BD |
459 | res->end-res->start+1, |
460 | pdev->name); | |
1add6781 BD |
461 | |
462 | if (s3c_rtc_mem == NULL) { | |
463 | dev_err(&pdev->dev, "failed to reserve memory region\n"); | |
464 | ret = -ENOENT; | |
465 | goto err_nores; | |
466 | } | |
467 | ||
468 | s3c_rtc_base = ioremap(res->start, res->end - res->start + 1); | |
469 | if (s3c_rtc_base == NULL) { | |
470 | dev_err(&pdev->dev, "failed ioremap()\n"); | |
471 | ret = -EINVAL; | |
472 | goto err_nomap; | |
473 | } | |
474 | ||
e48add8c AD |
475 | rtc_clk = clk_get(&pdev->dev, "rtc"); |
476 | if (IS_ERR(rtc_clk)) { | |
477 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
478 | ret = PTR_ERR(rtc_clk); | |
479 | rtc_clk = NULL; | |
480 | goto err_clk; | |
481 | } | |
482 | ||
483 | clk_enable(rtc_clk); | |
484 | ||
1add6781 BD |
485 | /* check to see if everything is setup correctly */ |
486 | ||
487 | s3c_rtc_enable(pdev, 1); | |
488 | ||
f61ae671 CY |
489 | pr_debug("s3c2410_rtc: RTCCON=%02x\n", |
490 | readw(s3c_rtc_base + S3C2410_RTCCON)); | |
1add6781 | 491 | |
51b7616e YK |
492 | device_init_wakeup(&pdev->dev, 1); |
493 | ||
1add6781 BD |
494 | /* register RTC and exit */ |
495 | ||
496 | rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops, | |
497 | THIS_MODULE); | |
498 | ||
499 | if (IS_ERR(rtc)) { | |
500 | dev_err(&pdev->dev, "cannot attach rtc\n"); | |
501 | ret = PTR_ERR(rtc); | |
502 | goto err_nortc; | |
503 | } | |
504 | ||
eaa6e4dd MC |
505 | s3c_rtc_cpu_type = platform_get_device_id(pdev)->driver_data; |
506 | ||
051fe54e TK |
507 | /* Check RTC Time */ |
508 | ||
e1df962e | 509 | s3c_rtc_gettime(NULL, &rtc_tm); |
051fe54e | 510 | |
e1df962e CY |
511 | if (rtc_valid_tm(&rtc_tm)) { |
512 | rtc_tm.tm_year = 100; | |
513 | rtc_tm.tm_mon = 0; | |
514 | rtc_tm.tm_mday = 1; | |
515 | rtc_tm.tm_hour = 0; | |
516 | rtc_tm.tm_min = 0; | |
517 | rtc_tm.tm_sec = 0; | |
518 | ||
519 | s3c_rtc_settime(NULL, &rtc_tm); | |
520 | ||
521 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
051fe54e TK |
522 | } |
523 | ||
9f4123b7 MC |
524 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) |
525 | rtc->max_user_freq = 32768; | |
526 | else | |
527 | rtc->max_user_freq = 128; | |
528 | ||
1add6781 | 529 | platform_set_drvdata(pdev, rtc); |
e893de59 MC |
530 | |
531 | s3c_rtc_setfreq(&pdev->dev, 1); | |
532 | ||
1add6781 BD |
533 | return 0; |
534 | ||
535 | err_nortc: | |
536 | s3c_rtc_enable(pdev, 0); | |
e48add8c AD |
537 | clk_disable(rtc_clk); |
538 | clk_put(rtc_clk); | |
539 | ||
540 | err_clk: | |
1add6781 BD |
541 | iounmap(s3c_rtc_base); |
542 | ||
543 | err_nomap: | |
544 | release_resource(s3c_rtc_mem); | |
545 | ||
546 | err_nores: | |
547 | return ret; | |
548 | } | |
549 | ||
550 | #ifdef CONFIG_PM | |
551 | ||
552 | /* RTC Power management control */ | |
553 | ||
9f4123b7 | 554 | static int ticnt_save, ticnt_en_save; |
1add6781 BD |
555 | |
556 | static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state) | |
557 | { | |
1add6781 | 558 | /* save TICNT for anyone using periodic interrupts */ |
9a654518 | 559 | ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT); |
9f4123b7 | 560 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 561 | ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
562 | ticnt_en_save &= S3C64XX_RTCCON_TICEN; |
563 | } | |
1add6781 | 564 | s3c_rtc_enable(pdev, 0); |
f501ed52 | 565 | |
52cd4e5c BD |
566 | if (device_may_wakeup(&pdev->dev) && !wake_en) { |
567 | if (enable_irq_wake(s3c_rtc_alarmno) == 0) | |
568 | wake_en = true; | |
569 | else | |
570 | dev_err(&pdev->dev, "enable_irq_wake failed\n"); | |
571 | } | |
f501ed52 | 572 | |
1add6781 BD |
573 | return 0; |
574 | } | |
575 | ||
576 | static int s3c_rtc_resume(struct platform_device *pdev) | |
577 | { | |
9f4123b7 MC |
578 | unsigned int tmp; |
579 | ||
1add6781 | 580 | s3c_rtc_enable(pdev, 1); |
9a654518 | 581 | writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT); |
9f4123b7 | 582 | if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) { |
f61ae671 CY |
583 | tmp = readw(s3c_rtc_base + S3C2410_RTCCON); |
584 | writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON); | |
9f4123b7 | 585 | } |
f501ed52 | 586 | |
52cd4e5c | 587 | if (device_may_wakeup(&pdev->dev) && wake_en) { |
f501ed52 | 588 | disable_irq_wake(s3c_rtc_alarmno); |
52cd4e5c BD |
589 | wake_en = false; |
590 | } | |
f501ed52 | 591 | |
1add6781 BD |
592 | return 0; |
593 | } | |
594 | #else | |
595 | #define s3c_rtc_suspend NULL | |
596 | #define s3c_rtc_resume NULL | |
597 | #endif | |
598 | ||
9f4123b7 MC |
599 | static struct platform_device_id s3c_rtc_driver_ids[] = { |
600 | { | |
601 | .name = "s3c2410-rtc", | |
602 | .driver_data = TYPE_S3C2410, | |
603 | }, { | |
604 | .name = "s3c64xx-rtc", | |
605 | .driver_data = TYPE_S3C64XX, | |
606 | }, | |
607 | { } | |
608 | }; | |
609 | ||
610 | MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids); | |
611 | ||
612 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 613 | .probe = s3c_rtc_probe, |
4cd0c5c4 | 614 | .remove = __devexit_p(s3c_rtc_remove), |
1add6781 BD |
615 | .suspend = s3c_rtc_suspend, |
616 | .resume = s3c_rtc_resume, | |
9f4123b7 | 617 | .id_table = s3c_rtc_driver_ids, |
1add6781 | 618 | .driver = { |
9f4123b7 | 619 | .name = "s3c-rtc", |
1add6781 BD |
620 | .owner = THIS_MODULE, |
621 | }, | |
622 | }; | |
623 | ||
624 | static char __initdata banner[] = "S3C24XX RTC, (c) 2004,2006 Simtec Electronics\n"; | |
625 | ||
626 | static int __init s3c_rtc_init(void) | |
627 | { | |
628 | printk(banner); | |
9f4123b7 | 629 | return platform_driver_register(&s3c_rtc_driver); |
1add6781 BD |
630 | } |
631 | ||
632 | static void __exit s3c_rtc_exit(void) | |
633 | { | |
9f4123b7 | 634 | platform_driver_unregister(&s3c_rtc_driver); |
1add6781 BD |
635 | } |
636 | ||
637 | module_init(s3c_rtc_init); | |
638 | module_exit(s3c_rtc_exit); | |
639 | ||
640 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
641 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
642 | MODULE_LICENSE("GPL"); | |
ad28a07b | 643 | MODULE_ALIAS("platform:s3c2410-rtc"); |