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Commit | Line | Data |
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1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
39ce4084 | 28 | #include <linux/of.h> |
dbd9acbe SK |
29 | #include <linux/uaccess.h> |
30 | #include <linux/io.h> | |
1add6781 | 31 | |
1add6781 | 32 | #include <asm/irq.h> |
b9d7c5d3 | 33 | #include "rtc-s3c.h" |
1add6781 | 34 | |
19be09f5 CC |
35 | struct s3c_rtc { |
36 | struct device *dev; | |
37 | struct rtc_device *rtc; | |
38 | ||
39 | void __iomem *base; | |
40 | struct clk *rtc_clk; | |
df9e26d0 | 41 | struct clk *rtc_src_clk; |
1fb1c35f | 42 | bool clk_disabled; |
19be09f5 | 43 | |
ae05c950 | 44 | struct s3c_rtc_data *data; |
1add6781 | 45 | |
19be09f5 CC |
46 | int irq_alarm; |
47 | int irq_tick; | |
1add6781 | 48 | |
19be09f5 CC |
49 | spinlock_t pie_lock; |
50 | spinlock_t alarm_clk_lock; | |
1add6781 | 51 | |
19be09f5 CC |
52 | int ticnt_save, ticnt_en_save; |
53 | bool wake_en; | |
54 | }; | |
55 | ||
ae05c950 CC |
56 | struct s3c_rtc_data { |
57 | int max_user_freq; | |
df9e26d0 | 58 | bool needs_src_clk; |
ae05c950 CC |
59 | |
60 | void (*irq_handler) (struct s3c_rtc *info, int mask); | |
61 | void (*set_freq) (struct s3c_rtc *info, int freq); | |
62 | void (*enable_tick) (struct s3c_rtc *info, struct seq_file *seq); | |
63 | void (*select_tick_clk) (struct s3c_rtc *info); | |
64 | void (*save_tick_cnt) (struct s3c_rtc *info); | |
65 | void (*restore_tick_cnt) (struct s3c_rtc *info); | |
66 | void (*enable) (struct s3c_rtc *info); | |
67 | void (*disable) (struct s3c_rtc *info); | |
68 | }; | |
69 | ||
24e14554 | 70 | static void s3c_rtc_enable_clk(struct s3c_rtc *info) |
88cee8fd | 71 | { |
88cee8fd DK |
72 | unsigned long irq_flags; |
73 | ||
19be09f5 | 74 | spin_lock_irqsave(&info->alarm_clk_lock, irq_flags); |
1fb1c35f JS |
75 | if (info->clk_disabled) { |
76 | clk_enable(info->rtc_clk); | |
77 | if (info->data->needs_src_clk) | |
78 | clk_enable(info->rtc_src_clk); | |
79 | info->clk_disabled = false; | |
80 | } | |
24e14554 CC |
81 | spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags); |
82 | } | |
83 | ||
84 | static void s3c_rtc_disable_clk(struct s3c_rtc *info) | |
85 | { | |
86 | unsigned long irq_flags; | |
87 | ||
88 | spin_lock_irqsave(&info->alarm_clk_lock, irq_flags); | |
1fb1c35f JS |
89 | if (!info->clk_disabled) { |
90 | if (info->data->needs_src_clk) | |
91 | clk_disable(info->rtc_src_clk); | |
92 | clk_disable(info->rtc_clk); | |
93 | info->clk_disabled = true; | |
94 | } | |
19be09f5 | 95 | spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags); |
88cee8fd DK |
96 | } |
97 | ||
1add6781 | 98 | /* IRQ Handlers */ |
ae05c950 | 99 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 | 100 | { |
19be09f5 | 101 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 102 | |
ae05c950 CC |
103 | if (info->data->irq_handler) |
104 | info->data->irq_handler(info, S3C2410_INTP_TIC); | |
88cee8fd | 105 | |
1add6781 BD |
106 | return IRQ_HANDLED; |
107 | } | |
108 | ||
ae05c950 | 109 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 | 110 | { |
19be09f5 | 111 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 112 | |
ae05c950 CC |
113 | if (info->data->irq_handler) |
114 | info->data->irq_handler(info, S3C2410_INTP_ALM); | |
2f3478f6 | 115 | |
1add6781 BD |
116 | return IRQ_HANDLED; |
117 | } | |
118 | ||
119 | /* Update control registers */ | |
2ec38a03 | 120 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 | 121 | { |
19be09f5 | 122 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
123 | unsigned int tmp; |
124 | ||
19be09f5 | 125 | dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled); |
1add6781 | 126 | |
24e14554 CC |
127 | s3c_rtc_enable_clk(info); |
128 | ||
19be09f5 | 129 | tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 130 | |
2ec38a03 | 131 | if (enabled) |
1add6781 BD |
132 | tmp |= S3C2410_RTCALM_ALMEN; |
133 | ||
19be09f5 | 134 | writeb(tmp, info->base + S3C2410_RTCALM); |
2ec38a03 | 135 | |
24e14554 | 136 | s3c_rtc_disable_clk(info); |
88cee8fd | 137 | |
1fb1c35f JS |
138 | if (enabled) |
139 | s3c_rtc_enable_clk(info); | |
140 | else | |
141 | s3c_rtc_disable_clk(info); | |
142 | ||
2ec38a03 | 143 | return 0; |
1add6781 BD |
144 | } |
145 | ||
ae05c950 | 146 | /* Set RTC frequency */ |
19be09f5 | 147 | static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq) |
1add6781 | 148 | { |
5d2a5037 JC |
149 | if (!is_power_of_2(freq)) |
150 | return -EINVAL; | |
151 | ||
19be09f5 | 152 | spin_lock_irq(&info->pie_lock); |
1add6781 | 153 | |
ae05c950 CC |
154 | if (info->data->set_freq) |
155 | info->data->set_freq(info, freq); | |
25c1a246 | 156 | |
19be09f5 | 157 | spin_unlock_irq(&info->pie_lock); |
773be7ee BD |
158 | |
159 | return 0; | |
1add6781 BD |
160 | } |
161 | ||
162 | /* Time read/write */ | |
1add6781 BD |
163 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) |
164 | { | |
19be09f5 | 165 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
166 | unsigned int have_retried = 0; |
167 | ||
24e14554 | 168 | s3c_rtc_enable_clk(info); |
df9e26d0 | 169 | |
1add6781 | 170 | retry_get_time: |
19be09f5 CC |
171 | rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN); |
172 | rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR); | |
173 | rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE); | |
174 | rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON); | |
175 | rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR); | |
176 | rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC); | |
1add6781 | 177 | |
48fc7f7e | 178 | /* the only way to work out whether the system was mid-update |
1add6781 BD |
179 | * when we read it is to check the second counter, and if it |
180 | * is zero, then we re-try the entire read | |
181 | */ | |
182 | ||
183 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
184 | have_retried = 1; | |
185 | goto retry_get_time; | |
186 | } | |
187 | ||
fe20ba70 AB |
188 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
189 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
190 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
191 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
192 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
193 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 | 194 | |
24e14554 CC |
195 | s3c_rtc_disable_clk(info); |
196 | ||
1add6781 | 197 | rtc_tm->tm_year += 100; |
4e8896cd | 198 | |
d4a48c2a | 199 | dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n", |
4e8896cd MH |
200 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, |
201 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); | |
202 | ||
1add6781 BD |
203 | rtc_tm->tm_mon -= 1; |
204 | ||
5b3ffddd | 205 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
206 | } |
207 | ||
208 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
209 | { | |
19be09f5 | 210 | struct s3c_rtc *info = dev_get_drvdata(dev); |
641741e0 | 211 | int year = tm->tm_year - 100; |
9a654518 | 212 | |
d4a48c2a | 213 | dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n", |
30ffc40c | 214 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
641741e0 BD |
215 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
216 | ||
217 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 218 | |
641741e0 | 219 | if (year < 0 || year >= 100) { |
9a654518 | 220 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 221 | return -EINVAL; |
9a654518 BD |
222 | } |
223 | ||
24e14554 | 224 | s3c_rtc_enable_clk(info); |
19be09f5 CC |
225 | |
226 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC); | |
227 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN); | |
228 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR); | |
229 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE); | |
230 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON); | |
231 | writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR); | |
232 | ||
24e14554 | 233 | s3c_rtc_disable_clk(info); |
1add6781 BD |
234 | |
235 | return 0; | |
236 | } | |
237 | ||
238 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
239 | { | |
19be09f5 | 240 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
241 | struct rtc_time *alm_tm = &alrm->time; |
242 | unsigned int alm_en; | |
243 | ||
24e14554 | 244 | s3c_rtc_enable_clk(info); |
df9e26d0 | 245 | |
19be09f5 CC |
246 | alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC); |
247 | alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN); | |
248 | alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR); | |
249 | alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON); | |
250 | alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE); | |
251 | alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR); | |
1add6781 | 252 | |
19be09f5 | 253 | alm_en = readb(info->base + S3C2410_RTCALM); |
1add6781 | 254 | |
24e14554 CC |
255 | s3c_rtc_disable_clk(info); |
256 | ||
a2db8dfc DB |
257 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
258 | ||
d4a48c2a | 259 | dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 260 | alm_en, |
30ffc40c | 261 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, |
1add6781 BD |
262 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); |
263 | ||
1add6781 | 264 | /* decode the alarm enable field */ |
1add6781 | 265 | if (alm_en & S3C2410_RTCALM_SECEN) |
fe20ba70 | 266 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 | 267 | else |
dd061d1a | 268 | alm_tm->tm_sec = -1; |
1add6781 BD |
269 | |
270 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 271 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 | 272 | else |
dd061d1a | 273 | alm_tm->tm_min = -1; |
1add6781 BD |
274 | |
275 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 276 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 | 277 | else |
dd061d1a | 278 | alm_tm->tm_hour = -1; |
1add6781 BD |
279 | |
280 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 281 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 | 282 | else |
dd061d1a | 283 | alm_tm->tm_mday = -1; |
1add6781 BD |
284 | |
285 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 286 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 BD |
287 | alm_tm->tm_mon -= 1; |
288 | } else { | |
dd061d1a | 289 | alm_tm->tm_mon = -1; |
1add6781 BD |
290 | } |
291 | ||
292 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 293 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 | 294 | else |
dd061d1a | 295 | alm_tm->tm_year = -1; |
1add6781 BD |
296 | |
297 | return 0; | |
298 | } | |
299 | ||
300 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
301 | { | |
19be09f5 | 302 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
303 | struct rtc_time *tm = &alrm->time; |
304 | unsigned int alrm_en; | |
fb4ac3c1 | 305 | int year = tm->tm_year - 100; |
1add6781 | 306 | |
d4a48c2a | 307 | dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 308 | alrm->enabled, |
4e8896cd | 309 | 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, |
30ffc40c | 310 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
1add6781 | 311 | |
24e14554 CC |
312 | s3c_rtc_enable_clk(info); |
313 | ||
19be09f5 CC |
314 | alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
315 | writeb(0x00, info->base + S3C2410_RTCALM); | |
1add6781 BD |
316 | |
317 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
318 | alrm_en |= S3C2410_RTCALM_SECEN; | |
19be09f5 | 319 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC); |
1add6781 BD |
320 | } |
321 | ||
322 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
323 | alrm_en |= S3C2410_RTCALM_MINEN; | |
19be09f5 | 324 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN); |
1add6781 BD |
325 | } |
326 | ||
327 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
328 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
19be09f5 | 329 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR); |
1add6781 BD |
330 | } |
331 | ||
fb4ac3c1 KK |
332 | if (year < 100 && year >= 0) { |
333 | alrm_en |= S3C2410_RTCALM_YEAREN; | |
334 | writeb(bin2bcd(year), info->base + S3C2410_ALMYEAR); | |
335 | } | |
336 | ||
337 | if (tm->tm_mon < 12 && tm->tm_mon >= 0) { | |
338 | alrm_en |= S3C2410_RTCALM_MONEN; | |
339 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_ALMMON); | |
340 | } | |
341 | ||
342 | if (tm->tm_mday <= 31 && tm->tm_mday >= 1) { | |
343 | alrm_en |= S3C2410_RTCALM_DAYEN; | |
344 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_ALMDATE); | |
345 | } | |
346 | ||
d4a48c2a | 347 | dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); |
1add6781 | 348 | |
19be09f5 | 349 | writeb(alrm_en, info->base + S3C2410_RTCALM); |
1add6781 | 350 | |
24e14554 | 351 | s3c_rtc_disable_clk(info); |
1add6781 | 352 | |
24e14554 | 353 | s3c_rtc_setaie(dev, alrm->enabled); |
19be09f5 | 354 | |
1add6781 BD |
355 | return 0; |
356 | } | |
357 | ||
1add6781 BD |
358 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
359 | { | |
19be09f5 | 360 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 | 361 | |
24e14554 | 362 | s3c_rtc_enable_clk(info); |
9f4123b7 | 363 | |
ae05c950 CC |
364 | if (info->data->enable_tick) |
365 | info->data->enable_tick(info, seq); | |
366 | ||
24e14554 | 367 | s3c_rtc_disable_clk(info); |
ae05c950 | 368 | |
1add6781 BD |
369 | return 0; |
370 | } | |
371 | ||
ff8371ac | 372 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
373 | .read_time = s3c_rtc_gettime, |
374 | .set_time = s3c_rtc_settime, | |
375 | .read_alarm = s3c_rtc_getalarm, | |
376 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
377 | .proc = s3c_rtc_proc, |
378 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
379 | }; |
380 | ||
ae05c950 | 381 | static void s3c24xx_rtc_enable(struct s3c_rtc *info) |
1add6781 | 382 | { |
d67288da | 383 | unsigned int con, tmp; |
1add6781 | 384 | |
d67288da | 385 | con = readw(info->base + S3C2410_RTCCON); |
ae05c950 CC |
386 | /* re-enable the device, and check it is ok */ |
387 | if ((con & S3C2410_RTCCON_RTCEN) == 0) { | |
388 | dev_info(info->dev, "rtc disabled, re-enabling\n"); | |
1add6781 | 389 | |
ae05c950 CC |
390 | tmp = readw(info->base + S3C2410_RTCCON); |
391 | writew(tmp | S3C2410_RTCCON_RTCEN, | |
392 | info->base + S3C2410_RTCCON); | |
393 | } | |
1add6781 | 394 | |
ae05c950 CC |
395 | if (con & S3C2410_RTCCON_CNTSEL) { |
396 | dev_info(info->dev, "removing RTCCON_CNTSEL\n"); | |
1add6781 | 397 | |
ae05c950 CC |
398 | tmp = readw(info->base + S3C2410_RTCCON); |
399 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
400 | info->base + S3C2410_RTCCON); | |
401 | } | |
1add6781 | 402 | |
ae05c950 CC |
403 | if (con & S3C2410_RTCCON_CLKRST) { |
404 | dev_info(info->dev, "removing RTCCON_CLKRST\n"); | |
1add6781 | 405 | |
ae05c950 CC |
406 | tmp = readw(info->base + S3C2410_RTCCON); |
407 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
408 | info->base + S3C2410_RTCCON); | |
1add6781 | 409 | } |
ae05c950 CC |
410 | } |
411 | ||
412 | static void s3c24xx_rtc_disable(struct s3c_rtc *info) | |
413 | { | |
414 | unsigned int con; | |
415 | ||
ae05c950 CC |
416 | con = readw(info->base + S3C2410_RTCCON); |
417 | con &= ~S3C2410_RTCCON_RTCEN; | |
418 | writew(con, info->base + S3C2410_RTCCON); | |
419 | ||
420 | con = readb(info->base + S3C2410_TICNT); | |
421 | con &= ~S3C2410_TICNT_ENABLE; | |
422 | writeb(con, info->base + S3C2410_TICNT); | |
ae05c950 CC |
423 | } |
424 | ||
425 | static void s3c6410_rtc_disable(struct s3c_rtc *info) | |
426 | { | |
427 | unsigned int con; | |
428 | ||
ae05c950 CC |
429 | con = readw(info->base + S3C2410_RTCCON); |
430 | con &= ~S3C64XX_RTCCON_TICEN; | |
431 | con &= ~S3C2410_RTCCON_RTCEN; | |
432 | writew(con, info->base + S3C2410_RTCCON); | |
1add6781 BD |
433 | } |
434 | ||
19be09f5 | 435 | static int s3c_rtc_remove(struct platform_device *pdev) |
1add6781 | 436 | { |
19be09f5 CC |
437 | struct s3c_rtc *info = platform_get_drvdata(pdev); |
438 | ||
439 | s3c_rtc_setaie(info->dev, 0); | |
1add6781 | 440 | |
7f23a936 JS |
441 | if (info->data->needs_src_clk) |
442 | clk_unprepare(info->rtc_src_clk); | |
19be09f5 | 443 | clk_unprepare(info->rtc_clk); |
e48add8c | 444 | |
1add6781 BD |
445 | return 0; |
446 | } | |
447 | ||
d2524caa HS |
448 | static const struct of_device_id s3c_rtc_dt_match[]; |
449 | ||
ae05c950 | 450 | static struct s3c_rtc_data *s3c_rtc_get_data(struct platform_device *pdev) |
d2524caa | 451 | { |
ae05c950 | 452 | const struct of_device_id *match; |
d67288da | 453 | |
ae05c950 CC |
454 | match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node); |
455 | return (struct s3c_rtc_data *)match->data; | |
d2524caa HS |
456 | } |
457 | ||
5a167f45 | 458 | static int s3c_rtc_probe(struct platform_device *pdev) |
1add6781 | 459 | { |
19be09f5 | 460 | struct s3c_rtc *info = NULL; |
e1df962e | 461 | struct rtc_time rtc_tm; |
1add6781 BD |
462 | struct resource *res; |
463 | int ret; | |
464 | ||
19be09f5 CC |
465 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
466 | if (!info) | |
467 | return -ENOMEM; | |
1add6781 BD |
468 | |
469 | /* find the IRQs */ | |
19be09f5 CC |
470 | info->irq_tick = platform_get_irq(pdev, 1); |
471 | if (info->irq_tick < 0) { | |
1add6781 | 472 | dev_err(&pdev->dev, "no irq for rtc tick\n"); |
19be09f5 | 473 | return info->irq_tick; |
1add6781 BD |
474 | } |
475 | ||
19be09f5 | 476 | info->dev = &pdev->dev; |
ae05c950 CC |
477 | info->data = s3c_rtc_get_data(pdev); |
478 | if (!info->data) { | |
479 | dev_err(&pdev->dev, "failed getting s3c_rtc_data\n"); | |
480 | return -EINVAL; | |
481 | } | |
19be09f5 CC |
482 | spin_lock_init(&info->pie_lock); |
483 | spin_lock_init(&info->alarm_clk_lock); | |
484 | ||
485 | platform_set_drvdata(pdev, info); | |
486 | ||
487 | info->irq_alarm = platform_get_irq(pdev, 0); | |
488 | if (info->irq_alarm < 0) { | |
1add6781 | 489 | dev_err(&pdev->dev, "no irq for alarm\n"); |
19be09f5 | 490 | return info->irq_alarm; |
1add6781 BD |
491 | } |
492 | ||
d4a48c2a | 493 | dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", |
19be09f5 | 494 | info->irq_tick, info->irq_alarm); |
1add6781 BD |
495 | |
496 | /* get the memory region */ | |
1add6781 | 497 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
19be09f5 CC |
498 | info->base = devm_ioremap_resource(&pdev->dev, res); |
499 | if (IS_ERR(info->base)) | |
500 | return PTR_ERR(info->base); | |
1add6781 | 501 | |
19be09f5 CC |
502 | info->rtc_clk = devm_clk_get(&pdev->dev, "rtc"); |
503 | if (IS_ERR(info->rtc_clk)) { | |
ae6e00b4 JMC |
504 | ret = PTR_ERR(info->rtc_clk); |
505 | if (ret != -EPROBE_DEFER) | |
506 | dev_err(&pdev->dev, "failed to find rtc clock\n"); | |
507 | else | |
508 | dev_dbg(&pdev->dev, "probe deferred due to missing rtc clk\n"); | |
509 | return ret; | |
e48add8c | 510 | } |
19be09f5 | 511 | clk_prepare_enable(info->rtc_clk); |
e48add8c | 512 | |
eaf3a659 MS |
513 | if (info->data->needs_src_clk) { |
514 | info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src"); | |
515 | if (IS_ERR(info->rtc_src_clk)) { | |
ae6e00b4 JMC |
516 | ret = PTR_ERR(info->rtc_src_clk); |
517 | if (ret != -EPROBE_DEFER) | |
518 | dev_err(&pdev->dev, | |
519 | "failed to find rtc source clock\n"); | |
520 | else | |
521 | dev_dbg(&pdev->dev, | |
522 | "probe deferred due to missing rtc src clk\n"); | |
7f23a936 | 523 | clk_disable_unprepare(info->rtc_clk); |
ae6e00b4 | 524 | return ret; |
eaf3a659 MS |
525 | } |
526 | clk_prepare_enable(info->rtc_src_clk); | |
df9e26d0 | 527 | } |
df9e26d0 | 528 | |
1add6781 | 529 | /* check to see if everything is setup correctly */ |
ae05c950 CC |
530 | if (info->data->enable) |
531 | info->data->enable(info); | |
1add6781 | 532 | |
d4a48c2a | 533 | dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", |
19be09f5 | 534 | readw(info->base + S3C2410_RTCCON)); |
1add6781 | 535 | |
51b7616e YK |
536 | device_init_wakeup(&pdev->dev, 1); |
537 | ||
202fe4c2 | 538 | /* Check RTC Time */ |
492da68c | 539 | if (s3c_rtc_gettime(&pdev->dev, &rtc_tm)) { |
202fe4c2 KK |
540 | rtc_tm.tm_year = 100; |
541 | rtc_tm.tm_mon = 0; | |
542 | rtc_tm.tm_mday = 1; | |
543 | rtc_tm.tm_hour = 0; | |
544 | rtc_tm.tm_min = 0; | |
545 | rtc_tm.tm_sec = 0; | |
546 | ||
547 | s3c_rtc_settime(&pdev->dev, &rtc_tm); | |
548 | ||
549 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
550 | } | |
551 | ||
1add6781 | 552 | /* register RTC and exit */ |
19be09f5 | 553 | info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, |
1add6781 | 554 | THIS_MODULE); |
19be09f5 | 555 | if (IS_ERR(info->rtc)) { |
1add6781 | 556 | dev_err(&pdev->dev, "cannot attach rtc\n"); |
19be09f5 | 557 | ret = PTR_ERR(info->rtc); |
1add6781 BD |
558 | goto err_nortc; |
559 | } | |
560 | ||
19be09f5 CC |
561 | ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq, |
562 | 0, "s3c2410-rtc alarm", info); | |
563 | if (ret) { | |
564 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret); | |
565 | goto err_nortc; | |
566 | } | |
eaa6e4dd | 567 | |
19be09f5 CC |
568 | ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq, |
569 | 0, "s3c2410-rtc tick", info); | |
570 | if (ret) { | |
571 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret); | |
572 | goto err_nortc; | |
573 | } | |
051fe54e | 574 | |
ae05c950 CC |
575 | if (info->data->select_tick_clk) |
576 | info->data->select_tick_clk(info); | |
62d17601 | 577 | |
19be09f5 | 578 | s3c_rtc_setfreq(info, 1); |
62d17601 | 579 | |
24e14554 | 580 | s3c_rtc_disable_clk(info); |
cefe4fbb | 581 | |
1add6781 BD |
582 | return 0; |
583 | ||
584 | err_nortc: | |
ae05c950 CC |
585 | if (info->data->disable) |
586 | info->data->disable(info); | |
24e14554 CC |
587 | |
588 | if (info->data->needs_src_clk) | |
589 | clk_disable_unprepare(info->rtc_src_clk); | |
19be09f5 | 590 | clk_disable_unprepare(info->rtc_clk); |
1add6781 | 591 | |
1add6781 BD |
592 | return ret; |
593 | } | |
594 | ||
32e445aa | 595 | #ifdef CONFIG_PM_SLEEP |
1add6781 | 596 | |
32e445aa | 597 | static int s3c_rtc_suspend(struct device *dev) |
1add6781 | 598 | { |
19be09f5 | 599 | struct s3c_rtc *info = dev_get_drvdata(dev); |
32e445aa | 600 | |
24e14554 | 601 | s3c_rtc_enable_clk(info); |
ae05c950 | 602 | |
1add6781 | 603 | /* save TICNT for anyone using periodic interrupts */ |
ae05c950 CC |
604 | if (info->data->save_tick_cnt) |
605 | info->data->save_tick_cnt(info); | |
606 | ||
607 | if (info->data->disable) | |
608 | info->data->disable(info); | |
f501ed52 | 609 | |
19be09f5 CC |
610 | if (device_may_wakeup(dev) && !info->wake_en) { |
611 | if (enable_irq_wake(info->irq_alarm) == 0) | |
612 | info->wake_en = true; | |
52cd4e5c | 613 | else |
32e445aa | 614 | dev_err(dev, "enable_irq_wake failed\n"); |
52cd4e5c | 615 | } |
ae05c950 | 616 | |
1add6781 BD |
617 | return 0; |
618 | } | |
619 | ||
32e445aa | 620 | static int s3c_rtc_resume(struct device *dev) |
1add6781 | 621 | { |
19be09f5 | 622 | struct s3c_rtc *info = dev_get_drvdata(dev); |
9f4123b7 | 623 | |
ae05c950 CC |
624 | if (info->data->enable) |
625 | info->data->enable(info); | |
626 | ||
627 | if (info->data->restore_tick_cnt) | |
628 | info->data->restore_tick_cnt(info); | |
f501ed52 | 629 | |
24e14554 CC |
630 | s3c_rtc_disable_clk(info); |
631 | ||
19be09f5 CC |
632 | if (device_may_wakeup(dev) && info->wake_en) { |
633 | disable_irq_wake(info->irq_alarm); | |
634 | info->wake_en = false; | |
52cd4e5c | 635 | } |
ae05c950 | 636 | |
1add6781 BD |
637 | return 0; |
638 | } | |
1add6781 | 639 | #endif |
32e445aa JH |
640 | static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); |
641 | ||
ae05c950 CC |
642 | static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask) |
643 | { | |
ae05c950 | 644 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
ae05c950 CC |
645 | } |
646 | ||
647 | static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask) | |
648 | { | |
ae05c950 CC |
649 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
650 | writeb(mask, info->base + S3C2410_INTP); | |
ae05c950 CC |
651 | } |
652 | ||
653 | static void s3c2410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
654 | { | |
655 | unsigned int tmp = 0; | |
656 | int val; | |
657 | ||
658 | tmp = readb(info->base + S3C2410_TICNT); | |
659 | tmp &= S3C2410_TICNT_ENABLE; | |
660 | ||
661 | val = (info->rtc->max_user_freq / freq) - 1; | |
662 | tmp |= val; | |
663 | ||
664 | writel(tmp, info->base + S3C2410_TICNT); | |
665 | } | |
666 | ||
667 | static void s3c2416_rtc_setfreq(struct s3c_rtc *info, int freq) | |
668 | { | |
669 | unsigned int tmp = 0; | |
670 | int val; | |
671 | ||
672 | tmp = readb(info->base + S3C2410_TICNT); | |
673 | tmp &= S3C2410_TICNT_ENABLE; | |
674 | ||
675 | val = (info->rtc->max_user_freq / freq) - 1; | |
676 | ||
677 | tmp |= S3C2443_TICNT_PART(val); | |
678 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
679 | ||
680 | writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2); | |
681 | ||
682 | writel(tmp, info->base + S3C2410_TICNT); | |
683 | } | |
684 | ||
685 | static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq) | |
686 | { | |
687 | unsigned int tmp = 0; | |
688 | int val; | |
689 | ||
690 | tmp = readb(info->base + S3C2410_TICNT); | |
691 | tmp &= S3C2410_TICNT_ENABLE; | |
692 | ||
693 | val = (info->rtc->max_user_freq / freq) - 1; | |
694 | ||
695 | tmp |= S3C2443_TICNT_PART(val); | |
696 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
697 | ||
698 | writel(tmp, info->base + S3C2410_TICNT); | |
699 | } | |
700 | ||
701 | static void s3c6410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
702 | { | |
703 | int val; | |
704 | ||
705 | val = (info->rtc->max_user_freq / freq) - 1; | |
706 | writel(val, info->base + S3C2410_TICNT); | |
707 | } | |
708 | ||
709 | static void s3c24xx_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
710 | { | |
711 | unsigned int ticnt; | |
712 | ||
713 | ticnt = readb(info->base + S3C2410_TICNT); | |
714 | ticnt &= S3C2410_TICNT_ENABLE; | |
715 | ||
716 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
717 | } | |
718 | ||
719 | static void s3c2416_rtc_select_tick_clk(struct s3c_rtc *info) | |
720 | { | |
721 | unsigned int con; | |
722 | ||
723 | con = readw(info->base + S3C2410_RTCCON); | |
724 | con |= S3C2443_RTCCON_TICSEL; | |
725 | writew(con, info->base + S3C2410_RTCCON); | |
726 | } | |
727 | ||
728 | static void s3c6410_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
729 | { | |
730 | unsigned int ticnt; | |
731 | ||
732 | ticnt = readw(info->base + S3C2410_RTCCON); | |
733 | ticnt &= S3C64XX_RTCCON_TICEN; | |
734 | ||
735 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
736 | } | |
737 | ||
738 | static void s3c24xx_rtc_save_tick_cnt(struct s3c_rtc *info) | |
739 | { | |
740 | info->ticnt_save = readb(info->base + S3C2410_TICNT); | |
741 | } | |
742 | ||
743 | static void s3c24xx_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
744 | { | |
745 | writeb(info->ticnt_save, info->base + S3C2410_TICNT); | |
746 | } | |
747 | ||
748 | static void s3c6410_rtc_save_tick_cnt(struct s3c_rtc *info) | |
749 | { | |
750 | info->ticnt_en_save = readw(info->base + S3C2410_RTCCON); | |
751 | info->ticnt_en_save &= S3C64XX_RTCCON_TICEN; | |
752 | info->ticnt_save = readl(info->base + S3C2410_TICNT); | |
753 | } | |
754 | ||
755 | static void s3c6410_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
756 | { | |
757 | unsigned int con; | |
758 | ||
759 | writel(info->ticnt_save, info->base + S3C2410_TICNT); | |
760 | if (info->ticnt_en_save) { | |
761 | con = readw(info->base + S3C2410_RTCCON); | |
762 | writew(con | info->ticnt_en_save, | |
763 | info->base + S3C2410_RTCCON); | |
764 | } | |
765 | } | |
766 | ||
767 | static struct s3c_rtc_data const s3c2410_rtc_data = { | |
768 | .max_user_freq = 128, | |
769 | .irq_handler = s3c24xx_rtc_irq, | |
770 | .set_freq = s3c2410_rtc_setfreq, | |
771 | .enable_tick = s3c24xx_rtc_enable_tick, | |
772 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
773 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
774 | .enable = s3c24xx_rtc_enable, | |
775 | .disable = s3c24xx_rtc_disable, | |
776 | }; | |
777 | ||
778 | static struct s3c_rtc_data const s3c2416_rtc_data = { | |
779 | .max_user_freq = 32768, | |
780 | .irq_handler = s3c24xx_rtc_irq, | |
781 | .set_freq = s3c2416_rtc_setfreq, | |
782 | .enable_tick = s3c24xx_rtc_enable_tick, | |
783 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
784 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
785 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
786 | .enable = s3c24xx_rtc_enable, | |
787 | .disable = s3c24xx_rtc_disable, | |
788 | }; | |
789 | ||
790 | static struct s3c_rtc_data const s3c2443_rtc_data = { | |
791 | .max_user_freq = 32768, | |
792 | .irq_handler = s3c24xx_rtc_irq, | |
793 | .set_freq = s3c2443_rtc_setfreq, | |
794 | .enable_tick = s3c24xx_rtc_enable_tick, | |
795 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
796 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
797 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
798 | .enable = s3c24xx_rtc_enable, | |
799 | .disable = s3c24xx_rtc_disable, | |
800 | }; | |
801 | ||
802 | static struct s3c_rtc_data const s3c6410_rtc_data = { | |
803 | .max_user_freq = 32768, | |
8792f777 | 804 | .needs_src_clk = true, |
ae05c950 CC |
805 | .irq_handler = s3c6410_rtc_irq, |
806 | .set_freq = s3c6410_rtc_setfreq, | |
807 | .enable_tick = s3c6410_rtc_enable_tick, | |
808 | .save_tick_cnt = s3c6410_rtc_save_tick_cnt, | |
809 | .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt, | |
810 | .enable = s3c24xx_rtc_enable, | |
811 | .disable = s3c6410_rtc_disable, | |
c3cba928 TB |
812 | }; |
813 | ||
39ce4084 | 814 | static const struct of_device_id s3c_rtc_dt_match[] = { |
d2524caa | 815 | { |
cd1e6f9e | 816 | .compatible = "samsung,s3c2410-rtc", |
ae05c950 | 817 | .data = (void *)&s3c2410_rtc_data, |
25c1a246 | 818 | }, { |
cd1e6f9e | 819 | .compatible = "samsung,s3c2416-rtc", |
ae05c950 | 820 | .data = (void *)&s3c2416_rtc_data, |
25c1a246 | 821 | }, { |
cd1e6f9e | 822 | .compatible = "samsung,s3c2443-rtc", |
ae05c950 | 823 | .data = (void *)&s3c2443_rtc_data, |
d2524caa | 824 | }, { |
cd1e6f9e | 825 | .compatible = "samsung,s3c6410-rtc", |
ae05c950 | 826 | .data = (void *)&s3c6410_rtc_data, |
df9e26d0 CC |
827 | }, { |
828 | .compatible = "samsung,exynos3250-rtc", | |
a42e6eae | 829 | .data = (void *)&s3c6410_rtc_data, |
d2524caa | 830 | }, |
ae05c950 | 831 | { /* sentinel */ }, |
39ce4084 TA |
832 | }; |
833 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
9f4123b7 MC |
834 | |
835 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 836 | .probe = s3c_rtc_probe, |
5a167f45 | 837 | .remove = s3c_rtc_remove, |
1add6781 | 838 | .driver = { |
9f4123b7 | 839 | .name = "s3c-rtc", |
32e445aa | 840 | .pm = &s3c_rtc_pm_ops, |
04a373fd | 841 | .of_match_table = of_match_ptr(s3c_rtc_dt_match), |
1add6781 BD |
842 | }, |
843 | }; | |
0c4eae66 | 844 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
845 | |
846 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
847 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
848 | MODULE_LICENSE("GPL"); | |
ad28a07b | 849 | MODULE_ALIAS("platform:s3c2410-rtc"); |