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26dcc12c KK |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd | |
4 | // http://www.samsung.com | |
5 | // | |
6 | // Copyright (C) 2013 Google, Inc | |
5bccae6e | 7 | |
a737e835 JP |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
9 | ||
5bccae6e SK |
10 | #include <linux/module.h> |
11 | #include <linux/i2c.h> | |
5bccae6e | 12 | #include <linux/bcd.h> |
5bccae6e SK |
13 | #include <linux/regmap.h> |
14 | #include <linux/rtc.h> | |
5bccae6e SK |
15 | #include <linux/platform_device.h> |
16 | #include <linux/mfd/samsung/core.h> | |
17 | #include <linux/mfd/samsung/irq.h> | |
18 | #include <linux/mfd/samsung/rtc.h> | |
0c5deb1e | 19 | #include <linux/mfd/samsung/s2mps14.h> |
5bccae6e | 20 | |
d73238d4 KK |
21 | /* |
22 | * Maximum number of retries for checking changes in UDR field | |
602cb5bb | 23 | * of S5M_RTC_UDR_CON register (to limit possible endless loop). |
d73238d4 KK |
24 | * |
25 | * After writing to RTC registers (setting time or alarm) read the UDR field | |
602cb5bb | 26 | * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have |
d73238d4 KK |
27 | * been transferred. |
28 | */ | |
29 | #define UDR_READ_RETRY_CNT 5 | |
30 | ||
4a681243 GS |
31 | enum { |
32 | RTC_SEC = 0, | |
33 | RTC_MIN, | |
34 | RTC_HOUR, | |
35 | RTC_WEEKDAY, | |
36 | RTC_DATE, | |
37 | RTC_MONTH, | |
38 | RTC_YEAR1, | |
39 | RTC_YEAR2, | |
756d5282 GS |
40 | /* Make sure this is always the last enum name. */ |
41 | RTC_MAX_NUM_TIME_REGS | |
4a681243 GS |
42 | }; |
43 | ||
8ae83b6f KK |
44 | /* |
45 | * Registers used by the driver which are different between chipsets. | |
46 | * | |
47 | * Operations like read time and write alarm/time require updating | |
48 | * specific fields in UDR register. These fields usually are auto-cleared | |
49 | * (with some exceptions). | |
50 | * | |
51 | * Table of operations per device: | |
52 | * | |
53 | * Device | Write time | Read time | Write alarm | |
54 | * ================================================= | |
55 | * S5M8767 | UDR + TIME | | UDR | |
56 | * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR | |
57 | * S2MPS13 | WUDR | RUDR | WUDR + AUDR | |
58 | * S2MPS15 | WUDR | RUDR | AUDR | |
59 | */ | |
f8b23bbd KK |
60 | struct s5m_rtc_reg_config { |
61 | /* Number of registers used for setting time/alarm0/alarm1 */ | |
62 | unsigned int regs_count; | |
63 | /* First register for time, seconds */ | |
64 | unsigned int time; | |
65 | /* RTC control register */ | |
66 | unsigned int ctrl; | |
67 | /* First register for alarm 0, seconds */ | |
68 | unsigned int alarm0; | |
69 | /* First register for alarm 1, seconds */ | |
70 | unsigned int alarm1; | |
f8b23bbd KK |
71 | /* |
72 | * Register for update flag (UDR). Typically setting UDR field to 1 | |
73 | * will enable update of time or alarm register. Then it will be | |
74 | * auto-cleared after successful update. | |
75 | */ | |
a83a793a | 76 | unsigned int udr_update; |
67a6025a KK |
77 | /* Auto-cleared mask in UDR field for writing time and alarm */ |
78 | unsigned int autoclear_udr_mask; | |
8ae83b6f KK |
79 | /* |
80 | * Masks in UDR field for time and alarm operations. | |
81 | * The read time mask can be 0. Rest should not. | |
82 | */ | |
83 | unsigned int read_time_udr_mask; | |
84 | unsigned int write_time_udr_mask; | |
85 | unsigned int write_alarm_udr_mask; | |
f8b23bbd KK |
86 | }; |
87 | ||
88 | /* Register map for S5M8763 and S5M8767 */ | |
89 | static const struct s5m_rtc_reg_config s5m_rtc_regs = { | |
90 | .regs_count = 8, | |
91 | .time = S5M_RTC_SEC, | |
92 | .ctrl = S5M_ALARM1_CONF, | |
93 | .alarm0 = S5M_ALARM0_SEC, | |
94 | .alarm1 = S5M_ALARM1_SEC, | |
a83a793a | 95 | .udr_update = S5M_RTC_UDR_CON, |
67a6025a | 96 | .autoclear_udr_mask = S5M_RTC_UDR_MASK, |
8ae83b6f KK |
97 | .read_time_udr_mask = 0, /* Not needed */ |
98 | .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK, | |
99 | .write_alarm_udr_mask = S5M_RTC_UDR_MASK, | |
100 | }; | |
101 | ||
102 | /* Register map for S2MPS13 */ | |
103 | static const struct s5m_rtc_reg_config s2mps13_rtc_regs = { | |
104 | .regs_count = 7, | |
105 | .time = S2MPS_RTC_SEC, | |
106 | .ctrl = S2MPS_RTC_CTRL, | |
107 | .alarm0 = S2MPS_ALARM0_SEC, | |
108 | .alarm1 = S2MPS_ALARM1_SEC, | |
109 | .udr_update = S2MPS_RTC_UDR_CON, | |
110 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, | |
111 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, | |
112 | .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, | |
113 | .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK, | |
114 | }; | |
115 | ||
116 | /* Register map for S2MPS11/14 */ | |
117 | static const struct s5m_rtc_reg_config s2mps14_rtc_regs = { | |
118 | .regs_count = 7, | |
119 | .time = S2MPS_RTC_SEC, | |
120 | .ctrl = S2MPS_RTC_CTRL, | |
121 | .alarm0 = S2MPS_ALARM0_SEC, | |
122 | .alarm1 = S2MPS_ALARM1_SEC, | |
123 | .udr_update = S2MPS_RTC_UDR_CON, | |
124 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, | |
125 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, | |
126 | .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, | |
127 | .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK, | |
f8b23bbd KK |
128 | }; |
129 | ||
0c5deb1e | 130 | /* |
8ae83b6f KK |
131 | * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits |
132 | * are swapped. | |
0c5deb1e | 133 | */ |
8ae83b6f | 134 | static const struct s5m_rtc_reg_config s2mps15_rtc_regs = { |
0c5deb1e KK |
135 | .regs_count = 7, |
136 | .time = S2MPS_RTC_SEC, | |
137 | .ctrl = S2MPS_RTC_CTRL, | |
138 | .alarm0 = S2MPS_ALARM0_SEC, | |
139 | .alarm1 = S2MPS_ALARM1_SEC, | |
a83a793a | 140 | .udr_update = S2MPS_RTC_UDR_CON, |
67a6025a | 141 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, |
8ae83b6f KK |
142 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, |
143 | .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK, | |
144 | .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK, | |
0c5deb1e KK |
145 | }; |
146 | ||
5bccae6e SK |
147 | struct s5m_rtc_info { |
148 | struct device *dev; | |
e349c910 | 149 | struct i2c_client *i2c; |
5bccae6e | 150 | struct sec_pmic_dev *s5m87xx; |
5ccb7d71 | 151 | struct regmap *regmap; |
5bccae6e SK |
152 | struct rtc_device *rtc_dev; |
153 | int irq; | |
94f91922 | 154 | enum sec_device_type device_type; |
5bccae6e | 155 | int rtc_24hr_mode; |
f8b23bbd | 156 | const struct s5m_rtc_reg_config *regs; |
5bccae6e SK |
157 | }; |
158 | ||
e349c910 KK |
159 | static const struct regmap_config s5m_rtc_regmap_config = { |
160 | .reg_bits = 8, | |
161 | .val_bits = 8, | |
162 | ||
602cb5bb | 163 | .max_register = S5M_RTC_REG_MAX, |
e349c910 KK |
164 | }; |
165 | ||
166 | static const struct regmap_config s2mps14_rtc_regmap_config = { | |
167 | .reg_bits = 8, | |
168 | .val_bits = 8, | |
169 | ||
170 | .max_register = S2MPS_RTC_REG_MAX, | |
171 | }; | |
172 | ||
5bccae6e SK |
173 | static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm, |
174 | int rtc_24hr_mode) | |
175 | { | |
176 | tm->tm_sec = data[RTC_SEC] & 0x7f; | |
177 | tm->tm_min = data[RTC_MIN] & 0x7f; | |
178 | if (rtc_24hr_mode) { | |
179 | tm->tm_hour = data[RTC_HOUR] & 0x1f; | |
180 | } else { | |
181 | tm->tm_hour = data[RTC_HOUR] & 0x0f; | |
182 | if (data[RTC_HOUR] & HOUR_PM_MASK) | |
183 | tm->tm_hour += 12; | |
184 | } | |
185 | ||
186 | tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f); | |
187 | tm->tm_mday = data[RTC_DATE] & 0x1f; | |
188 | tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; | |
189 | tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100; | |
190 | tm->tm_yday = 0; | |
191 | tm->tm_isdst = 0; | |
192 | } | |
193 | ||
194 | static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data) | |
195 | { | |
196 | data[RTC_SEC] = tm->tm_sec; | |
197 | data[RTC_MIN] = tm->tm_min; | |
198 | ||
199 | if (tm->tm_hour >= 12) | |
200 | data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK; | |
201 | else | |
202 | data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK; | |
203 | ||
204 | data[RTC_WEEKDAY] = 1 << tm->tm_wday; | |
205 | data[RTC_DATE] = tm->tm_mday; | |
206 | data[RTC_MONTH] = tm->tm_mon + 1; | |
207 | data[RTC_YEAR1] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0; | |
208 | ||
209 | if (tm->tm_year < 100) { | |
a737e835 | 210 | pr_err("RTC cannot handle the year %d\n", |
5bccae6e SK |
211 | 1900 + tm->tm_year); |
212 | return -EINVAL; | |
213 | } else { | |
214 | return 0; | |
215 | } | |
216 | } | |
217 | ||
d73238d4 KK |
218 | /* |
219 | * Read RTC_UDR_CON register and wait till UDR field is cleared. | |
220 | * This indicates that time/alarm update ended. | |
221 | */ | |
8124c711 | 222 | static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info) |
d73238d4 KK |
223 | { |
224 | int ret, retry = UDR_READ_RETRY_CNT; | |
225 | unsigned int data; | |
226 | ||
227 | do { | |
a83a793a | 228 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
67a6025a | 229 | } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret); |
d73238d4 KK |
230 | |
231 | if (!retry) | |
232 | dev_err(info->dev, "waiting for UDR update, reached max number of retries\n"); | |
233 | ||
234 | return ret; | |
235 | } | |
236 | ||
8124c711 | 237 | static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info, |
f8b23bbd KK |
238 | struct rtc_wkalrm *alarm) |
239 | { | |
240 | int ret; | |
241 | unsigned int val; | |
242 | ||
243 | switch (info->device_type) { | |
244 | case S5M8767X: | |
245 | case S5M8763X: | |
246 | ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); | |
247 | val &= S5M_ALARM0_STATUS; | |
248 | break; | |
a65e5efa | 249 | case S2MPS15X: |
0c5deb1e | 250 | case S2MPS14X: |
5281f94a | 251 | case S2MPS13X: |
0c5deb1e KK |
252 | ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2, |
253 | &val); | |
254 | val &= S2MPS_ALARM0_STATUS; | |
255 | break; | |
f8b23bbd KK |
256 | default: |
257 | return -EINVAL; | |
258 | } | |
259 | if (ret < 0) | |
260 | return ret; | |
261 | ||
262 | if (val) | |
263 | alarm->pending = 1; | |
264 | else | |
265 | alarm->pending = 0; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
8124c711 | 270 | static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info) |
5bccae6e SK |
271 | { |
272 | int ret; | |
273 | unsigned int data; | |
274 | ||
a83a793a | 275 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
5bccae6e SK |
276 | if (ret < 0) { |
277 | dev_err(info->dev, "failed to read update reg(%d)\n", ret); | |
278 | return ret; | |
279 | } | |
280 | ||
8ae83b6f | 281 | data |= info->regs->write_time_udr_mask; |
a65e5efa | 282 | |
a83a793a | 283 | ret = regmap_write(info->regmap, info->regs->udr_update, data); |
5bccae6e SK |
284 | if (ret < 0) { |
285 | dev_err(info->dev, "failed to write update reg(%d)\n", ret); | |
286 | return ret; | |
287 | } | |
288 | ||
d73238d4 | 289 | ret = s5m8767_wait_for_udr_update(info); |
5bccae6e SK |
290 | |
291 | return ret; | |
292 | } | |
293 | ||
8124c711 | 294 | static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info) |
5bccae6e SK |
295 | { |
296 | int ret; | |
297 | unsigned int data; | |
298 | ||
a83a793a | 299 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
5bccae6e SK |
300 | if (ret < 0) { |
301 | dev_err(info->dev, "%s: fail to read update reg(%d)\n", | |
302 | __func__, ret); | |
303 | return ret; | |
304 | } | |
305 | ||
8ae83b6f | 306 | data |= info->regs->write_alarm_udr_mask; |
0c5deb1e KK |
307 | switch (info->device_type) { |
308 | case S5M8763X: | |
309 | case S5M8767X: | |
310 | data &= ~S5M_RTC_TIME_EN_MASK; | |
311 | break; | |
a65e5efa | 312 | case S2MPS15X: |
0c5deb1e | 313 | case S2MPS14X: |
5281f94a | 314 | case S2MPS13X: |
8ae83b6f | 315 | /* No exceptions needed */ |
5281f94a | 316 | break; |
0c5deb1e KK |
317 | default: |
318 | return -EINVAL; | |
319 | } | |
5bccae6e | 320 | |
a83a793a | 321 | ret = regmap_write(info->regmap, info->regs->udr_update, data); |
5bccae6e SK |
322 | if (ret < 0) { |
323 | dev_err(info->dev, "%s: fail to write update reg(%d)\n", | |
324 | __func__, ret); | |
325 | return ret; | |
326 | } | |
327 | ||
d73238d4 | 328 | ret = s5m8767_wait_for_udr_update(info); |
5bccae6e | 329 | |
5281f94a KK |
330 | /* On S2MPS13 the AUDR is not auto-cleared */ |
331 | if (info->device_type == S2MPS13X) | |
a83a793a | 332 | regmap_update_bits(info->regmap, info->regs->udr_update, |
5281f94a KK |
333 | S2MPS13_RTC_AUDR_MASK, 0); |
334 | ||
5bccae6e SK |
335 | return ret; |
336 | } | |
337 | ||
338 | static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm) | |
339 | { | |
340 | tm->tm_sec = bcd2bin(data[RTC_SEC]); | |
341 | tm->tm_min = bcd2bin(data[RTC_MIN]); | |
342 | ||
343 | if (data[RTC_HOUR] & HOUR_12) { | |
344 | tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f); | |
345 | if (data[RTC_HOUR] & HOUR_PM) | |
346 | tm->tm_hour += 12; | |
347 | } else { | |
348 | tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f); | |
349 | } | |
350 | ||
351 | tm->tm_wday = data[RTC_WEEKDAY] & 0x07; | |
352 | tm->tm_mday = bcd2bin(data[RTC_DATE]); | |
353 | tm->tm_mon = bcd2bin(data[RTC_MONTH]); | |
354 | tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100; | |
355 | tm->tm_year -= 1900; | |
356 | } | |
357 | ||
358 | static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data) | |
359 | { | |
360 | data[RTC_SEC] = bin2bcd(tm->tm_sec); | |
361 | data[RTC_MIN] = bin2bcd(tm->tm_min); | |
362 | data[RTC_HOUR] = bin2bcd(tm->tm_hour); | |
363 | data[RTC_WEEKDAY] = tm->tm_wday; | |
364 | data[RTC_DATE] = bin2bcd(tm->tm_mday); | |
365 | data[RTC_MONTH] = bin2bcd(tm->tm_mon); | |
366 | data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100); | |
367 | data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100); | |
368 | } | |
369 | ||
370 | static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
371 | { | |
372 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 373 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
374 | int ret; |
375 | ||
8ae83b6f | 376 | if (info->regs->read_time_udr_mask) { |
0c5deb1e | 377 | ret = regmap_update_bits(info->regmap, |
a83a793a | 378 | info->regs->udr_update, |
8ae83b6f KK |
379 | info->regs->read_time_udr_mask, |
380 | info->regs->read_time_udr_mask); | |
0c5deb1e KK |
381 | if (ret) { |
382 | dev_err(dev, | |
383 | "Failed to prepare registers for time reading: %d\n", | |
384 | ret); | |
385 | return ret; | |
386 | } | |
387 | } | |
f8b23bbd KK |
388 | ret = regmap_bulk_read(info->regmap, info->regs->time, data, |
389 | info->regs->regs_count); | |
5bccae6e SK |
390 | if (ret < 0) |
391 | return ret; | |
392 | ||
393 | switch (info->device_type) { | |
394 | case S5M8763X: | |
395 | s5m8763_data_to_tm(data, tm); | |
396 | break; | |
397 | ||
398 | case S5M8767X: | |
a65e5efa | 399 | case S2MPS15X: |
0c5deb1e | 400 | case S2MPS14X: |
5281f94a | 401 | case S2MPS13X: |
5bccae6e SK |
402 | s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode); |
403 | break; | |
404 | ||
405 | default: | |
406 | return -EINVAL; | |
407 | } | |
408 | ||
5527842e | 409 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday); |
5bccae6e | 410 | |
22652ba7 | 411 | return 0; |
5bccae6e SK |
412 | } |
413 | ||
414 | static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
415 | { | |
416 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 417 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
418 | int ret = 0; |
419 | ||
420 | switch (info->device_type) { | |
421 | case S5M8763X: | |
422 | s5m8763_tm_to_data(tm, data); | |
423 | break; | |
424 | case S5M8767X: | |
a65e5efa | 425 | case S2MPS15X: |
0c5deb1e | 426 | case S2MPS14X: |
5281f94a | 427 | case S2MPS13X: |
5bccae6e SK |
428 | ret = s5m8767_tm_to_data(tm, data); |
429 | break; | |
430 | default: | |
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | if (ret < 0) | |
435 | return ret; | |
436 | ||
5527842e | 437 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday); |
5bccae6e | 438 | |
f8b23bbd KK |
439 | ret = regmap_raw_write(info->regmap, info->regs->time, data, |
440 | info->regs->regs_count); | |
5bccae6e SK |
441 | if (ret < 0) |
442 | return ret; | |
443 | ||
444 | ret = s5m8767_rtc_set_time_reg(info); | |
445 | ||
446 | return ret; | |
447 | } | |
448 | ||
449 | static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
450 | { | |
451 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 452 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
453 | unsigned int val; |
454 | int ret, i; | |
455 | ||
f8b23bbd KK |
456 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
457 | info->regs->regs_count); | |
5bccae6e SK |
458 | if (ret < 0) |
459 | return ret; | |
460 | ||
461 | switch (info->device_type) { | |
462 | case S5M8763X: | |
463 | s5m8763_data_to_tm(data, &alrm->time); | |
602cb5bb | 464 | ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val); |
5bccae6e SK |
465 | if (ret < 0) |
466 | return ret; | |
467 | ||
468 | alrm->enabled = !!val; | |
5bccae6e SK |
469 | break; |
470 | ||
471 | case S5M8767X: | |
a65e5efa | 472 | case S2MPS15X: |
0c5deb1e | 473 | case S2MPS14X: |
5281f94a | 474 | case S2MPS13X: |
5bccae6e | 475 | s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode); |
5bccae6e | 476 | alrm->enabled = 0; |
f8b23bbd | 477 | for (i = 0; i < info->regs->regs_count; i++) { |
5bccae6e SK |
478 | if (data[i] & ALARM_ENABLE_MASK) { |
479 | alrm->enabled = 1; | |
480 | break; | |
481 | } | |
482 | } | |
5bccae6e SK |
483 | break; |
484 | ||
485 | default: | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
5527842e | 489 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday); |
f8b23bbd KK |
490 | |
491 | ret = s5m_check_peding_alarm_interrupt(info, alrm); | |
5bccae6e SK |
492 | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) | |
497 | { | |
756d5282 | 498 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
499 | int ret, i; |
500 | struct rtc_time tm; | |
501 | ||
f8b23bbd KK |
502 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
503 | info->regs->regs_count); | |
5bccae6e SK |
504 | if (ret < 0) |
505 | return ret; | |
506 | ||
507 | s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); | |
5527842e | 508 | dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday); |
5bccae6e SK |
509 | |
510 | switch (info->device_type) { | |
511 | case S5M8763X: | |
602cb5bb | 512 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0); |
5bccae6e SK |
513 | break; |
514 | ||
515 | case S5M8767X: | |
a65e5efa | 516 | case S2MPS15X: |
0c5deb1e | 517 | case S2MPS14X: |
5281f94a | 518 | case S2MPS13X: |
f8b23bbd | 519 | for (i = 0; i < info->regs->regs_count; i++) |
5bccae6e SK |
520 | data[i] &= ~ALARM_ENABLE_MASK; |
521 | ||
f8b23bbd KK |
522 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
523 | info->regs->regs_count); | |
5bccae6e SK |
524 | if (ret < 0) |
525 | return ret; | |
526 | ||
527 | ret = s5m8767_rtc_set_alarm_reg(info); | |
528 | ||
529 | break; | |
530 | ||
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
538 | static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | |
539 | { | |
540 | int ret; | |
756d5282 | 541 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
542 | u8 alarm0_conf; |
543 | struct rtc_time tm; | |
544 | ||
f8b23bbd KK |
545 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
546 | info->regs->regs_count); | |
5bccae6e SK |
547 | if (ret < 0) |
548 | return ret; | |
549 | ||
550 | s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); | |
5527842e | 551 | dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday); |
5bccae6e SK |
552 | |
553 | switch (info->device_type) { | |
554 | case S5M8763X: | |
555 | alarm0_conf = 0x77; | |
602cb5bb | 556 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf); |
5bccae6e SK |
557 | break; |
558 | ||
559 | case S5M8767X: | |
a65e5efa | 560 | case S2MPS15X: |
0c5deb1e | 561 | case S2MPS14X: |
5281f94a | 562 | case S2MPS13X: |
5bccae6e SK |
563 | data[RTC_SEC] |= ALARM_ENABLE_MASK; |
564 | data[RTC_MIN] |= ALARM_ENABLE_MASK; | |
565 | data[RTC_HOUR] |= ALARM_ENABLE_MASK; | |
566 | data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK; | |
567 | if (data[RTC_DATE] & 0x1f) | |
568 | data[RTC_DATE] |= ALARM_ENABLE_MASK; | |
569 | if (data[RTC_MONTH] & 0xf) | |
570 | data[RTC_MONTH] |= ALARM_ENABLE_MASK; | |
571 | if (data[RTC_YEAR1] & 0x7f) | |
572 | data[RTC_YEAR1] |= ALARM_ENABLE_MASK; | |
573 | ||
f8b23bbd KK |
574 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
575 | info->regs->regs_count); | |
5bccae6e SK |
576 | if (ret < 0) |
577 | return ret; | |
578 | ret = s5m8767_rtc_set_alarm_reg(info); | |
579 | ||
580 | break; | |
581 | ||
582 | default: | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
586 | return ret; | |
587 | } | |
588 | ||
589 | static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
590 | { | |
591 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 592 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
593 | int ret; |
594 | ||
595 | switch (info->device_type) { | |
596 | case S5M8763X: | |
597 | s5m8763_tm_to_data(&alrm->time, data); | |
598 | break; | |
599 | ||
600 | case S5M8767X: | |
a65e5efa | 601 | case S2MPS15X: |
0c5deb1e | 602 | case S2MPS14X: |
5281f94a | 603 | case S2MPS13X: |
5bccae6e SK |
604 | s5m8767_tm_to_data(&alrm->time, data); |
605 | break; | |
606 | ||
607 | default: | |
608 | return -EINVAL; | |
609 | } | |
610 | ||
5527842e | 611 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday); |
5bccae6e SK |
612 | |
613 | ret = s5m_rtc_stop_alarm(info); | |
614 | if (ret < 0) | |
615 | return ret; | |
616 | ||
f8b23bbd KK |
617 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
618 | info->regs->regs_count); | |
5bccae6e SK |
619 | if (ret < 0) |
620 | return ret; | |
621 | ||
622 | ret = s5m8767_rtc_set_alarm_reg(info); | |
623 | if (ret < 0) | |
624 | return ret; | |
625 | ||
626 | if (alrm->enabled) | |
627 | ret = s5m_rtc_start_alarm(info); | |
628 | ||
629 | return ret; | |
630 | } | |
631 | ||
632 | static int s5m_rtc_alarm_irq_enable(struct device *dev, | |
633 | unsigned int enabled) | |
634 | { | |
635 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
636 | ||
637 | if (enabled) | |
638 | return s5m_rtc_start_alarm(info); | |
639 | else | |
640 | return s5m_rtc_stop_alarm(info); | |
641 | } | |
642 | ||
643 | static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data) | |
644 | { | |
645 | struct s5m_rtc_info *info = data; | |
646 | ||
647 | rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); | |
648 | ||
649 | return IRQ_HANDLED; | |
650 | } | |
651 | ||
652 | static const struct rtc_class_ops s5m_rtc_ops = { | |
653 | .read_time = s5m_rtc_read_time, | |
654 | .set_time = s5m_rtc_set_time, | |
655 | .read_alarm = s5m_rtc_read_alarm, | |
656 | .set_alarm = s5m_rtc_set_alarm, | |
657 | .alarm_irq_enable = s5m_rtc_alarm_irq_enable, | |
658 | }; | |
659 | ||
5bccae6e SK |
660 | static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) |
661 | { | |
662 | u8 data[2]; | |
5bccae6e | 663 | int ret; |
5bccae6e | 664 | |
0c5deb1e KK |
665 | switch (info->device_type) { |
666 | case S5M8763X: | |
667 | case S5M8767X: | |
668 | /* UDR update time. Default of 7.32 ms is too long. */ | |
669 | ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON, | |
670 | S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US); | |
671 | if (ret < 0) | |
672 | dev_err(info->dev, "%s: fail to change UDR time: %d\n", | |
673 | __func__, ret); | |
0c5f5d9a | 674 | |
0c5deb1e KK |
675 | /* Set RTC control register : Binary mode, 24hour mode */ |
676 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
677 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
678 | ||
679 | ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2); | |
680 | break; | |
681 | ||
a65e5efa | 682 | case S2MPS15X: |
0c5deb1e | 683 | case S2MPS14X: |
5281f94a | 684 | case S2MPS13X: |
0c5deb1e KK |
685 | data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
686 | ret = regmap_write(info->regmap, info->regs->ctrl, data[0]); | |
ff02c044 JS |
687 | if (ret < 0) |
688 | break; | |
689 | ||
690 | /* | |
691 | * Should set WUDR & (RUDR or AUDR) bits to high after writing | |
692 | * RTC_CTRL register like writing Alarm registers. We can't find | |
693 | * the description from datasheet but vendor code does that | |
694 | * really. | |
695 | */ | |
696 | ret = s5m8767_rtc_set_alarm_reg(info); | |
0c5deb1e KK |
697 | break; |
698 | ||
699 | default: | |
700 | return -EINVAL; | |
701 | } | |
5bccae6e SK |
702 | |
703 | info->rtc_24hr_mode = 1; | |
5bccae6e SK |
704 | if (ret < 0) { |
705 | dev_err(info->dev, "%s: fail to write controlm reg(%d)\n", | |
706 | __func__, ret); | |
707 | return ret; | |
708 | } | |
709 | ||
5bccae6e SK |
710 | return ret; |
711 | } | |
712 | ||
713 | static int s5m_rtc_probe(struct platform_device *pdev) | |
714 | { | |
715 | struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent); | |
716 | struct sec_platform_data *pdata = s5m87xx->pdata; | |
717 | struct s5m_rtc_info *info; | |
e349c910 | 718 | const struct regmap_config *regmap_cfg; |
a0347f20 | 719 | int ret, alarm_irq; |
5bccae6e SK |
720 | |
721 | if (!pdata) { | |
722 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); | |
723 | return -ENODEV; | |
724 | } | |
725 | ||
726 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
727 | if (!info) | |
728 | return -ENOMEM; | |
729 | ||
94f91922 | 730 | switch (platform_get_device_id(pdev)->driver_data) { |
a65e5efa | 731 | case S2MPS15X: |
8ae83b6f KK |
732 | regmap_cfg = &s2mps14_rtc_regmap_config; |
733 | info->regs = &s2mps15_rtc_regs; | |
734 | alarm_irq = S2MPS14_IRQ_RTCA0; | |
735 | break; | |
e349c910 | 736 | case S2MPS14X: |
8ae83b6f KK |
737 | regmap_cfg = &s2mps14_rtc_regmap_config; |
738 | info->regs = &s2mps14_rtc_regs; | |
739 | alarm_irq = S2MPS14_IRQ_RTCA0; | |
740 | break; | |
5281f94a | 741 | case S2MPS13X: |
e349c910 | 742 | regmap_cfg = &s2mps14_rtc_regmap_config; |
8ae83b6f | 743 | info->regs = &s2mps13_rtc_regs; |
a0347f20 | 744 | alarm_irq = S2MPS14_IRQ_RTCA0; |
e349c910 KK |
745 | break; |
746 | case S5M8763X: | |
747 | regmap_cfg = &s5m_rtc_regmap_config; | |
f8b23bbd | 748 | info->regs = &s5m_rtc_regs; |
a0347f20 | 749 | alarm_irq = S5M8763_IRQ_ALARM0; |
e349c910 KK |
750 | break; |
751 | case S5M8767X: | |
752 | regmap_cfg = &s5m_rtc_regmap_config; | |
f8b23bbd | 753 | info->regs = &s5m_rtc_regs; |
a0347f20 | 754 | alarm_irq = S5M8767_IRQ_RTCA1; |
e349c910 KK |
755 | break; |
756 | default: | |
94f91922 KK |
757 | dev_err(&pdev->dev, |
758 | "Device type %lu is not supported by RTC driver\n", | |
759 | platform_get_device_id(pdev)->driver_data); | |
e349c910 KK |
760 | return -ENODEV; |
761 | } | |
762 | ||
7db7ad08 BG |
763 | info->i2c = devm_i2c_new_dummy_device(&pdev->dev, s5m87xx->i2c->adapter, |
764 | RTC_I2C_ADDR); | |
aae364d2 | 765 | if (IS_ERR(info->i2c)) { |
e349c910 | 766 | dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n"); |
aae364d2 | 767 | return PTR_ERR(info->i2c); |
e349c910 KK |
768 | } |
769 | ||
770 | info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg); | |
771 | if (IS_ERR(info->regmap)) { | |
772 | ret = PTR_ERR(info->regmap); | |
773 | dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n", | |
774 | ret); | |
7db7ad08 | 775 | return ret; |
e349c910 KK |
776 | } |
777 | ||
5bccae6e SK |
778 | info->dev = &pdev->dev; |
779 | info->s5m87xx = s5m87xx; | |
94f91922 | 780 | info->device_type = platform_get_device_id(pdev)->driver_data; |
5bccae6e | 781 | |
b7d5b9a9 BZ |
782 | if (s5m87xx->irq_data) { |
783 | info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq); | |
784 | if (info->irq <= 0) { | |
b7d5b9a9 | 785 | dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n", |
a0347f20 | 786 | alarm_irq); |
7db7ad08 | 787 | return -EINVAL; |
b7d5b9a9 | 788 | } |
5bccae6e SK |
789 | } |
790 | ||
791 | platform_set_drvdata(pdev, info); | |
792 | ||
793 | ret = s5m8767_rtc_init_reg(info); | |
794 | ||
5bccae6e SK |
795 | device_init_wakeup(&pdev->dev, 1); |
796 | ||
797 | info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc", | |
798 | &s5m_rtc_ops, THIS_MODULE); | |
799 | ||
7db7ad08 BG |
800 | if (IS_ERR(info->rtc_dev)) |
801 | return PTR_ERR(info->rtc_dev); | |
5bccae6e | 802 | |
b7d5b9a9 BZ |
803 | if (!info->irq) { |
804 | dev_info(&pdev->dev, "Alarm IRQ not available\n"); | |
805 | return 0; | |
806 | } | |
807 | ||
5bccae6e SK |
808 | ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL, |
809 | s5m_rtc_alarm_irq, 0, "rtc-alarm0", | |
810 | info); | |
e349c910 | 811 | if (ret < 0) { |
5bccae6e SK |
812 | dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", |
813 | info->irq, ret); | |
7db7ad08 | 814 | return ret; |
e349c910 KK |
815 | } |
816 | ||
e349c910 KK |
817 | return 0; |
818 | } | |
819 | ||
11ba5a1e | 820 | #ifdef CONFIG_PM_SLEEP |
222ead7f KK |
821 | static int s5m_rtc_resume(struct device *dev) |
822 | { | |
823 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
824 | int ret = 0; | |
825 | ||
b7d5b9a9 | 826 | if (info->irq && device_may_wakeup(dev)) |
222ead7f KK |
827 | ret = disable_irq_wake(info->irq); |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
832 | static int s5m_rtc_suspend(struct device *dev) | |
833 | { | |
834 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
835 | int ret = 0; | |
836 | ||
b7d5b9a9 | 837 | if (info->irq && device_may_wakeup(dev)) |
222ead7f KK |
838 | ret = enable_irq_wake(info->irq); |
839 | ||
840 | return ret; | |
841 | } | |
11ba5a1e | 842 | #endif /* CONFIG_PM_SLEEP */ |
222ead7f KK |
843 | |
844 | static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); | |
845 | ||
5bccae6e | 846 | static const struct platform_device_id s5m_rtc_id[] = { |
0c5deb1e | 847 | { "s5m-rtc", S5M8767X }, |
5281f94a | 848 | { "s2mps13-rtc", S2MPS13X }, |
0c5deb1e | 849 | { "s2mps14-rtc", S2MPS14X }, |
a65e5efa | 850 | { "s2mps15-rtc", S2MPS15X }, |
45cd15e6 | 851 | { }, |
5bccae6e | 852 | }; |
63074cc3 | 853 | MODULE_DEVICE_TABLE(platform, s5m_rtc_id); |
5bccae6e SK |
854 | |
855 | static struct platform_driver s5m_rtc_driver = { | |
856 | .driver = { | |
857 | .name = "s5m-rtc", | |
222ead7f | 858 | .pm = &s5m_rtc_pm_ops, |
5bccae6e SK |
859 | }, |
860 | .probe = s5m_rtc_probe, | |
5bccae6e SK |
861 | .id_table = s5m_rtc_id, |
862 | }; | |
863 | ||
864 | module_platform_driver(s5m_rtc_driver); | |
865 | ||
866 | /* Module information */ | |
867 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | |
0c5deb1e | 868 | MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver"); |
5bccae6e SK |
869 | MODULE_LICENSE("GPL"); |
870 | MODULE_ALIAS("platform:s5m-rtc"); |