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26dcc12c KK |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd | |
4 | // http://www.samsung.com | |
5 | // | |
6 | // Copyright (C) 2013 Google, Inc | |
5bccae6e | 7 | |
a737e835 JP |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
9 | ||
5bccae6e SK |
10 | #include <linux/module.h> |
11 | #include <linux/i2c.h> | |
5bccae6e | 12 | #include <linux/bcd.h> |
5bccae6e SK |
13 | #include <linux/regmap.h> |
14 | #include <linux/rtc.h> | |
5bccae6e SK |
15 | #include <linux/platform_device.h> |
16 | #include <linux/mfd/samsung/core.h> | |
17 | #include <linux/mfd/samsung/irq.h> | |
18 | #include <linux/mfd/samsung/rtc.h> | |
0c5deb1e | 19 | #include <linux/mfd/samsung/s2mps14.h> |
5bccae6e | 20 | |
d73238d4 KK |
21 | /* |
22 | * Maximum number of retries for checking changes in UDR field | |
602cb5bb | 23 | * of S5M_RTC_UDR_CON register (to limit possible endless loop). |
d73238d4 KK |
24 | * |
25 | * After writing to RTC registers (setting time or alarm) read the UDR field | |
602cb5bb | 26 | * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have |
d73238d4 KK |
27 | * been transferred. |
28 | */ | |
29 | #define UDR_READ_RETRY_CNT 5 | |
30 | ||
4a681243 GS |
31 | enum { |
32 | RTC_SEC = 0, | |
33 | RTC_MIN, | |
34 | RTC_HOUR, | |
35 | RTC_WEEKDAY, | |
36 | RTC_DATE, | |
37 | RTC_MONTH, | |
38 | RTC_YEAR1, | |
39 | RTC_YEAR2, | |
756d5282 GS |
40 | /* Make sure this is always the last enum name. */ |
41 | RTC_MAX_NUM_TIME_REGS | |
4a681243 GS |
42 | }; |
43 | ||
8ae83b6f KK |
44 | /* |
45 | * Registers used by the driver which are different between chipsets. | |
46 | * | |
47 | * Operations like read time and write alarm/time require updating | |
48 | * specific fields in UDR register. These fields usually are auto-cleared | |
49 | * (with some exceptions). | |
50 | * | |
51 | * Table of operations per device: | |
52 | * | |
53 | * Device | Write time | Read time | Write alarm | |
54 | * ================================================= | |
55 | * S5M8767 | UDR + TIME | | UDR | |
56 | * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR | |
57 | * S2MPS13 | WUDR | RUDR | WUDR + AUDR | |
58 | * S2MPS15 | WUDR | RUDR | AUDR | |
59 | */ | |
f8b23bbd KK |
60 | struct s5m_rtc_reg_config { |
61 | /* Number of registers used for setting time/alarm0/alarm1 */ | |
62 | unsigned int regs_count; | |
63 | /* First register for time, seconds */ | |
64 | unsigned int time; | |
65 | /* RTC control register */ | |
66 | unsigned int ctrl; | |
67 | /* First register for alarm 0, seconds */ | |
68 | unsigned int alarm0; | |
69 | /* First register for alarm 1, seconds */ | |
70 | unsigned int alarm1; | |
f8b23bbd KK |
71 | /* |
72 | * Register for update flag (UDR). Typically setting UDR field to 1 | |
73 | * will enable update of time or alarm register. Then it will be | |
74 | * auto-cleared after successful update. | |
75 | */ | |
a83a793a | 76 | unsigned int udr_update; |
67a6025a KK |
77 | /* Auto-cleared mask in UDR field for writing time and alarm */ |
78 | unsigned int autoclear_udr_mask; | |
8ae83b6f KK |
79 | /* |
80 | * Masks in UDR field for time and alarm operations. | |
81 | * The read time mask can be 0. Rest should not. | |
82 | */ | |
83 | unsigned int read_time_udr_mask; | |
84 | unsigned int write_time_udr_mask; | |
85 | unsigned int write_alarm_udr_mask; | |
f8b23bbd KK |
86 | }; |
87 | ||
88 | /* Register map for S5M8763 and S5M8767 */ | |
89 | static const struct s5m_rtc_reg_config s5m_rtc_regs = { | |
90 | .regs_count = 8, | |
91 | .time = S5M_RTC_SEC, | |
92 | .ctrl = S5M_ALARM1_CONF, | |
93 | .alarm0 = S5M_ALARM0_SEC, | |
94 | .alarm1 = S5M_ALARM1_SEC, | |
a83a793a | 95 | .udr_update = S5M_RTC_UDR_CON, |
67a6025a | 96 | .autoclear_udr_mask = S5M_RTC_UDR_MASK, |
8ae83b6f KK |
97 | .read_time_udr_mask = 0, /* Not needed */ |
98 | .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK, | |
99 | .write_alarm_udr_mask = S5M_RTC_UDR_MASK, | |
100 | }; | |
101 | ||
102 | /* Register map for S2MPS13 */ | |
103 | static const struct s5m_rtc_reg_config s2mps13_rtc_regs = { | |
104 | .regs_count = 7, | |
105 | .time = S2MPS_RTC_SEC, | |
106 | .ctrl = S2MPS_RTC_CTRL, | |
107 | .alarm0 = S2MPS_ALARM0_SEC, | |
108 | .alarm1 = S2MPS_ALARM1_SEC, | |
109 | .udr_update = S2MPS_RTC_UDR_CON, | |
110 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, | |
111 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, | |
112 | .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, | |
113 | .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK, | |
114 | }; | |
115 | ||
116 | /* Register map for S2MPS11/14 */ | |
117 | static const struct s5m_rtc_reg_config s2mps14_rtc_regs = { | |
118 | .regs_count = 7, | |
119 | .time = S2MPS_RTC_SEC, | |
120 | .ctrl = S2MPS_RTC_CTRL, | |
121 | .alarm0 = S2MPS_ALARM0_SEC, | |
122 | .alarm1 = S2MPS_ALARM1_SEC, | |
123 | .udr_update = S2MPS_RTC_UDR_CON, | |
124 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, | |
125 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, | |
126 | .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, | |
127 | .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK, | |
f8b23bbd KK |
128 | }; |
129 | ||
0c5deb1e | 130 | /* |
8ae83b6f KK |
131 | * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits |
132 | * are swapped. | |
0c5deb1e | 133 | */ |
8ae83b6f | 134 | static const struct s5m_rtc_reg_config s2mps15_rtc_regs = { |
0c5deb1e KK |
135 | .regs_count = 7, |
136 | .time = S2MPS_RTC_SEC, | |
137 | .ctrl = S2MPS_RTC_CTRL, | |
138 | .alarm0 = S2MPS_ALARM0_SEC, | |
139 | .alarm1 = S2MPS_ALARM1_SEC, | |
a83a793a | 140 | .udr_update = S2MPS_RTC_UDR_CON, |
67a6025a | 141 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, |
8ae83b6f KK |
142 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, |
143 | .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK, | |
144 | .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK, | |
0c5deb1e KK |
145 | }; |
146 | ||
5bccae6e SK |
147 | struct s5m_rtc_info { |
148 | struct device *dev; | |
e349c910 | 149 | struct i2c_client *i2c; |
5bccae6e | 150 | struct sec_pmic_dev *s5m87xx; |
5ccb7d71 | 151 | struct regmap *regmap; |
5bccae6e SK |
152 | struct rtc_device *rtc_dev; |
153 | int irq; | |
94f91922 | 154 | enum sec_device_type device_type; |
5bccae6e | 155 | int rtc_24hr_mode; |
f8b23bbd | 156 | const struct s5m_rtc_reg_config *regs; |
5bccae6e SK |
157 | }; |
158 | ||
e349c910 KK |
159 | static const struct regmap_config s5m_rtc_regmap_config = { |
160 | .reg_bits = 8, | |
161 | .val_bits = 8, | |
162 | ||
602cb5bb | 163 | .max_register = S5M_RTC_REG_MAX, |
e349c910 KK |
164 | }; |
165 | ||
166 | static const struct regmap_config s2mps14_rtc_regmap_config = { | |
167 | .reg_bits = 8, | |
168 | .val_bits = 8, | |
169 | ||
170 | .max_register = S2MPS_RTC_REG_MAX, | |
171 | }; | |
172 | ||
5bccae6e SK |
173 | static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm, |
174 | int rtc_24hr_mode) | |
175 | { | |
176 | tm->tm_sec = data[RTC_SEC] & 0x7f; | |
177 | tm->tm_min = data[RTC_MIN] & 0x7f; | |
178 | if (rtc_24hr_mode) { | |
179 | tm->tm_hour = data[RTC_HOUR] & 0x1f; | |
180 | } else { | |
181 | tm->tm_hour = data[RTC_HOUR] & 0x0f; | |
182 | if (data[RTC_HOUR] & HOUR_PM_MASK) | |
183 | tm->tm_hour += 12; | |
184 | } | |
185 | ||
186 | tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f); | |
187 | tm->tm_mday = data[RTC_DATE] & 0x1f; | |
188 | tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; | |
189 | tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100; | |
190 | tm->tm_yday = 0; | |
191 | tm->tm_isdst = 0; | |
192 | } | |
193 | ||
194 | static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data) | |
195 | { | |
196 | data[RTC_SEC] = tm->tm_sec; | |
197 | data[RTC_MIN] = tm->tm_min; | |
198 | ||
199 | if (tm->tm_hour >= 12) | |
200 | data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK; | |
201 | else | |
202 | data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK; | |
203 | ||
204 | data[RTC_WEEKDAY] = 1 << tm->tm_wday; | |
205 | data[RTC_DATE] = tm->tm_mday; | |
206 | data[RTC_MONTH] = tm->tm_mon + 1; | |
fffd603a | 207 | data[RTC_YEAR1] = tm->tm_year - 100; |
5bccae6e | 208 | |
fffd603a | 209 | return 0; |
5bccae6e SK |
210 | } |
211 | ||
d73238d4 KK |
212 | /* |
213 | * Read RTC_UDR_CON register and wait till UDR field is cleared. | |
214 | * This indicates that time/alarm update ended. | |
215 | */ | |
8124c711 | 216 | static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info) |
d73238d4 KK |
217 | { |
218 | int ret, retry = UDR_READ_RETRY_CNT; | |
219 | unsigned int data; | |
220 | ||
221 | do { | |
a83a793a | 222 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
67a6025a | 223 | } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret); |
d73238d4 KK |
224 | |
225 | if (!retry) | |
226 | dev_err(info->dev, "waiting for UDR update, reached max number of retries\n"); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
8124c711 | 231 | static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info, |
f8b23bbd KK |
232 | struct rtc_wkalrm *alarm) |
233 | { | |
234 | int ret; | |
235 | unsigned int val; | |
236 | ||
237 | switch (info->device_type) { | |
238 | case S5M8767X: | |
239 | case S5M8763X: | |
240 | ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); | |
241 | val &= S5M_ALARM0_STATUS; | |
242 | break; | |
a65e5efa | 243 | case S2MPS15X: |
0c5deb1e | 244 | case S2MPS14X: |
5281f94a | 245 | case S2MPS13X: |
0c5deb1e KK |
246 | ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2, |
247 | &val); | |
248 | val &= S2MPS_ALARM0_STATUS; | |
249 | break; | |
f8b23bbd KK |
250 | default: |
251 | return -EINVAL; | |
252 | } | |
253 | if (ret < 0) | |
254 | return ret; | |
255 | ||
256 | if (val) | |
257 | alarm->pending = 1; | |
258 | else | |
259 | alarm->pending = 0; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
8124c711 | 264 | static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info) |
5bccae6e SK |
265 | { |
266 | int ret; | |
267 | unsigned int data; | |
268 | ||
a83a793a | 269 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
5bccae6e SK |
270 | if (ret < 0) { |
271 | dev_err(info->dev, "failed to read update reg(%d)\n", ret); | |
272 | return ret; | |
273 | } | |
274 | ||
8ae83b6f | 275 | data |= info->regs->write_time_udr_mask; |
a65e5efa | 276 | |
a83a793a | 277 | ret = regmap_write(info->regmap, info->regs->udr_update, data); |
5bccae6e SK |
278 | if (ret < 0) { |
279 | dev_err(info->dev, "failed to write update reg(%d)\n", ret); | |
280 | return ret; | |
281 | } | |
282 | ||
d73238d4 | 283 | ret = s5m8767_wait_for_udr_update(info); |
5bccae6e SK |
284 | |
285 | return ret; | |
286 | } | |
287 | ||
8124c711 | 288 | static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info) |
5bccae6e SK |
289 | { |
290 | int ret; | |
291 | unsigned int data; | |
292 | ||
a83a793a | 293 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
5bccae6e SK |
294 | if (ret < 0) { |
295 | dev_err(info->dev, "%s: fail to read update reg(%d)\n", | |
296 | __func__, ret); | |
297 | return ret; | |
298 | } | |
299 | ||
8ae83b6f | 300 | data |= info->regs->write_alarm_udr_mask; |
0c5deb1e KK |
301 | switch (info->device_type) { |
302 | case S5M8763X: | |
303 | case S5M8767X: | |
304 | data &= ~S5M_RTC_TIME_EN_MASK; | |
305 | break; | |
a65e5efa | 306 | case S2MPS15X: |
0c5deb1e | 307 | case S2MPS14X: |
5281f94a | 308 | case S2MPS13X: |
8ae83b6f | 309 | /* No exceptions needed */ |
5281f94a | 310 | break; |
0c5deb1e KK |
311 | default: |
312 | return -EINVAL; | |
313 | } | |
5bccae6e | 314 | |
a83a793a | 315 | ret = regmap_write(info->regmap, info->regs->udr_update, data); |
5bccae6e SK |
316 | if (ret < 0) { |
317 | dev_err(info->dev, "%s: fail to write update reg(%d)\n", | |
318 | __func__, ret); | |
319 | return ret; | |
320 | } | |
321 | ||
d73238d4 | 322 | ret = s5m8767_wait_for_udr_update(info); |
5bccae6e | 323 | |
5281f94a KK |
324 | /* On S2MPS13 the AUDR is not auto-cleared */ |
325 | if (info->device_type == S2MPS13X) | |
a83a793a | 326 | regmap_update_bits(info->regmap, info->regs->udr_update, |
5281f94a KK |
327 | S2MPS13_RTC_AUDR_MASK, 0); |
328 | ||
5bccae6e SK |
329 | return ret; |
330 | } | |
331 | ||
332 | static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm) | |
333 | { | |
334 | tm->tm_sec = bcd2bin(data[RTC_SEC]); | |
335 | tm->tm_min = bcd2bin(data[RTC_MIN]); | |
336 | ||
337 | if (data[RTC_HOUR] & HOUR_12) { | |
338 | tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f); | |
339 | if (data[RTC_HOUR] & HOUR_PM) | |
340 | tm->tm_hour += 12; | |
341 | } else { | |
342 | tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f); | |
343 | } | |
344 | ||
345 | tm->tm_wday = data[RTC_WEEKDAY] & 0x07; | |
346 | tm->tm_mday = bcd2bin(data[RTC_DATE]); | |
347 | tm->tm_mon = bcd2bin(data[RTC_MONTH]); | |
348 | tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100; | |
349 | tm->tm_year -= 1900; | |
350 | } | |
351 | ||
352 | static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data) | |
353 | { | |
354 | data[RTC_SEC] = bin2bcd(tm->tm_sec); | |
355 | data[RTC_MIN] = bin2bcd(tm->tm_min); | |
356 | data[RTC_HOUR] = bin2bcd(tm->tm_hour); | |
357 | data[RTC_WEEKDAY] = tm->tm_wday; | |
358 | data[RTC_DATE] = bin2bcd(tm->tm_mday); | |
359 | data[RTC_MONTH] = bin2bcd(tm->tm_mon); | |
360 | data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100); | |
361 | data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100); | |
362 | } | |
363 | ||
364 | static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
365 | { | |
366 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 367 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
368 | int ret; |
369 | ||
8ae83b6f | 370 | if (info->regs->read_time_udr_mask) { |
0c5deb1e | 371 | ret = regmap_update_bits(info->regmap, |
a83a793a | 372 | info->regs->udr_update, |
8ae83b6f KK |
373 | info->regs->read_time_udr_mask, |
374 | info->regs->read_time_udr_mask); | |
0c5deb1e KK |
375 | if (ret) { |
376 | dev_err(dev, | |
377 | "Failed to prepare registers for time reading: %d\n", | |
378 | ret); | |
379 | return ret; | |
380 | } | |
381 | } | |
f8b23bbd KK |
382 | ret = regmap_bulk_read(info->regmap, info->regs->time, data, |
383 | info->regs->regs_count); | |
5bccae6e SK |
384 | if (ret < 0) |
385 | return ret; | |
386 | ||
387 | switch (info->device_type) { | |
388 | case S5M8763X: | |
389 | s5m8763_data_to_tm(data, tm); | |
390 | break; | |
391 | ||
392 | case S5M8767X: | |
a65e5efa | 393 | case S2MPS15X: |
0c5deb1e | 394 | case S2MPS14X: |
5281f94a | 395 | case S2MPS13X: |
5bccae6e SK |
396 | s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode); |
397 | break; | |
398 | ||
399 | default: | |
400 | return -EINVAL; | |
401 | } | |
402 | ||
5527842e | 403 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday); |
5bccae6e | 404 | |
22652ba7 | 405 | return 0; |
5bccae6e SK |
406 | } |
407 | ||
408 | static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
409 | { | |
410 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 411 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
412 | int ret = 0; |
413 | ||
414 | switch (info->device_type) { | |
415 | case S5M8763X: | |
416 | s5m8763_tm_to_data(tm, data); | |
417 | break; | |
418 | case S5M8767X: | |
a65e5efa | 419 | case S2MPS15X: |
0c5deb1e | 420 | case S2MPS14X: |
5281f94a | 421 | case S2MPS13X: |
5bccae6e SK |
422 | ret = s5m8767_tm_to_data(tm, data); |
423 | break; | |
424 | default: | |
425 | return -EINVAL; | |
426 | } | |
427 | ||
428 | if (ret < 0) | |
429 | return ret; | |
430 | ||
5527842e | 431 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday); |
5bccae6e | 432 | |
f8b23bbd KK |
433 | ret = regmap_raw_write(info->regmap, info->regs->time, data, |
434 | info->regs->regs_count); | |
5bccae6e SK |
435 | if (ret < 0) |
436 | return ret; | |
437 | ||
438 | ret = s5m8767_rtc_set_time_reg(info); | |
439 | ||
440 | return ret; | |
441 | } | |
442 | ||
443 | static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
444 | { | |
445 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 446 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
447 | unsigned int val; |
448 | int ret, i; | |
449 | ||
f8b23bbd KK |
450 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
451 | info->regs->regs_count); | |
5bccae6e SK |
452 | if (ret < 0) |
453 | return ret; | |
454 | ||
455 | switch (info->device_type) { | |
456 | case S5M8763X: | |
457 | s5m8763_data_to_tm(data, &alrm->time); | |
602cb5bb | 458 | ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val); |
5bccae6e SK |
459 | if (ret < 0) |
460 | return ret; | |
461 | ||
462 | alrm->enabled = !!val; | |
5bccae6e SK |
463 | break; |
464 | ||
465 | case S5M8767X: | |
a65e5efa | 466 | case S2MPS15X: |
0c5deb1e | 467 | case S2MPS14X: |
5281f94a | 468 | case S2MPS13X: |
5bccae6e | 469 | s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode); |
5bccae6e | 470 | alrm->enabled = 0; |
f8b23bbd | 471 | for (i = 0; i < info->regs->regs_count; i++) { |
5bccae6e SK |
472 | if (data[i] & ALARM_ENABLE_MASK) { |
473 | alrm->enabled = 1; | |
474 | break; | |
475 | } | |
476 | } | |
5bccae6e SK |
477 | break; |
478 | ||
479 | default: | |
480 | return -EINVAL; | |
481 | } | |
482 | ||
5527842e | 483 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday); |
f8b23bbd | 484 | |
f2581b1d | 485 | return s5m_check_peding_alarm_interrupt(info, alrm); |
5bccae6e SK |
486 | } |
487 | ||
488 | static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) | |
489 | { | |
756d5282 | 490 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
491 | int ret, i; |
492 | struct rtc_time tm; | |
493 | ||
f8b23bbd KK |
494 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
495 | info->regs->regs_count); | |
5bccae6e SK |
496 | if (ret < 0) |
497 | return ret; | |
498 | ||
499 | s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); | |
5527842e | 500 | dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday); |
5bccae6e SK |
501 | |
502 | switch (info->device_type) { | |
503 | case S5M8763X: | |
602cb5bb | 504 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0); |
5bccae6e SK |
505 | break; |
506 | ||
507 | case S5M8767X: | |
a65e5efa | 508 | case S2MPS15X: |
0c5deb1e | 509 | case S2MPS14X: |
5281f94a | 510 | case S2MPS13X: |
f8b23bbd | 511 | for (i = 0; i < info->regs->regs_count; i++) |
5bccae6e SK |
512 | data[i] &= ~ALARM_ENABLE_MASK; |
513 | ||
f8b23bbd KK |
514 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
515 | info->regs->regs_count); | |
5bccae6e SK |
516 | if (ret < 0) |
517 | return ret; | |
518 | ||
519 | ret = s5m8767_rtc_set_alarm_reg(info); | |
520 | ||
521 | break; | |
522 | ||
523 | default: | |
524 | return -EINVAL; | |
525 | } | |
526 | ||
527 | return ret; | |
528 | } | |
529 | ||
530 | static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | |
531 | { | |
532 | int ret; | |
756d5282 | 533 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
534 | u8 alarm0_conf; |
535 | struct rtc_time tm; | |
536 | ||
f8b23bbd KK |
537 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
538 | info->regs->regs_count); | |
5bccae6e SK |
539 | if (ret < 0) |
540 | return ret; | |
541 | ||
542 | s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); | |
5527842e | 543 | dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday); |
5bccae6e SK |
544 | |
545 | switch (info->device_type) { | |
546 | case S5M8763X: | |
547 | alarm0_conf = 0x77; | |
602cb5bb | 548 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf); |
5bccae6e SK |
549 | break; |
550 | ||
551 | case S5M8767X: | |
a65e5efa | 552 | case S2MPS15X: |
0c5deb1e | 553 | case S2MPS14X: |
5281f94a | 554 | case S2MPS13X: |
5bccae6e SK |
555 | data[RTC_SEC] |= ALARM_ENABLE_MASK; |
556 | data[RTC_MIN] |= ALARM_ENABLE_MASK; | |
557 | data[RTC_HOUR] |= ALARM_ENABLE_MASK; | |
558 | data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK; | |
559 | if (data[RTC_DATE] & 0x1f) | |
560 | data[RTC_DATE] |= ALARM_ENABLE_MASK; | |
561 | if (data[RTC_MONTH] & 0xf) | |
562 | data[RTC_MONTH] |= ALARM_ENABLE_MASK; | |
563 | if (data[RTC_YEAR1] & 0x7f) | |
564 | data[RTC_YEAR1] |= ALARM_ENABLE_MASK; | |
565 | ||
f8b23bbd KK |
566 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
567 | info->regs->regs_count); | |
5bccae6e SK |
568 | if (ret < 0) |
569 | return ret; | |
570 | ret = s5m8767_rtc_set_alarm_reg(info); | |
571 | ||
572 | break; | |
573 | ||
574 | default: | |
575 | return -EINVAL; | |
576 | } | |
577 | ||
578 | return ret; | |
579 | } | |
580 | ||
581 | static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
582 | { | |
583 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
756d5282 | 584 | u8 data[RTC_MAX_NUM_TIME_REGS]; |
5bccae6e SK |
585 | int ret; |
586 | ||
587 | switch (info->device_type) { | |
588 | case S5M8763X: | |
589 | s5m8763_tm_to_data(&alrm->time, data); | |
590 | break; | |
591 | ||
592 | case S5M8767X: | |
a65e5efa | 593 | case S2MPS15X: |
0c5deb1e | 594 | case S2MPS14X: |
5281f94a | 595 | case S2MPS13X: |
5bccae6e SK |
596 | s5m8767_tm_to_data(&alrm->time, data); |
597 | break; | |
598 | ||
599 | default: | |
600 | return -EINVAL; | |
601 | } | |
602 | ||
5527842e | 603 | dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday); |
5bccae6e SK |
604 | |
605 | ret = s5m_rtc_stop_alarm(info); | |
606 | if (ret < 0) | |
607 | return ret; | |
608 | ||
f8b23bbd KK |
609 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
610 | info->regs->regs_count); | |
5bccae6e SK |
611 | if (ret < 0) |
612 | return ret; | |
613 | ||
614 | ret = s5m8767_rtc_set_alarm_reg(info); | |
615 | if (ret < 0) | |
616 | return ret; | |
617 | ||
618 | if (alrm->enabled) | |
619 | ret = s5m_rtc_start_alarm(info); | |
620 | ||
621 | return ret; | |
622 | } | |
623 | ||
624 | static int s5m_rtc_alarm_irq_enable(struct device *dev, | |
625 | unsigned int enabled) | |
626 | { | |
627 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
628 | ||
629 | if (enabled) | |
630 | return s5m_rtc_start_alarm(info); | |
631 | else | |
632 | return s5m_rtc_stop_alarm(info); | |
633 | } | |
634 | ||
635 | static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data) | |
636 | { | |
637 | struct s5m_rtc_info *info = data; | |
638 | ||
639 | rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); | |
640 | ||
641 | return IRQ_HANDLED; | |
642 | } | |
643 | ||
644 | static const struct rtc_class_ops s5m_rtc_ops = { | |
645 | .read_time = s5m_rtc_read_time, | |
646 | .set_time = s5m_rtc_set_time, | |
647 | .read_alarm = s5m_rtc_read_alarm, | |
648 | .set_alarm = s5m_rtc_set_alarm, | |
649 | .alarm_irq_enable = s5m_rtc_alarm_irq_enable, | |
650 | }; | |
651 | ||
5bccae6e SK |
652 | static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) |
653 | { | |
654 | u8 data[2]; | |
5bccae6e | 655 | int ret; |
5bccae6e | 656 | |
0c5deb1e KK |
657 | switch (info->device_type) { |
658 | case S5M8763X: | |
659 | case S5M8767X: | |
660 | /* UDR update time. Default of 7.32 ms is too long. */ | |
661 | ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON, | |
662 | S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US); | |
663 | if (ret < 0) | |
664 | dev_err(info->dev, "%s: fail to change UDR time: %d\n", | |
665 | __func__, ret); | |
0c5f5d9a | 666 | |
0c5deb1e KK |
667 | /* Set RTC control register : Binary mode, 24hour mode */ |
668 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
669 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
670 | ||
671 | ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2); | |
672 | break; | |
673 | ||
a65e5efa | 674 | case S2MPS15X: |
0c5deb1e | 675 | case S2MPS14X: |
5281f94a | 676 | case S2MPS13X: |
0c5deb1e KK |
677 | data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
678 | ret = regmap_write(info->regmap, info->regs->ctrl, data[0]); | |
ff02c044 JS |
679 | if (ret < 0) |
680 | break; | |
681 | ||
682 | /* | |
683 | * Should set WUDR & (RUDR or AUDR) bits to high after writing | |
684 | * RTC_CTRL register like writing Alarm registers. We can't find | |
685 | * the description from datasheet but vendor code does that | |
686 | * really. | |
687 | */ | |
688 | ret = s5m8767_rtc_set_alarm_reg(info); | |
0c5deb1e KK |
689 | break; |
690 | ||
691 | default: | |
692 | return -EINVAL; | |
693 | } | |
5bccae6e SK |
694 | |
695 | info->rtc_24hr_mode = 1; | |
5bccae6e SK |
696 | if (ret < 0) { |
697 | dev_err(info->dev, "%s: fail to write controlm reg(%d)\n", | |
698 | __func__, ret); | |
699 | return ret; | |
700 | } | |
701 | ||
5bccae6e SK |
702 | return ret; |
703 | } | |
704 | ||
705 | static int s5m_rtc_probe(struct platform_device *pdev) | |
706 | { | |
707 | struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent); | |
5bccae6e | 708 | struct s5m_rtc_info *info; |
e349c910 | 709 | const struct regmap_config *regmap_cfg; |
a0347f20 | 710 | int ret, alarm_irq; |
5bccae6e | 711 | |
5bccae6e SK |
712 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
713 | if (!info) | |
714 | return -ENOMEM; | |
715 | ||
94f91922 | 716 | switch (platform_get_device_id(pdev)->driver_data) { |
a65e5efa | 717 | case S2MPS15X: |
8ae83b6f KK |
718 | regmap_cfg = &s2mps14_rtc_regmap_config; |
719 | info->regs = &s2mps15_rtc_regs; | |
720 | alarm_irq = S2MPS14_IRQ_RTCA0; | |
721 | break; | |
e349c910 | 722 | case S2MPS14X: |
8ae83b6f KK |
723 | regmap_cfg = &s2mps14_rtc_regmap_config; |
724 | info->regs = &s2mps14_rtc_regs; | |
725 | alarm_irq = S2MPS14_IRQ_RTCA0; | |
726 | break; | |
5281f94a | 727 | case S2MPS13X: |
e349c910 | 728 | regmap_cfg = &s2mps14_rtc_regmap_config; |
8ae83b6f | 729 | info->regs = &s2mps13_rtc_regs; |
a0347f20 | 730 | alarm_irq = S2MPS14_IRQ_RTCA0; |
e349c910 KK |
731 | break; |
732 | case S5M8763X: | |
733 | regmap_cfg = &s5m_rtc_regmap_config; | |
f8b23bbd | 734 | info->regs = &s5m_rtc_regs; |
a0347f20 | 735 | alarm_irq = S5M8763_IRQ_ALARM0; |
e349c910 KK |
736 | break; |
737 | case S5M8767X: | |
738 | regmap_cfg = &s5m_rtc_regmap_config; | |
f8b23bbd | 739 | info->regs = &s5m_rtc_regs; |
a0347f20 | 740 | alarm_irq = S5M8767_IRQ_RTCA1; |
e349c910 KK |
741 | break; |
742 | default: | |
94f91922 KK |
743 | dev_err(&pdev->dev, |
744 | "Device type %lu is not supported by RTC driver\n", | |
745 | platform_get_device_id(pdev)->driver_data); | |
e349c910 KK |
746 | return -ENODEV; |
747 | } | |
748 | ||
7db7ad08 BG |
749 | info->i2c = devm_i2c_new_dummy_device(&pdev->dev, s5m87xx->i2c->adapter, |
750 | RTC_I2C_ADDR); | |
aae364d2 | 751 | if (IS_ERR(info->i2c)) { |
e349c910 | 752 | dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n"); |
aae364d2 | 753 | return PTR_ERR(info->i2c); |
e349c910 KK |
754 | } |
755 | ||
756 | info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg); | |
757 | if (IS_ERR(info->regmap)) { | |
758 | ret = PTR_ERR(info->regmap); | |
759 | dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n", | |
760 | ret); | |
7db7ad08 | 761 | return ret; |
e349c910 KK |
762 | } |
763 | ||
5bccae6e SK |
764 | info->dev = &pdev->dev; |
765 | info->s5m87xx = s5m87xx; | |
94f91922 | 766 | info->device_type = platform_get_device_id(pdev)->driver_data; |
5bccae6e | 767 | |
b7d5b9a9 BZ |
768 | if (s5m87xx->irq_data) { |
769 | info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq); | |
770 | if (info->irq <= 0) { | |
b7d5b9a9 | 771 | dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n", |
a0347f20 | 772 | alarm_irq); |
7db7ad08 | 773 | return -EINVAL; |
b7d5b9a9 | 774 | } |
5bccae6e SK |
775 | } |
776 | ||
777 | platform_set_drvdata(pdev, info); | |
778 | ||
779 | ret = s5m8767_rtc_init_reg(info); | |
3be95d27 BG |
780 | if (ret) |
781 | return ret; | |
5bccae6e | 782 | |
dae68c6b | 783 | info->rtc_dev = devm_rtc_allocate_device(&pdev->dev); |
7db7ad08 BG |
784 | if (IS_ERR(info->rtc_dev)) |
785 | return PTR_ERR(info->rtc_dev); | |
5bccae6e | 786 | |
dae68c6b AB |
787 | info->rtc_dev->ops = &s5m_rtc_ops; |
788 | ||
fffd603a AB |
789 | if (info->device_type == S5M8763X) { |
790 | info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_0000; | |
791 | info->rtc_dev->range_max = RTC_TIMESTAMP_END_9999; | |
792 | } else { | |
793 | info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; | |
794 | info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099; | |
795 | } | |
796 | ||
b7d5b9a9 | 797 | if (!info->irq) { |
1ed4dba2 AB |
798 | clear_bit(RTC_FEATURE_ALARM, info->rtc_dev->features); |
799 | } else { | |
800 | ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL, | |
801 | s5m_rtc_alarm_irq, 0, "rtc-alarm0", | |
802 | info); | |
803 | if (ret < 0) { | |
804 | dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", | |
805 | info->irq, ret); | |
806 | return ret; | |
807 | } | |
308247d2 | 808 | device_init_wakeup(&pdev->dev, 1); |
e349c910 KK |
809 | } |
810 | ||
1ed4dba2 | 811 | return devm_rtc_register_device(info->rtc_dev); |
e349c910 KK |
812 | } |
813 | ||
11ba5a1e | 814 | #ifdef CONFIG_PM_SLEEP |
222ead7f KK |
815 | static int s5m_rtc_resume(struct device *dev) |
816 | { | |
817 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
818 | int ret = 0; | |
819 | ||
b7d5b9a9 | 820 | if (info->irq && device_may_wakeup(dev)) |
222ead7f KK |
821 | ret = disable_irq_wake(info->irq); |
822 | ||
823 | return ret; | |
824 | } | |
825 | ||
826 | static int s5m_rtc_suspend(struct device *dev) | |
827 | { | |
828 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
829 | int ret = 0; | |
830 | ||
b7d5b9a9 | 831 | if (info->irq && device_may_wakeup(dev)) |
222ead7f KK |
832 | ret = enable_irq_wake(info->irq); |
833 | ||
834 | return ret; | |
835 | } | |
11ba5a1e | 836 | #endif /* CONFIG_PM_SLEEP */ |
222ead7f KK |
837 | |
838 | static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); | |
839 | ||
5bccae6e | 840 | static const struct platform_device_id s5m_rtc_id[] = { |
0c5deb1e | 841 | { "s5m-rtc", S5M8767X }, |
5281f94a | 842 | { "s2mps13-rtc", S2MPS13X }, |
0c5deb1e | 843 | { "s2mps14-rtc", S2MPS14X }, |
a65e5efa | 844 | { "s2mps15-rtc", S2MPS15X }, |
45cd15e6 | 845 | { }, |
5bccae6e | 846 | }; |
63074cc3 | 847 | MODULE_DEVICE_TABLE(platform, s5m_rtc_id); |
5bccae6e SK |
848 | |
849 | static struct platform_driver s5m_rtc_driver = { | |
850 | .driver = { | |
851 | .name = "s5m-rtc", | |
222ead7f | 852 | .pm = &s5m_rtc_pm_ops, |
5bccae6e SK |
853 | }, |
854 | .probe = s5m_rtc_probe, | |
5bccae6e SK |
855 | .id_table = s5m_rtc_id, |
856 | }; | |
857 | ||
858 | module_platform_driver(s5m_rtc_driver); | |
859 | ||
860 | /* Module information */ | |
861 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | |
0c5deb1e | 862 | MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver"); |
5bccae6e SK |
863 | MODULE_LICENSE("GPL"); |
864 | MODULE_ALIAS("platform:s5m-rtc"); |