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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
2f82af08 | 12 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
13 | * Andrew Christian <andrew.christian@hp.com> |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/rtc.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/interrupt.h> | |
3888c090 | 30 | #include <linux/slab.h> |
a0164a57 | 31 | #include <linux/string.h> |
e842f1c8 | 32 | #include <linux/pm.h> |
a0164a57 | 33 | #include <linux/bitops.h> |
e842f1c8 | 34 | |
a09e64fb | 35 | #include <mach/hardware.h> |
e842f1c8 | 36 | #include <asm/irq.h> |
e842f1c8 | 37 | |
3888c090 | 38 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
a0164a57 RK |
39 | #include <mach/regs-rtc.h> |
40 | #endif | |
41 | ||
a404ad1f | 42 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 43 | #define RTC_DEF_TRIM 0 |
3888c090 | 44 | #define RTC_FREQ 1024 |
a0164a57 | 45 | |
3888c090 HZ |
46 | struct sa1100_rtc { |
47 | spinlock_t lock; | |
48 | int irq_1hz; | |
49 | int irq_alarm; | |
50 | struct rtc_device *rtc; | |
51 | }; | |
a0164a57 | 52 | |
7d12e780 | 53 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 | 54 | { |
3888c090 HZ |
55 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
56 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
57 | unsigned int rtsr; |
58 | unsigned long events = 0; | |
59 | ||
3888c090 | 60 | spin_lock(&info->lock); |
e842f1c8 | 61 | |
a0164a57 | 62 | rtsr = RTSR; |
e842f1c8 | 63 | /* clear interrupt sources */ |
a0164a57 | 64 | RTSR = 0; |
7decaa55 MRJ |
65 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
66 | * See also the comments in sa1100_rtc_probe(). */ | |
67 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
68 | /* This is the original code, before there was the if test | |
69 | * above. This code does not clear interrupts that were not | |
70 | * enabled. */ | |
a0164a57 | 71 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); |
7decaa55 MRJ |
72 | } else { |
73 | /* For some reason, it is possible to enter this routine | |
74 | * without interruptions enabled, it has been tested with | |
75 | * several units (Bug in SA11xx chip?). | |
76 | * | |
77 | * This situation leads to an infinite "loop" of interrupt | |
78 | * routine calling and as a result the processor seems to | |
79 | * lock on its first call to open(). */ | |
a0164a57 | 80 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 81 | } |
e842f1c8 RP |
82 | |
83 | /* clear alarm interrupt if it has occurred */ | |
84 | if (rtsr & RTSR_AL) | |
85 | rtsr &= ~RTSR_ALE; | |
a0164a57 | 86 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); |
e842f1c8 RP |
87 | |
88 | /* update irq data & counter */ | |
89 | if (rtsr & RTSR_AL) | |
90 | events |= RTC_AF | RTC_IRQF; | |
91 | if (rtsr & RTSR_HZ) | |
92 | events |= RTC_UF | RTC_IRQF; | |
93 | ||
a0164a57 | 94 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 95 | |
3888c090 | 96 | spin_unlock(&info->lock); |
e842f1c8 RP |
97 | |
98 | return IRQ_HANDLED; | |
99 | } | |
100 | ||
e842f1c8 RP |
101 | static int sa1100_rtc_open(struct device *dev) |
102 | { | |
3888c090 HZ |
103 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
104 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
105 | int ret; |
106 | ||
3888c090 | 107 | ret = request_irq(info->irq_1hz, sa1100_rtc_interrupt, IRQF_DISABLED, |
a0164a57 | 108 | "rtc 1Hz", dev); |
e842f1c8 | 109 | if (ret) { |
3888c090 | 110 | dev_err(dev, "IRQ %d already in use.\n", info->irq_1hz); |
e842f1c8 RP |
111 | goto fail_ui; |
112 | } | |
3888c090 | 113 | ret = request_irq(info->irq_alarm, sa1100_rtc_interrupt, IRQF_DISABLED, |
a0164a57 | 114 | "rtc Alrm", dev); |
e842f1c8 | 115 | if (ret) { |
3888c090 | 116 | dev_err(dev, "IRQ %d already in use.\n", info->irq_alarm); |
e842f1c8 RP |
117 | goto fail_ai; |
118 | } | |
a0164a57 RK |
119 | rtc->max_user_freq = RTC_FREQ; |
120 | rtc_irq_set_freq(rtc, NULL, RTC_FREQ); | |
d2ccb52d | 121 | |
e842f1c8 RP |
122 | return 0; |
123 | ||
e842f1c8 | 124 | fail_ai: |
3888c090 | 125 | free_irq(info->irq_1hz, dev); |
e842f1c8 RP |
126 | fail_ui: |
127 | return ret; | |
128 | } | |
129 | ||
130 | static void sa1100_rtc_release(struct device *dev) | |
131 | { | |
3888c090 HZ |
132 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
133 | ||
134 | spin_lock_irq(&info->lock); | |
a0164a57 | 135 | RTSR = 0; |
3888c090 | 136 | spin_unlock_irq(&info->lock); |
e842f1c8 | 137 | |
3888c090 HZ |
138 | free_irq(info->irq_alarm, dev); |
139 | free_irq(info->irq_1hz, dev); | |
e842f1c8 RP |
140 | } |
141 | ||
16380c15 JS |
142 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
143 | { | |
3888c090 HZ |
144 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
145 | ||
146 | spin_lock_irq(&info->lock); | |
16380c15 | 147 | if (enabled) |
a0164a57 | 148 | RTSR |= RTSR_ALE; |
16380c15 | 149 | else |
a0164a57 | 150 | RTSR &= ~RTSR_ALE; |
3888c090 | 151 | spin_unlock_irq(&info->lock); |
16380c15 JS |
152 | return 0; |
153 | } | |
154 | ||
e842f1c8 RP |
155 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
156 | { | |
a0164a57 | 157 | rtc_time_to_tm(RCNR, tm); |
e842f1c8 RP |
158 | return 0; |
159 | } | |
160 | ||
161 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
162 | { | |
163 | unsigned long time; | |
164 | int ret; | |
165 | ||
166 | ret = rtc_tm_to_time(tm, &time); | |
167 | if (ret == 0) | |
a0164a57 | 168 | RCNR = time; |
e842f1c8 RP |
169 | return ret; |
170 | } | |
171 | ||
172 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
173 | { | |
a0164a57 | 174 | u32 rtsr; |
32b49da4 | 175 | |
a0164a57 | 176 | rtsr = RTSR; |
32b49da4 DB |
177 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
178 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
179 | return 0; |
180 | } | |
181 | ||
182 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
183 | { | |
3888c090 | 184 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
1d8c38c3 | 185 | unsigned long time; |
a0164a57 | 186 | int ret; |
e842f1c8 | 187 | |
3888c090 | 188 | spin_lock_irq(&info->lock); |
1d8c38c3 HZ |
189 | ret = rtc_tm_to_time(&alrm->time, &time); |
190 | if (ret != 0) | |
191 | goto out; | |
192 | RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL); | |
193 | RTAR = time; | |
194 | if (alrm->enabled) | |
195 | RTSR |= RTSR_ALE; | |
196 | else | |
197 | RTSR &= ~RTSR_ALE; | |
198 | out: | |
3888c090 | 199 | spin_unlock_irq(&info->lock); |
e842f1c8 | 200 | |
a0164a57 | 201 | return ret; |
e842f1c8 RP |
202 | } |
203 | ||
204 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
205 | { | |
a0164a57 RK |
206 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR); |
207 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR); | |
e842f1c8 RP |
208 | |
209 | return 0; | |
210 | } | |
211 | ||
ff8371ac | 212 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 | 213 | .open = sa1100_rtc_open, |
e842f1c8 | 214 | .release = sa1100_rtc_release, |
e842f1c8 RP |
215 | .read_time = sa1100_rtc_read_time, |
216 | .set_time = sa1100_rtc_set_time, | |
217 | .read_alarm = sa1100_rtc_read_alarm, | |
218 | .set_alarm = sa1100_rtc_set_alarm, | |
219 | .proc = sa1100_rtc_proc, | |
16380c15 | 220 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
221 | }; |
222 | ||
223 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
224 | { | |
a0164a57 | 225 | struct rtc_device *rtc; |
3888c090 HZ |
226 | struct sa1100_rtc *info; |
227 | int irq_1hz, irq_alarm, ret = 0; | |
228 | ||
229 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); | |
230 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); | |
231 | if (irq_1hz < 0 || irq_alarm < 0) | |
232 | return -ENODEV; | |
233 | ||
234 | info = kzalloc(sizeof(struct sa1100_rtc), GFP_KERNEL); | |
235 | if (!info) | |
236 | return -ENOMEM; | |
237 | info->irq_1hz = irq_1hz; | |
238 | info->irq_alarm = irq_alarm; | |
239 | spin_lock_init(&info->lock); | |
240 | platform_set_drvdata(pdev, info); | |
e842f1c8 RP |
241 | |
242 | /* | |
243 | * According to the manual we should be able to let RTTR be zero | |
244 | * and then a default diviser for a 32.768KHz clock is used. | |
245 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
246 | * If the clock divider is uninitialized then reset it to the | |
247 | * default value to get the 1Hz clock. | |
248 | */ | |
a0164a57 RK |
249 | if (RTTR == 0) { |
250 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
251 | dev_warn(&pdev->dev, "warning: " | |
252 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 253 | /* The current RTC value probably doesn't make sense either */ |
a0164a57 | 254 | RCNR = 0; |
e842f1c8 RP |
255 | } |
256 | ||
e5a2c9cc UL |
257 | device_init_wakeup(&pdev->dev, 1); |
258 | ||
a0164a57 RK |
259 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, |
260 | THIS_MODULE); | |
261 | ||
3888c090 HZ |
262 | if (IS_ERR(rtc)) { |
263 | ret = PTR_ERR(rtc); | |
264 | goto err_dev; | |
265 | } | |
266 | info->rtc = rtc; | |
a0164a57 | 267 | |
7decaa55 MRJ |
268 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
269 | * See also the comments in sa1100_rtc_interrupt(). | |
270 | * | |
271 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
272 | * interrupt pending, even though interrupts were never enabled. | |
273 | * In this case, this bit it must be reset before enabling | |
274 | * interruptions to avoid a nonexistent interrupt to occur. | |
275 | * | |
276 | * In principle, the same problem would apply to bit 0, although it has | |
277 | * never been observed to happen. | |
278 | * | |
279 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
280 | * If the issue is not addressed here, in the times when the processor | |
281 | * wakes up with the bit set there will be one spurious interrupt. | |
282 | * | |
283 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
284 | * safe side, once the condition that lead to this strange | |
285 | * initialization is unknown and could in principle happen during | |
286 | * normal processing. | |
287 | * | |
288 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
289 | * the corresponding bits in RTSR. */ | |
a0164a57 | 290 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 291 | |
e842f1c8 | 292 | return 0; |
3888c090 HZ |
293 | err_dev: |
294 | platform_set_drvdata(pdev, NULL); | |
295 | kfree(info); | |
296 | return ret; | |
e842f1c8 RP |
297 | } |
298 | ||
299 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
300 | { | |
3888c090 | 301 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
a0164a57 | 302 | |
3888c090 HZ |
303 | if (info) { |
304 | rtc_device_unregister(info->rtc); | |
305 | platform_set_drvdata(pdev, NULL); | |
306 | kfree(info); | |
307 | } | |
e842f1c8 RP |
308 | |
309 | return 0; | |
310 | } | |
311 | ||
6bc54e69 | 312 | #ifdef CONFIG_PM |
5d027cd2 | 313 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 314 | { |
3888c090 | 315 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 316 | if (device_may_wakeup(dev)) |
3888c090 | 317 | enable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
318 | return 0; |
319 | } | |
320 | ||
5d027cd2 | 321 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 322 | { |
3888c090 | 323 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 324 | if (device_may_wakeup(dev)) |
3888c090 | 325 | disable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
326 | return 0; |
327 | } | |
5d027cd2 | 328 | |
47145210 | 329 | static const struct dev_pm_ops sa1100_rtc_pm_ops = { |
5d027cd2 HZ |
330 | .suspend = sa1100_rtc_suspend, |
331 | .resume = sa1100_rtc_resume, | |
332 | }; | |
6bc54e69 RK |
333 | #endif |
334 | ||
e842f1c8 RP |
335 | static struct platform_driver sa1100_rtc_driver = { |
336 | .probe = sa1100_rtc_probe, | |
337 | .remove = sa1100_rtc_remove, | |
338 | .driver = { | |
5d027cd2 HZ |
339 | .name = "sa1100-rtc", |
340 | #ifdef CONFIG_PM | |
341 | .pm = &sa1100_rtc_pm_ops, | |
342 | #endif | |
e842f1c8 RP |
343 | }, |
344 | }; | |
345 | ||
0c4eae66 | 346 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
347 | |
348 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
349 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
350 | MODULE_LICENSE("GPL"); | |
ad28a07b | 351 | MODULE_ALIAS("platform:sa1100-rtc"); |